Tag Archives: letter-wafer-tech

A lithographic method for TSV alignment to embedded targets was evaluated using in-line stepper self metrology, with TIS correction.

BY WARREN W. FLACK, Veeco Instruments, Plainview, NY and JOHN SLABBEKOORN, imec, Leuven, Belgium

Demand for consumer product related devices including backside illuminated image sensors, interposers and 3D memory is driving advanced packaging using through silicon via (TSV) [1]. The various process flows for TSV processing (via first, via middle and via last) affect the relative levels of integration required at the foundry and OSAT manufacturing locations. Via last provides distinct advantages for process integration, including minimizing the impact on back end of line (BEOL) processing, and does not require a TSV reveal for the wafer thinning process. Scaling the diameter of the TSV significantly improves the system performance and cost. Current via last diameters are approximately 30μm with advanced TSV designs at 5 μm [2].

Lithography is one of the critical factors affecting overall device performance and yield for via last TSV fabrication [2]. One of the unique lithography requirements for via last patterning is the need for back-to-front side wafer alignment. With smaller TSV diameters, the back-to- front overlay becomes a critical parameter because via landing pads on the first level metal must be large enough to include both TSV critical dimension (CD) and overlay variations, as shown in FIGURE 1. Reducing the size of via landing pads provide significant advantages for device design and final chip size. This study evaluates 5μm TSVs with overlay performance of ≤ 750nm.

Alignment, illumination and metrology

Lithography was performed using an advanced packaging 1X stepper with a 0.16 numerical aperture (NA) Wynne Dyson lens. This stepper has a dual side alignment (DSA) system which uses infrared (IR) illumination to view metal targets through a thinned silicon wafer [3]. For the purposes of this study and its results, the wafer device side is referred to as the “front side” and the silicon side is referred to as the “back side.” The side facing up on the lithography tool is the back side of the TSV wafer, as shown in FIGURE 2.

The top IR illumination method for viewing embedded alignment targets, shown in Fig. 2, provides practical advantages for integration with stepper lithography. Since the illumination and imaging are directed from the top, this method does not interfere with the design of the wafer chuck, and does not constrain alignment target positioning on the wafer. The top IR alignment method illuminates the alignment target from the back side using an IR wavelength capable of transmitting through silicon (shown as light green in FIGURE 2) and the process films (shown in blue). In this configuration the target (shown in orange) needs to be made from an IR reflective material such as metal for optimal contrast. The alignment sequence requires that the wafer move in the Z axis in order to shift alignment focus from the wafer surface to the embedded target.

Back-to-front side registration was measured using a metrology package on the lithography tool which uses the DSA alignment system. This stepper self metrology package (DSA-SSM) includes routines to diagnose and compensate for measurement error from having features at different heights. For each measurement site the optical metrology system needs to move the focus in Z between the resist feature and the embedded feature. Therefore angular differences between the Z axis of motion, the optical axis of the alignment camera, and the wafer normal will contribute to measurement error for the tool [3]. The quality of the wafer stage motion is also very important because a significant pitch and roll signature would result in a location dependent error for embedded feature measurement, which would complicate the analysis.

If the measurement operation is repeatable and consistent across the wafer, then a constant error coming from the measurement tool, commonly referred to as tool induced shift (TIS), can be characterized using the method of TIS calibration, which incorporates measurements at 0 and 180 degree orientations. The TIS error—or calibration—is calculated by dividing the sum of offsets for the two orientations by two [4]. While the TIS calibration is effective for many types of measurements for planar metrology, for embedded feature metrology, the quality of measurement and calibration also depend on the quality and repeatability of wafer positioning, including tilt. In previous studies, the registration data obtained from the current method were self consistent and proved to be an effective inspection method [3, 5]. However given the dependencies affecting TIS calibration for embedded feature metrology, it is desirable to confirm the registration result using an alternate metrology method [5]. In order to independently verify the DSA-SSM, overlay data dedicated electrical structures were designed and placed on the test chip.

Electrical verification of TSV alignment is performed after complete processing of the test chip and relies on the landing position of a TSV on a fork-to-fork test structure in the embedded metal 1 (damascene metal). When the TSV processing is complete the copper filled TSV will make contact with metal 1. The TSV creates a short between the two sets of metal forks, allowing measurement of two resistance values which can be translated into edge measurements. For the case of ideal TSV alignment, the two resistances are equal. The measurement resolution of the electrical structure is limited by the pitch of the fork branches. In this study resolution is enhanced by creating structures with four different fork pitches. A similar fork-to-fork structure rotated 90 degrees is used for the Y alignment. Using this approach both overlay error and size of the TSV in both X and Y can be electrically determined [6].

Experimental methods

This study scrutinizes image placement performance by examining DSA optical metrology repeatability after TSV lithography, and then comparing this optical registration data with final electrical registration data.

The TSV-last process begins with a 300mm device wafer with metal 1, temporarily bonded to a carrier for mechanical support as shown in FIGURE 3. The back side of the silicon device wafer (light green) is thinned by grinding and then polished smooth by chemical mechanical planarization (CMP). The TSV is imaged in photoresist (red) and etched through the thinned silicon layer. FIGURE 3 depicts the complete process flow including the TSV, STI and PMD etch, TSV fill, redis- tribution layer (RDL) and de-bonding from carrier. The aligned TSV structure must land completely on the metal 1 pad (dark blue).

TSV lithography is done with a stepper equipped with DSA. The photoresist is a gh-line novolac based positive- tone material requiring 1250mJ/cm2 exposure dose with a thickness of 7.5μm [5]. The TSV diameter is 5μm, and the silicon thickness is 50μm. TSV etching of the silicon is performed by Bosch etching [7]. Tight control of lithography and TSV etching is required to insure that vias land completely on metal 1 pads, as shown in FIGURE 1.

Acceptable features for DSA-SSM metrology need to fit the via process requirements for integration. Since the TSV etch process is very sensitive to pattern size and density, the TSV layer is restricted to one size of via, and the DSA-SSM measurement structure is constructed using this shape. The design of the DSA-SSM measurement structure uses a cluster of 5μm vias with unique grouping and clocked rotation to avoid confusion with adjacent TSV device patterns during alignment.

FIGURE 4 shows two different focus offsets of DSA camera images of the overlay structure. For this structure, the reference metal 1 feature (outlined by the blue ring) and the resist pattern feature (outlined by the red ring) are not in the same focal plane. For a silicon thickness of 50μm, focusing on one feature will render the other feature out of focus, requiring each feature to have its own focus offset, which is specified in the metrology measurement recipe.

Optical registration process control

This study leveraged a sampling plan of 23 lithography fields with 5 measurements per field, resulting in a total of 115 measurements per wafer. Since the full wafer layout contains 262 fields, this sampling plan provides a good statistical sample for monitoring linear grid and intrafield parameters.

In the initial run, the overlay settings were optimized using the DSA-SSM metrology feedback and then the parameters were fixed to investigate overlay stability over a nine-week period. Trend charts for mean and 3σ for seven TSV lots are shown in FIGURE 5. Each measurement lot consists of 8 wafers, with 115 measure- ments per wafer, and all data is corrected for TIS on a per lot basis using measurements of a single wafer at 0 and 180 degree orientations [3]. The lot 3σ is consistently less than 600nm over the nine-week period. There appears to be a consistent small Y mean error (blue diamond) that could be adjusted to improve subsequent overlay results. With a Y mean correction applied, the registration data shows mean plus 3σ ≤ 600nm.

Validating TSV alignment and in-line optical metrology

Two TSV last test chip wafers were completely processed to the stage that they can be electrically measured. TABLE 1 shows the registration numbers confirming a good match between the two metrology methods. It is important to note that an extra translation step is performed between the optical and the electrical measurement: the TSV etch.

In this analysis the TSV etch is assumed to be perfectly vertical. From the data we can conclude that the TSV etch is indeed vertical enough not to interfere with the overlay data. Otherwise this would show as translation or scaling effects between the two metrology methods.

Conclusions

The lithographic method for TSV alignment to embedded targets was evaluated using in-line stepper self metrology, with TIS correction. Registration data was collected over a nine-week period to characterize the stability of TSV alignment. With corrections applied, the registration data demonstrates mean plus 3σ ≤ 600nm. The in-line optical registration data was then correlated to detailed electrical measurements performed on the same wafers at the end of the process to provide independent assessment of the accuracy of the optical data. Good correlation between optical and electrical data confirms the accuracy of the in-line optical metrology method, and also confirms that the TSV etch through 50μm thick silicon is vertical.

References

1. Vardaman, J. et. al., TechSearch International: Advanced Packaging Update, July 2016.
2. Van Huylenbroeck, S. et. al., “Small Pitch High Aspect Ratio Via Last TSV Module”, The 66th Electronic Components and Technology Conference, Los Vegas, NV, May 2016.
3. Flack, W. et. al., “Optimization of Through Si Via Last Lithography for 3D Packaging”, Twelfth International Wafer- Level Packaging Conference, San Jose, CA, October 2015.
4. Preil, M. et. al, “Improving the Accuracy of Overlay Measurements through Reduction of Tool and Wafer Induced Shifts”, Metrology, Inspection, and Process Control for Microlithography Proceedings, SPIE 3050, 1997.
5. Flack, W. et. al., “Verification of Back-to-Front Side Alignment for Advanced Packaging”, Ninth Interna- tional Wafer-Level Packaging Conference, Santa Clara, CA, November. 2012.
6. Flack, W. et.al., “Overlay Performance of Through Si Via Last Lithography for 3D Packaging”, 18th Electronics Packaging Technology Conference, Singapore, December 2016
7. Slabbekoorn, J. et. al, “Bosch Process Characterization For Donut TSV’s” Eleventh International Wafer-Level Packaging Conference, Santa Clara, CA, November 2014.

Materials that are hybrid constructions (combining organic and inorganic precursors) and quasi-two-dimensional (with malleable and highly compactable molecular structures) are on the rise in several technological applications, such as the fabrication of ever-smaller optoelectronic devices.

An article published in the journal Physical Review B describes a study in this field resulting from the doctoral research of Diana Meneses Gustin and Luís Cabral, both supervised by Victor Lopez Richard, a professor at the Federal University of São Carlos (UFSCar) in Brazil. Cabral was co-supervised by Juarez Lopes Ferreira da Silva, a professor at the University of São Paulo’s São Carlos Chemistry Institute (IQSC-USP). Gustin was supported by São Paulo Research Foundation – FAPESP via a doctoral scholarship and a scholarship for a research internship abroad.

“Gustin and Cabral explain theoretically the unique optical and transport properties resulting from interaction between a molybdenum disulfide monolayer [inorganic substance MoS2] and a substrate of azobenzene [organic substance C12H10N2],” Lopez Richard told.

Illumination makes the azobenzene molecule switch isomerization and transition from a stable trans spatial configuration to a metastable cis form, producing effects on the electron cloud in the molybdenum disulfide monolayer. These effects, which are reversible, had previously been investigated experimentally by Emanuela Margapoti in postdoctoral research conducted at UFSCar and supported by FAPESP.

Gustin and Cabral developed a model to emulate the process theoretically. “They performed ab initio simulations [computational simulations using only established science] and calculations based on density functional theory [a quantum mechanical method used to investigate the dynamics of many-body systems]. They also modeled the transport properties of the molybdenum disulfide monolayer when disturbed by variations in the azobenzene substrate,” Richard explained.

While the published paper does not address technological applications, the deployment of the effect to build a light-activated two-dimensional transistor is on the researchers’ horizon.

“The quasi two-dimensional structure makes molybdenum disulfide as attractive as graphene in terms of space reduction and malleability, but it has virtues that potentially make it even better. It’s a semiconductor with similar electrical conductivity properties to graphene’s and it’s more versatile optically because it emits light in the wavelength range from infrared to the visible region,” Richard said.

The hybrid molybdenum-disulfide-azobenzene structure is considered a highly promising material, but a great deal of research and development will be required if it is to be effectively deployed in useful devices.

Materials that are hybrid constructions (combining organic and inorganic precursors) and quasi-two-dimensional (with malleable and highly compactable molecular structures) are on the rise in several technological applications, such as the fabrication of ever-smaller optoelectronic devices.

An article published in the journal Physical Review B describes a study in this field resulting from the doctoral research of Diana Meneses Gustin and Luís Cabral, both supervised by Victor Lopez Richard, a professor at the Federal University of São Carlos (UFSCar) in Brazil. Cabral was co-supervised by Juarez Lopes Ferreira da Silva, a professor at the University of São Paulo’s São Carlos Chemistry Institute (IQSC-USP). Gustin was supported by São Paulo Research Foundation – FAPESP via a doctoral scholarship and a scholarship for a research internship abroad.

“Gustin and Cabral explain theoretically the unique optical and transport properties resulting from interaction between a molybdenum disulfide monolayer [inorganic substance MoS2] and a substrate of azobenzene [organic substance C12H10N2],” Lopez Richard told.

Illumination makes the azobenzene molecule switch isomerization and transition from a stable trans spatial configuration to a metastable cis form, producing effects on the electron cloud in the molybdenum disulfide monolayer. These effects, which are reversible, had previously been investigated experimentally by Emanuela Margapoti in postdoctoral research conducted at UFSCar and supported by FAPESP.

Gustin and Cabral developed a model to emulate the process theoretically. “They performed ab initio simulations [computational simulations using only established science] and calculations based on density functional theory [a quantum mechanical method used to investigate the dynamics of many-body systems]. They also modeled the transport properties of the molybdenum disulfide monolayer when disturbed by variations in the azobenzene substrate,” Richard explained.

While the published paper does not address technological applications, the deployment of the effect to build a light-activated two-dimensional transistor is on the researchers’ horizon.

“The quasi two-dimensional structure makes molybdenum disulfide as attractive as graphene in terms of space reduction and malleability, but it has virtues that potentially make it even better. It’s a semiconductor with similar electrical conductivity properties to graphene’s and it’s more versatile optically because it emits light in the wavelength range from infrared to the visible region,” Richard said.

The hybrid molybdenum-disulfide-azobenzene structure is considered a highly promising material, but a great deal of research and development will be required if it is to be effectively deployed in useful devices.

Nova (NASDAQ: NVMI) today announced that its co-authored paper with GLOBALFOUNDRIES on ‘Implementation of machine learning for high volume manufacturing metrology challenges’ has been selected as the winner of the Diana Nyyssonen award for ‘best paper at SPIE‘s 2018 Advanced Lithography Symposia.’ The award was granted to Nova and GF on the opening day of the 2019 Conference. The paper is a result of the continuous partnership between the companies and demonstrates the innovation Nova promotes in advanced process control utilizing its unique and differentiated software solutions. The methodology described in the paper was already installed and is utilized by GF in high volume manufacturing.

The joint effort demonstrates that predictive metrology based on machine learning is an advantageous and complementary technique for high volume semiconductor manufacturing. The collaborative work of Nova and GF examined the suitability of machine learning to address high volume manufacturing metrology requirements for applications in both front end of line (FEOL) and back end of line (BEOL) in advanced technology nodes. Feasibility to predict CD values from an inline measurement using machine learning engines was demonstrated, as well as the usage of machine learning data to directly predict electrical parameters.

“We are honored to be selected for this prestigious award in collaboration with our partners at GF,” said Dr. Shay Wolfling, Chief Technology Officer of Nova. “This innovative metrology solution is enabled by our NOVAFitTM technology that enhances traditional modeling capabilities with advanced machine learning algorithms. The joint work with GF has demonstrated once more that through collaboration with our customers our most advanced machine-learning solutions can quickly proliferate and be validated in high volume production in advanced technology nodes.”

The connection from fridge magnets to cutting edge materials science is shorter than what one might expect. The reason why a magnet sticks to your fridge is that electronic spins or magnetic moments in the magnetic material spontaneously align or order in one direction, which enables it to exert an attractive force to the steel door of your fridge and reminds you to buy milk.

Magnets are one type of materials with such built-in order. A ‘topological defect’ in such a material occurs as a discontinuity in this order, i.e. a boundary region where the order does not seamlessly transition from one area to another. These topological structures form naturally or can be highly engineered in advanced functional materials.

An article published this week in the leading journal Nature Materials by FLEET CI Prof Jan Seidel outlines emerging research into different types of ‘defective’ order, i.e. topological structures in materials, and their potential highly interesting applications in nanotechnology and nanoelectronics.

Seidel was invited by the journal editor to review current and discuss future research on domain walls and related topological structures.

Although known for a long time, domain walls as one type of topological structure have only been intensively studied in detail over recent years. It is only with recent developments in high-resolution electron microscopy (HREM) and scanning probe microscopy (SPM) that it has been shown that they can significantly affect macroscopic materials properties, and even more interestingly, that they can exhibit intrinsic properties of their own. Research in this field pioneered in part by Prof Seidel has grown extensively in the last few years and now has entire conferences dedicated to it, such as the annual International Workshop on Topological Structures in Ferroic Materials (TOPO), for which the first meeting was held in 2015 in Sydney.

Nanoelectronics based on topological structures was published in Nature Materials on 20 February 2019. Prof Seidel acknowledges funding support by the Australian Research Council (ARC) through Discovery Grants and the ARC Centre of Excellence in Future Low Energy Electronics Technologies (FLEET).

Prof Jan Seidel is a Professor at the School of Materials Science and Engineering at UNSW Sydney. Contact [email protected]

FLEET is an ARC-funded research centre bringing together over a hundred Australian and international experts to develop a new generation of ultra-low energy electronics, motivated by the need to reduce the energy consumed by computing.

Graphene Flagship researchers solved one of the challenges of making graphene nano-electronics effective: to carve out graphene to nanoscale dimensions without ruining its electrical properties. This allowed them to achieve electrical currents orders of magnitude higher than previously achieved for similar structures. The work shows that the quantum transport properties needed for future electronics can survive scaling down to nanometric dimensions.

Lithographically carved nanographene yields outstanding electrical properties. Credit: Carl Otto Moesgaard

Since its inception, scientists have tried to exploit graphene to produce nano-sized electronics. However, since graphene is only an atom thick, all atoms are exposed to the outside world, and even small amounts of defects and impurities impede its properties. Now, Graphene Flagship researchers at DTU, Denmark solved this problem by protecting graphene with insulating layers of hexagonal boron nitride, another two-dimensional material with insulating properties.

Peter Bøggild, researcher at Graphene Flagship partner DTU and coauthor of the paper, explains that although ‘graphene is a fantastic material that could play a crucial role in making new nano-sized electronics, it is still extremely difficult to control its electrical properties.’ Since 2010, scientists at DTU have tried to tailor the electrical properties of graphene, by making a very fine pattern of holes, so that channels through which an electric power can flow freely are formed. ‘Creating nanostructured graphene turned out to be amazingly difficult, since even small errors wash out all the properties we designed it to have,’ comments Bøggild.

Now, researchers from Graphene Flagship partner DTU made a leap forward. Bjarke Jessen and Lene Gammelgaard encapsulated graphene with another 2D material, hexagonal boron nitride, which is very similar to graphene, but electrically insulating. Then, using nanolithography, they carefully drilled nanoscopic holes in graphene through the protective layer of boron nitride. The holes have a diameter of approximately 20 nanometers, and are separated from each other with just 12 nanometers. This great precision makes possible to send an electrical current through the graphene that is 100-1000 times higher than typical numbers for lithographically carved nanographene.

‘When you make patterns in a material like graphene, you do so in order to change its properties. However, what we have seen throughout the years is that when we shape graphene on this fine scale, it does not behave like graphene anymore – there is too much disorder,’ explains Bøggild. ‘Many scientists have abandoned nanolithography in graphene on this scale, but now we have figured out how it can be done – you could say that the curse is lifted,’ he adds.

‘We have shown that we can control graphene’s band structure and that deterministic design of nanoelectronics is realistic. Looking solely at electronics, this means that we can make insulators, transistors, conductors and perhaps even superconductors, as our nanolithography can preserve the subtle inter-layer physics that was recently shown to lead to superconductivity in double-layer graphene. However, it goes way beyond that. When we control the band structure, we have access to all of graphene’s properties. In other words, we could sit in front of the computer and dream up other applications – and then go to the laboratory and make them happen,’ says Bøggild. ‘There are plenty of practical challenges, but the fact that we can tailor electronic properties of graphene is a big step towards creating new electronics with extremely small dimensions,’ he concludes.

Daniel Neumaier, Graphene Flagship Division Leader for Electronics and Photonics Integration says: ‘Controlling the electronic properties of graphene by nano-pattering offers an additional degree of freedom for the design of electronic and photonic devices, which was so far not accessible. The researchers from Graphene Flagship partner DTU and their co-workers now discovered a unique way for nano-patterning of graphene without seeing the limitations of patterning introduced defects. This was the key enabling step for using the nano-patterning induced electronic properties of graphene in real device and we are expecting significant advances especially for nano-electronics and photonics based on these results.’

Andrea C. Ferrari, Science and Technology Officer of the Graphene Flagship and Chair of its Management Panel added how ‘patterning of graphene to create nano-electronic devices was one of the first approaches attempted to exploit this unique material into devices. However, after an initial flurry of publications, the amount of damage produced was so much that this line of research was almost entirely abandoned. The work presented here shows how the long term nature of the Flagship allows scientists to pursue and solve even apparently intractable problems. This will rejuvenate the interest in graphene nanoelectronics, and could lead to a variety of useful devices, previously hampered by defects.’

Nanowires have the potential to revolutionize the technology around us. Measuring just 5-100 nanometers in diameter (a nanometer is a millionth of a millimeter), these tiny, needle-shaped crystalline structures can alter how electricity or light passes through them.

EPFL researchers have found a way to control and standardize the production of nanowires on silicon surfaces. This discovery could make it possible to grow nanowires on electronic platforms, with potential applications including the integration of nanolasers into electronic chips and improved energy conversion in solar panels. Credit: Jamani Caillet / EPFL

They can emit, concentrate and absorb light and could therefore be used to add optical functionalities to electronic chips. They could, for example, make it possible to generate lasers directly on silicon chips and to integrate single-photon emitters for coding purposes. They could even be applied in solar panels to improve how sunlight is converted into electrical energy.

Up until now, it was impossible to reproduce the process of growing nanowires on silicon semiconductors – there was no way to repeatedly produce homogeneous nanowires in specific positions. But researchers from EPFL’s Laboratory of Semiconductor Materials, run by Anna Fontcuberta i Morral, together with colleagues from MIT and the IOFFE Institute, have come up with a way of growing nanowire networks in a highly controlled and fully reproducible manner. The key was to understand what happens at the onset of nanowire growth, which goes against currently accepted theories. Their work has been published in Nature Communications.

“We think that this discovery will make it possible to realistically integrate a series of nanowires on silicon substrates,” says Fontcuberta i Morral. “Up to now, these nanowires had to be grown individually, and the process couldn’t be reproduced.”

Getting the right ratio

The standard process for producing nanowires is to make tiny holes in silicon monoxide and fill them with a nanodrop of liquid gallium. This substance then solidifies when it comes into contact with arsenic. But with this process, the substance tends to harden at the corners of the nanoholes, which means that the angle at which the nanowires will grow can’t be predicted. The search was on for a way to produce homogeneous nanowires and control their position.

Research aimed at controlling the production process has tended to focus on the diameter of the hole, but this approach has not paid off. Now EPFL researchers have shown that by altering the diameter-to-height ratio of the hole, they can perfectly control how the nanowires grow. At the right ratio, the substance will solidify in a ring around the edge of the hole, which prevents the nanowires from growing at a non-perpendicular angle. And the researchers’ process should work for all types of nanowires.

“It’s kind of like growing a plant. They need water and sunlight, but you have to get the quantities right,” says Fontcuberta i Morral.

This new production technique will be a boon for nanowire research, and further samples should soon be developed.

A team of Cambridge researchers have found a way to control the sea of nuclei in semiconductor quantum dots so they can operate as a quantum memory device.

Quantum dots are crystals made up of thousands of atoms, and each of these atoms interacts magnetically with the trapped electron. If left alone to its own devices, this interaction of the electron with the nuclear spins, limits the usefulness of the electron as a quantum bit – a qubit.

Led by Professor Mete Atatüre, a Fellow at St John’s College, University of Cambridge, the research group, located at the Cavendish Laboratory, exploit the laws of quantum physics and optics to investigate computing, sensing or communication applications.

Atatüre said: “Quantum dots offer an ideal interface, as mediated by light, to a system where the dynamics of individual interacting spins could be controlled and exploited. Because the nuclei randomly ‘steal’ information from the electron they have traditionally been an annoyance, but we have shown we can harness them as a resource.”

The Cambridge team found a way to exploit the interaction between the electron and the thousands of nuclei using lasers to ‘cool’ the nuclei to less than 1 milliKelvin, or a thousandth of a degree above the absolute zero temperature. They then showed they can control and manipulate the thousands of nuclei as if they form a single body in unison, like a second qubit. This proves the nuclei in the quantum dot can exchange information with the electron qubit and can be used to store quantum information as a memory device. The findings have been published in Science today.

Quantum computing aims to harness fundamental concepts of quantum physics, such as entanglement and superposition principle, to outperform current approaches to computing and could revolutionise technology, business and research. Just like classical computers, quantum computers need a processor, memory, and a bus to transport the information backwards and forwards. The processor is a qubit which can be an electron trapped in a quantum dot, the bus is a single photon that these quantum dots generate and are ideal for exchanging information. But the missing link for quantum dots is quantum memory.

Atatüre said: “Instead of talking to individual nuclear spins, we worked on accessing collective spin waves by lasers. This is like a stadium where you don’t need to worry about who raises their hands in the Mexican wave going round, as long as there is one collective wave because they all dance in unison.

“We then went on to show that these spin waves have quantum coherence. This was the missing piece of the jigsaw and we now have everything needed to build a dedicated quantum memory for every qubit.”

In quantum technologies, the photon, the qubit and the memory need to interact with each other in a controlled way. This is mostly realised by interfacing different physical systems to form a single hybrid unit which can be inefficient. The researchers have been able to show that in quantum dots, the memory element is automatically there with every single qubit.

Dr Dorian Gangloff, one of the first authors of the paper and a Fellow at St John’s, said the discovery will renew interest in these types of semiconductor quantum dots. Dr Gangloff explained: “This is a Holy Grail breakthrough for quantum dot research – both for quantum memory and fundamental research; we now have the tools to study dynamics of complex systems in the spirit of quantum simulation.”

The long term opportunities of this work could be seen in the field of quantum computing. Last month, IBM launched the world’s first commercial quantum computer, and the Chief Executive of Microsoft has said quantum computing has the potential to ‘radically reshape the world’.

Gangloff said: “The impact of the qubit could be half a century away but the power of disruptive technology is that it is hard to conceive of the problems we might open up – you can try to think of it as known unknowns but at some point you get into new territory. We don’t yet know the kind of problems it will help to solve which is very exciting.”

Rice University integrated circuit (IC) designers are at Silicon Valley’s premier chip-design conference to unveil technology that is 10 times more reliable than current methods of producing unclonable digital fingerprints for Internet of Things (IoT) devices.

Rice’s Kaiyuan Yang and Dai Li will present their physically unclonable function (PUF) technology today at the 2019 International Solid-State Circuits Conference (ISSCC), a prestigious scientific conference known informally as the “Chip Olympics.” PUF uses a microchip’s physical imperfections to produce unique security keys that can be used to authenticate devices linked to the Internet of Things.

Considering that some experts expect Earth to pass the threshold of 1 trillion internet-connected sensors within five years, there is growing pressure to improve the security of IoT devices.

Yang and Li’s PUF provides a leap in reliability by generating two unique fingerprints for each PUF. This “zero-overhead” method uses the same PUF components to make both keys and does not require extra area and latency because of an innovative design feature that also allows their PUF to be about 15 times more energy efficient than previously published versions.

“Basically each PUF unit can work in two modes,” said Yang, assistant professor of electrical and computer engineering. “In the first mode, it creates one fingerprint, and in the other mode it gives a second fingerprint. Each one is a unique identifier, and dual keys are much better for reliability. On the off chance the device fails in the first mode, it can use the second key. The probability that it will fail in both modes is extremely small.”

As a means of authentication, PUF fingerprints have several of the same advantages as human fingerprints, he said.

“First, they are unique,” Yang said. “You don’t have to worry about two people having the same fingerprint. Second, they are bonded to the individual. You cannot change your fingerprint or copy it to someone else’s finger. And finally, a fingerprint is unclonable. There’s no way to create a new person who has the same fingerprint as someone else.”

PUF-derived encryption keys are also unique, bonded and unclonable. To understand why, it helps to understand that each transistor on a computer chip is incredibly small. More than a billion of them can be crammed onto a chip half the size of a credit card. But for all their precision, microchips are not perfect. The difference between transistors can amount to a few more atoms in one or a few less in another, but those miniscule differences are enough to produce the electronic fingerprints used to make PUF keys.

For a 128-bit key, a PUF device would send request signals to an array of PUF cells comprising several hundred transistors, allocating a one or zero to each bit based on the responses from the PUF cells. Unlike a numeric key that’s stored in a traditional digital format, PUF keys are actively created each time they’re requested, and different keys can be used by activating a different set of transistors.

Adopting PUF would allow chipmakers to inexpensively and securely generate secret keys for encryption as a standard feature on next-generation computer chips for IoT devices like “smart home” thermostats, security cameras and lightbulbs.

Encrypted lightbulbs? If that sounds like overkill, consider that unsecured IoT devices are what three young computer savants assembled by the hundreds of thousands to mount the October 2016 distributed denial-of-service attack that crippled the internet on the East Coast for most of a day.

“The general concept for IoT is to connect physical objects to the internet in order to integrate the physical and cyber worlds,” Yang said. “In most consumer IoT today, the concept isn’t fully realized because many of the devices are powered and almost all use existing IC feature sets that were developed for the mobile market.”

In contrast, the devices coming out of research labs like Yang’s are designed for IoT from the ground up. Measuring just a few millimeters in size, the latest IoT prototypes can pack a processor, flash memory, wireless transmitter, antenna, one or more sensors, batteries and more into an area the size of a grain of rice.

PUF is not a new idea for IoT security, but Yang and Li’s version of PUF is unique in terms of reliability, energy efficiency and the amount of area it would take to implement on a chip. For starters, Yang said the performance gains were measured in tests at military-grade temperatures ranging from 125 degrees Celsius to minus 55 degrees Celsius and when supply voltage dropped by up to 50 percent.

“If even one transistor behaves abnormally under varying environmental conditions, the device will produce the wrong key, and it will look like an inauthentic device,” Yang said. “For that reason, reliability, or stability, is the most important measure for PUF.”

Energy efficiency also is important for IoT, where devices can be expected to run for a decade on a single battery charge. In Yang and Li’s PUF, keys are created using a static voltage rather than by actively powering up the transistor. It’s counterintuitive that the static approach would be more energy efficient because it’s the equivalent of leaving the lights on 24/7 rather than flicking the switch to get a quick glance of the room.

“Normally, people have sleep mode activated, and when they want to create a key, they activate the transistor, switch it once and then put it to sleep again,” Yang said. “In our design, the PUF module is always on, but it takes very little power, even less than a conventional system in sleep mode.”

On-chip area — the amount of space and expense manufacturers would have to allocate to put the PUF device on a production chip — is the third metric where they outperform previously reported work. Their design occupied 2.37 square micrometers to generate one bit on prototypes produced using 65-nanometer complementary metal-oxide-semiconductor (CMOS) technology.

The research was funded by Rice University.

GLOBALFOUNDRIES today announced that the company’s mobile-optimized 8SW RF SOI technology platform has delivered more than a billion dollars of client design win revenue since its launch in September 2017. With yields and performance exceeding client expectations, 8SW is enabling designers to develop solutions that offer extremely fast downloads, higher quality connections and reliable data connectivity for today’s 4G/LTE Advanced operating frequencies and future sub-6 GHz 5G mobile and wireless communication applications.

As the industry’s first 300mm RF SOI foundry solution, 8SW delivers significant performance, integration and area advantages, with best-in-class low-noise amplifier (LNA) and switch performance which all together improve integration solutions in the front-end module (FEM). The optimized RF FEM platform is tailored to accommodate aggressive LTE and sub-6 GHz standards for FEM applications, including 5G IoT, mobile device and wireless communications.

“At Qorvo, we continuously expand upon our industry-leading RF portfolio to support all pre-5G and 5G architectures, as such we require the best available technologies to enable us to deliver top-notch solutions with the broadest range of connectivity in sub-6 GHz and mmWave 5G,” said Todd Gillenwater, Qorvo CTO. “GF’s 8SW technology delivers a mix of performance, integration and area advantages in FEM switches and LNAs, giving us a great platform for our world-class products.”

“As new high-speed standards, including 4G LTE and 5G, continue to grow in complexity, innovation in RF Front End radio design must continue to deliver performance commensurate with growing network, data and application demands,” said Bami Bastani, senior vice president of business units at GF. “GF continuously builds on our extensive RF SOI capabilities that are providing our clients a competitive market advantage with first time design success, optimal performance, and the shortest time to market.”

According to Mobile Experts, the mobile RF front-end market is estimated to reach $22 billion in 2022, with a CAGR of 8.3 percent. With more than 40 billion RF SOI chips shipped thru 2018, GF is uniquely positioned to deliver an expanding RF portfolio for a broad range of high-growth applications such as automotive, 5G connectivity and the Internet of Things (IoT).

“Radio complexity promises to increase for both sub-6 GHz and mmWave, driving tight integration of multiple RF functions,” said Joe Madden, Principal Analyst at Mobile Experts. “The market needs RF solutions with high efficiency and linearity performance, but also using scalable processes on large wafers. GF has established an RF SOI process that will enable longer-term market expansion.”

GF combines legacy RF expertise and the industry’s most differentiated RF technology platform spanning advanced and established technology nodes, to help clients develop 5G connectivity solutions for next-generation products.

GF will present its 5G-ready RF solutions with industry experts at MWC Barcelona on February 25 at the NEXTech Labs Theater, in the Fira Gran Via Convention Center, in Barcelona Spain. For more information, go to globalfoundries.com.