Tag Archives: letter-wafer-tech

The way that electrons paired as composite particles or arranged in lines interact with each other within a semiconductor provides new design opportunities for electronics, according to recent findings in Nature Communications.

What this means for semiconductor components, such as those that send information throughout electronic devices, is not yet clear, but hydrostatic pressure can be used to tune the interaction so that electrons paired as composite particles switch between paired, or “superconductor-like,” and lined-up, or “nematic,” phases. Forcing these phases to interact also suggests that they can influence each other’s properties, like stability – opening up possibilities for manipulation in electronic devices and quantum computing.

Two different kinds of electron arrangements in a semiconductor, paired as composite particles or lined-up, can interact with and tweak each other in the presence of hydrostatic pressure. Credit: Purdue University image/Gábor Csáthy

“You can literally have hundreds of different phases of electrons organizing themselves in different ways in a semiconductor,” said Gábor Csáthy, Purdue professor of physics and astronomy. “We found that two in particular can actually talk to each other in the presence of hydrostatic pressure.”

Csáthy’s group discovered that hydrostatic pressure, which is 10,000 times stronger than ambient pressure, compresses the lattice of atoms in a semiconductor and, therefore, influences the electron arrangement within a two-dimensional electron gas hosted by the semiconductor. The strength of the pressure determines which arrangement is favored and tunes the transition between the paired and lined-up phases, making them more tailorable for an application. Of the two phases, the paired phase may support a certain type of quantum computing.

“We can also tune the interaction by engineering the semiconductor,” Csáthy said. “Say, for example, we grew a semiconductor with a particular width and electron density that we estimated could stabilize the nematic phase. Then we’ve tuned the electron-electron interaction as a result.”

Michael Manfra, Purdue professor of physics and astronomy, electrical and computer engineering and materials engineering, and researchers Loren Pfeiffer and Kenneth West at Princeton University grew the semiconductor samples for this study. Yuli Lyanda-Geller, Purdue associate professor of physics and astronomy, provided theoretical support for the understanding on how these electron-electron interactions took place.

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the research and innovation hub in nanoelectronics and digital technology presented considerable progress in enabling germanium nanowire pFET devices as a practical solution to extend scaling beyond the 5nm node. In a first paper, the research center unveiled an in-depth study of the electrical properties of strained germanium nanowire pFETs. A second paper presents the first demonstration of vertically-stacked gate-all-around highly-strained germanium nanowire pFETs.

“With a number of scaling boosters, the industry will be able to extend FinFET technology to the 7- or even 5nm node,” says An Steegen, EVP at imec’s Semiconductor Technology and Systems division. “Beyond, the gate-all-around (GAA) architecture appears as a practical solution since it reuses most of the FinFET process steps. But one important challenge of using lateral nanowires is the significant decrease of the channel cross-section compared to conventional FinFETs. To improve the drive per footprint, several nanowires have to be stacked, but this comes with a serious penalty of increased parasitic capacitance and resistance. A solution is to replace the silicon nanowires by a high-mobility channel material such as germanium (Ge), providing the necessary current boost per footprint”, adds Steegen, “These new studies show that solution is indeed feasible, reaching the cost, area and performance requirements for nodes beyond 5nm.”

The first study of high-performing strained Ge nanowire pFETs gives insight in the device performance these new devices may offer for high-end analog and high-performance digital solutions. One conclusion is that dedicated optimizations of key process steps make these devices a serious contender for the GAA technology. The second paper reports on Ge GAA FETs with single nanowires, achieving a performance that matches state-of-the-art SiGe and Ge FinFETs. Moreover, for the first time, strained p-type Ge GAA FETs with stacked nanowires were demonstrated on a 14/16nm platform. The GAA nanowire technology appears as a promising high-performance solution for future nodes, provided that the junctions are further optimized.

“These complimentary studies establish germanium GAA nanowire technology as a valid contender for the sustained scaling that will be required to fulfill the requirements for the data-driven IoT-era requiring huge computational power,” concludes Steegen.

These results will be presented on June 20 at the VLSI Technology Symposium, in session T8: Advanced FinFET and GAA. This research is performed in cooperation with imec’s key program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, TOSHIBA Memory, TSMC and Western Digital.

An international team of scientists, including NUST MISIS’s Professor Gotthard Seifert, have made an important step towards the control of excitonic effects in two-dimensional van der Waals heterostructures. In the future, this research will help to create electronics with more controlled properties. The research has been published in Nature Physics.

The creation of two-dimensional semiconductor materials is one of the most important areas of modern materials science. These materials can be the basis for elements needed to create the next generation of electronics.

One two-dimensional material with suitable electronic characteristics is two-dimensional molybdenum disulfide (MoS2), which has a single-layer structure (one atom layer) of molybdenum located between two sulfur layers: this material has a high charge mobility and high on/off in the transistor element.

In 2017, Professor Gotthard Seifert described the mechanism of defect germination in the structure of two-dimensional molybdenum disulfide as a process that will make it possible for scientists to capitalize on two-dimensional MoS2’s full potential use in microelectronics. This work was published in the leading journal, ACS Nano.

The study of other two-dimensional materials’ properties for their application in electronics has become the next step in this field. Monolayers of molybdenum disulfide (and, for example, wolframite diselenides–WSe2) have shown exceptional optical properties due to excitons: tightly bound pairs of electron-hole (quasiparticles acting as a carrier of a positive charge).

At the same time, the creation of the MoS2/WSe2 heterostructure by laying separate monolayers on each other leads to the appearance of a new type of exciton in it, where the electron and the hole are spatially divided into different layers.

Scientists have shown that interlayer excitons give a very specific optical signal display when layered. This allow scientists to study quantum phenomena, making it ideal for experiments in volitronics (a field of quantum electronics, «valley», or the local minimum of an element’s conduction zone) to control electrons in the «valleys» of semiconductors. In the future, these breakthroughs could lead to the most effective way to code information (by placing an electron in one of these valleys).

“Thanks to the use of spectroscopic methods and quantum-chemical calculations from the first principles, we have revealed a partially charged electron-hole in MoS2/WSe2 heterostructures, as well as [the electron-hole’s] location. We have managed to control the radiation energy of this new exciton by changing the relative orientation of the layers”, commented Professor Gotthard Seifert, one of NUST MISIS`s leading scientists.

According to Seifert, this result is an important step towards understanding and controlling exciton effects in Van der Waals heterostructures (where these distance-dependent atomic interactions occur). The research team is continuing to study the effect of layer rotations on the material’s electronic properties. In the future, this will allow for the creation of unique new materials for solar panels or electronics.

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the world-leading research and innovation hub in nanoelectronics and digital technology, demonstrates for the first time the possibility to fabricate spin-orbit torque MRAM (SOT-MRAM) devices on 300mm wafers using CMOS compatible processes. With an unlimited endurance (>5×1010), fast switching speed (210ps), and power consumption as low as 300pJ, the SOT-MRAM devices manufactured in a 300mm line achieve the same or better performance as lab devices. This next-generation MRAM technology targets replacement of L1/L2 SRAM cache memories in high-performance computing applications.

SOT-MRAM has recently emerged as a non-volatile memory technology that promises a high endurance and low-power, sub-ns switching speed. With these properties, it can potentially overcome the limitations of spin-transfer torque MRAM (STT-MRAM) for L1/L2 SRAM cache memory replacement. But so far, SOT-MRAM devices have only been demonstrated in the lab. Imec has now for the first time proven full-scale integration of SOT-MRAM device modules on 300mm wafers using CMOS-compatible processes.

At the core of the SOT-MRAM device is a magnetic tunnel junction in which a thin dielectric layer is sandwiched between a magnetic fixed layer and a magnetic free layer. Similar as for STT-MRAM operation, writing of the memory is performed by switching the magnetization of this free magnetic layer, by means of a current. In STT-MRAM, this current is injected perpendicularly into the magnetic tunnel junction, and the read and write operation is performed through the same path – challenging the reliability of the device. In an SOT-MRAM device, on the contrary, switching of the free magnetic layer is done by injecting an in-plane current in an adjacent SOT layer – typically made of a heavy metal. Because of the current injection geometry, the read and write path are de-coupled, significantly improving the device endurance and read stability.

Imec has compared SOT and STT switching behavior on one and the same device, fabricated on 300mm wafers. While switching speed during STT-MRAM operation was limited to 5ns, reliable switching down to 210ps was demonstrated during SOT-MRAM operation. The SOT-MRAM devices show unlimited endurance (>5×1010) and operation power as low as 300pJ. In these devices, the magnetic tunnel junction consists of a SOT/CoFeB/MgO/CoFeB/SAF perpendicularly magnetized stack, using beta-phase tungsten (W) for the SOT layer.

“STT-MRAM technology has a high potential to replace L3 cache memory in high-performance computing applications”, says Gouri Sankar Kar, Distinguished Member of Technical Staff at imec. “However, due to the challenging reliability and increased nergy at sub-ns switching speeds, they are unsuitable to replace the faster L1/L2 SRAM cache memories. SOT-MRAM technology will help us to expand MRAM operation into the SRAM application domain. By moving this next-generation MRAM technology out of the lab, we have now demonstrated the maturity of the technology.” Future work will focus on further reducing the energy  consumption, by bringing down current density and by demonstrating field-free switching operation.

These results will be presented at the VLSI Circuits Symposium on June 20 in the session C8 Emerging Memory. Imec’s research into advanced memory is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Micron, Qualcomm, Sony Semiconductor Solutions, TSMC and Western Digital.

FormFactor, Inc. (NASDAQ:FORM), a electrical test and measurement supplier to the semiconductor industry, has extended its Contact Intelligence technology. With Contact Intelligence, FormFactor’s advanced probe systems automatically and autonomously adapt in real time to changes in the testing environment, enabling customers to collect large amounts of RF data faster. As the race to bring 5G devices to market heats up, this addresses the need for higher productivity, to reduce time to market.

FormFactor’s Contact Intelligence technology combines smart hardware design and innovative software algorithms to provide accurate probe-to-pad alignment and electronic recalibrations in engineering labs and many production applications. With the introduction of its new RF solution, FormFactor now has specialized Contact Intelligence applications for RF, DC and Silicon Photonics (SiPh) testing.

FormFactor is best known for it’s probe card business, but with its acquisition of Cascade Microtech in 2016, it became more involved in the design and characterization side of chip-making, including RF and silicon photonic devices (probe cards are primarily used at the end of wafer manufacturing, testing the devices before they are packaged).

Mike Slessor, CEO of FormFactor, said with upcoming infrastructure changes — such as 5G, more mobile communications and IoT — RF is an important place to be. “The Cascade Microtech acquisition gave us an engineering systems business. These are pieces of customized capital equipment that help people very early on in their development and R&D — even early pathfinding — to figure out how their next device is going to perform, to characterize it and to improve its yield,” he said. That systems business grew saw a double digit growth rate last year.

Slessor said the new Contact Intelligence technology is designed to help customers in the systems business get a lot of data faster. He said the push to improve yield, along with new materials and new devices, is driving a tremendous amount of data collection. “What Contact Intelligence really is positioned to do is to help people easily and efficiently collect that data. You can think of it as bringing almost production automation to the engineering lab. We’re helping people do it autonomously over wide ranges of temperatures,” he said. He said it enables engineering tools to be upgraded. Customers can “set it up, push a button and walk away for 48 hours, 96 hours even more and come back and have a hundreds of thousands of individual characterization data points.”

New high frequency ICs, such as 5G (with multiple high frequency bands from sub-6 to more than 70 GHz) and automotive communication devices, need the highest quality process design kits (PDK’s) to ensure working devices at first iteration.

Traditional systems and methods require engineers to invest significant time for recalibration when the system invariably drifts, or to reposition probes with intentional changes in test temperatures. At higher frequencies, calibrations and measurements are more sensitive to probe placement errors and there is more calibration drift, so recalibration is required more often.Over time and temperature, Contact Intelligence automatically makes these adjustments with no operator intervention, resulting in more devices tested in less time, for more accurate PDK’s and faster time to market.

Slessor says the push to 5G brings many design and test challenges due to the significant increase in carrier frequencies – 10 times higher than 4G. “Although there are different bands and the carriers and the countries are still ironing out where they’re going to operate, there are bands as high as 72 gigahertz,” Slessor said. “Electrical signal propagation gets much, much more challenging as you go up in frequency. All kinds of new engineering and physics challenges emerge because you’ve got things that are radiating a good deal of power and there’s a whole bunch of cross talk on the chip. There are all kinds of interesting phenomena that appear that make the designers and the test engineer’s job much more difficult just because of these higher frequencies.”

In an RF front end, instead of modems or radios communicating, a wide variety of a BAW and SAW  filters are used to do the frequency band management and make sure that only the individual bands that are supposed to be used or being effectively used.

In addition to RF, Contact Intelligence is also designed for use in autonomous DC testing and for silicon phototonics.

In DC applications, Contact Intelligence automatically senses preset temperatures, and responds by waiting the correct amount of time until the system is stabilized. This allows lengthy test routines to be conducted over multiple temperatures without an operator present. Contact Intelligence also provides dynamic probe-to-pad alignment, even on pads as small as 25 µm, employing a combination of smart software, probe tip recognition algorithms and advanced programmable positioners.

FormFactor’s integrated SiPh solution allows sub-micron manipulation of optical fibers positioned above the wafer, automatically optimizing fiber coupling position.  Contact Intelligence uses machine vision technology to automate Theta X, Y and Z axis calibrations and alignments enabling measurements out of the box, reducing what used to take days or weeks to a matter of minutes.When combined with autonomous DC and RF, measurement options expand from Optical-Optical to include Photo-Diodes, Optical Modulators and more.

For more information, visit http://www.formfactor.com/contactintelligence.

Synopsys, Inc. (Nasdaq: SNPS) today announced that Synopsys’ IC Validator has been certified by Samsung Foundry for signoff of all designs using its 7-nanometer (nm) Low Power Plus (LPP) process with Extreme Ultraviolet (EUV) lithography technology. The signoff-certified runsets, including design rule checking (DRC), layout-versus-schematic (LVS) and metal fill technology files, are available immediately from Samsung Foundry. Samsung Foundry 7LPP customers can now use IC Validator’s modern distributed processing in conjunction with runsets from Samsung Foundry to achieve faster physical verification turnaround time with the highest level of accuracy.

“We are building a customer-friendly design enablement ecosystem for 7LPP, our first EUV-based process technology,” said Ryan Sanghyun Lee, vice president of Foundry Marketing Team at Samsung Electronics. “Synopsys’ IC Validator is a great solution for our mutual customers to make the next generation of SoCs, which will lead the fourth industrial revolution with maximized power and performance benefit based on 7LPP process technology.”

IC Validator, a key component of the Synopsys Design Platform, is a comprehensive and highly scalable physical verification tool suite including DRC, LVS, programmable electrical rule checks (PERC), fill, and DFM enhancement capabilities. IC Validator is architected for high performance and scalability that maximizes utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies. It uses both multi-threading and distributed processing over multiple machines to provide scalability benefits that extend to more than a thousand CPUs.

“Our partnership with Samsung Foundry has been focused on delivering high-quality and high-performance physical signoff solutions for today’s leading-edge designs,” said Christen Decoin, senior director of business development, Design Group at Synopsys. “This certification brings the proven benefits of IC Validator physical verification to Samsung Foundry 7LPP customers.”

WIN Semiconductors Corp (TPEx:3105), the world’s largest pure-play compound semiconductor foundry, has expanded its portfolio of highly integrated GaAs technologies with the release of a new pHEMT technology. The PIH0-03 platform incorporates monolithic PIN and vertical Schottky diodes with WIN’s high performance 0.1um pseudomorphic HEMT process, PP10. This integrated technology, PIH0-03, adds a highly linear vertical Schottky diode with cut-off frequency over 600GHz, as well as multi-function PIN diodes while preserving the state-of-the-art mmWave performance of the PP10 technology. The availability of monolithic PIN and Schottky diodes with a high performance mmWave transistor enables on-chip integration of a wide range of functions, including mixers, temperature/power detecting, limiters, and high frequency switching, and supports power, low noise and optical applications through100 GHz.

This integrated technology provides users with multiple pathways to add on-chip functionality and reduce the overall die count of complex multi-chip modules used in a variety of end-markets. In addition to high frequency switching, the monolithic PIN diodes can be used for low parasitic capacitance ESD protection circuits, and as an on-chip power limiter to protect sensitive LNAs in phased array radars. The vertical Schottky diodes enable numerous detecting and mixing functions and can be combined with the PIN diodes in unique limiter applications.

“Today’s complex systems and highly competitive markets require increased mmWave performance and more functionality per chip. The PIH0-03 platform is the latest example of how WIN Semiconductors is addressing these critical market needs by offering high performance GaAs technologies with new levels of multifunction integration. To meet the ever-increasing demands of next generation mobile user equipment, wireless infrastructure, fiber optics and military applications, WIN Semiconductors continues to commercialize advanced, highly integrated GaAs solutions and provide our customers a clear technology advantage,” said David Danzilio, Senior Vice President of WIN Semiconductors Corp.

In the field of photovoltaic technologies, silicon-based solar cells make up 90% of the market. In terms of cost, stability and efficiency (20-22% for a typical solar cell on the market), they are well ahead of the competition.

However, after decades of research and investment, silicon-based solar cells are now close to their maximum theoretical efficiency. As a result, new concepts are required to achieve a long-term reduction in solar electricity prices and allow photovoltaic technology to become a more widely adopted way of generating power.

One solution is to place two different types of solar cells on top of each other to maximize the conversion of light rays into electrical power. These “double-junction” cells are being widely researched in the scientific community, but are expensive to make. Now research teams in Neuchâtel – from EPFL’s Photovoltaics Laboratory and the CSEM PV-center – have developed an economically competitive solution. They have integrated a perovskite cell directly on top of a standard silicon-based cell, obtaining a record efficiency of 25.2%. Their production method is promising, because it would add only a few extra steps to the current silicon-cell production process, and the cost would be reasonable. Their research has been published in Nature Materials.

This scanning electron microscopy image shows Silicon’s pyramids covered with perovskite. Credit: EPFL

Perovskite-on-silicon: a nanometric sandwich

Perovskite’s unique properties have prompted a great deal of research into its use in solar cells over the last few years. In the space of nine years, the efficiency of these cells has risen by a factor of six. Perovskite allows high conversion efficiency to be achieved at a potentially limited production cost.

In tandem cells, perovskite complements silicon: it converts blue and green light more efficiently, while silicon is better at converting red and infra-red light. “By combining the two materials, we can maximize the use of the solar spectrum and increase the amount of power generated. The calculations and work we have done show that a 30% efficiency should soon be possible,” say the study’s main authors Florent Sahli and Jérémie Werner.

However, creating an effective tandem structure by superposing the two materials is no easy task. “Silicon’s surface consists of a series of pyramids measuring around 5 microns, which trap light and prevent it from being reflected. However, the surface texture makes it hard to deposit a homogeneous film of perovskite,” explains Quentin Jeangros, who co-authored the paper.

When the perovskite is deposited in liquid form, as it usually is, it accumulates in the valleys between the pyramids while leaving the peaks uncovered, leading to short circuits.

A key layer ensuring an optimal microstructure

Scientists at EPFL and CSEM have gotten around that problem by using evaporation methods to form an inorganic base layer that fully covers the pyramids. That layer is porous, enabling it to retain the liquid organic solution that is then added using a thin-film deposition technique called spin-coating. The researchers subsequently heat the substrate to a relatively low temperature of 150°C to crystallize a homogeneous film of perovskite on top of the silicon pyramids.

“Until now, the standard approach for making a perovskite/silicon tandem cell was to level off the pyramids of the silicon cell, which decreased its optical properties and therefore its performance, before depositing the perovskite cell on top of it. It also added steps to the manufacturing process,” says Florent Sahli.

Updating existing technologies

The new type of tandem cell is highly efficient and directly compatible with monocrystalline silicon-based technologies, which benefit from long-standing industrial expertise and are already being produced profitably. “We are proposing to use equipment that is already in use, just adding a few specific stages. Manufacturers won’t be adopting a whole new solar technology, but simply updating the production lines they are already using for silicon-based cells,” explains Christophe Ballif, head of EPFL’s Photovoltaics Laboratory and CSEM’s PV-Center.

At the moment, research is continuing in order to increase efficiency further and give the perovskite film more long-term stability. Although the team has made a breakthrough, there is still work to be done before their technology can be adopted commercially.

WIN Semiconductors Corp (TPEx:3105), the world’’s largest pure-play compound semiconductor foundry, has expanded its gallium nitride (GaN) process capabilities to include a 0.45?m-gate technology that supports current and future 5G applications. The NP45-11 GaN-on-SiC process allows customers to design hybrid Doherty power amplifiers used in 5G applications including massive MIMO (multiple-input and multiple-output) wireless antenna systems. Similar to macro-cell applications, MIMO base stations often combine Doherty power amplifiers with linearization techniques to meet demanding linearity and efficiency specifications of today’s wireless infrastructure.

GaN devices outperform the incumbent LDMOS technology, offering superior efficiency, instantaneous bandwidth and linearity, particularly in the higher frequency bands utilized in 5G radio access networks.

Ideal for use in sub-6 GHz 5G applications including macro-cell transmitters and MIMO access points, the NP45-11 technology supports power applications from 100 MHz through 6GHz. This discrete transistor process is environmentally rugged, incorporating advanced moisture protection and meets the JEDEC JESD22-A110 biased HAST qualification at 55 volts. Combined with WIN Semiconductors’ environmentally rugged high voltage passive technology, IP3M-01, the NP45-11 technology enables hybrid power amplifiers in a low cost plastic package.

The NP45-11 technology is fabricated on 100mm silicon carbide substrates and operates at a drain bias of 50 volts. In the 2.7GHz band, this technology provides saturated output power of 7 watts/mm with 18 dB linear gain and more than 65% power added efficiency without harmonic tuning.

“5G radio access networks create several challenges to power amplifier designs used in MIMO systems. High output power and linear efficiency are primary design objectives to meet performance specifications and lower total cost of ownership. The tradeoff between output power and linearized efficiency is significant because of the high peak-to-average power ratio employed in today’s wireless modulation schemes. This tradeoff becomes more difficult in 5G applications due to greater instantaneous bandwidth requirements and higher operating frequency,” said David Danzilio, Senior Vice President of WIN Semiconductors Corp.

Ever shrinking transistors are the key to faster and more efficient computer processing. Since the 1970s, advancements in electronics have largely been driven by the steady pace with which these tiny components have grown simultaneously smaller and more powerful–right down to their current dimensions on the nanometer scale. But recent years have seen this progress plateau, as researchers grapple with whether transistors may have finally hit their size limit. High among the list of hurdles standing in the way of further miniaturization: problems caused by “leakage current.”

Leakage current results when the gap between two metal electrodes narrows to the point that electrons are no longer contained by their barriers, a phenomenon known as quantum mechanical tunnelling. As the gap continues to decrease, this tunnelling conduction increases at an exponentially higher rate, rendering further miniaturization extremely challenging. Scientific consensus has long held that vacuum barriers represent the most effective means to curtail tunnelling, making them the best overall option for insulating transistors. However, even vacuum barriers can allow for some leakage due to quantum tunnelling.

In a highly interdisciplinary collaboration, researchers across Columbia Engineering, Columbia University Department of Chemistry, Shanghai Normal University, and the University of Copenhagen have upended conventional wisdom, synthesizing the first molecule capable of insulating at the nanometer scale more effectively than a vacuum barrier. Their findings are published online today in Nature.

“We’ve reached the point where it’s critical for researchers to develop creative solutions for redesigning insulators. Our molecular strategy represents a new design principle for classic devices, with the potential to support continued miniaturization in the near term,” said Columbia Engineering physicist and co-author Latha Venkataraman, who heads the lab where researcher Haixing Li conducted the project’s experimental work. Molecular synthesis was carried out in the Colin Nuckolls Lab at Columbia’s Department of Chemistry, in partnership with Shengxiong Xiao at Shanghai Normal University.

The team’s insight was to exploit the wave nature of electrons. By designing an extremely rigid silicon-based molecule under 1 nm in length that exhibited comprehensive destructive interference signatures, they devised a novel technique for blocking tunnelling conduction at the nanoscale.

“This quantum interference-based approach sets a new standard for short insulating molecules,” said lead author Marc Garner, a chemist in the University of Copenhagen’s Solomon Lab, which handled the theoretical work. “Theoretically, interference can lead to complete cancellation of tunneling probability, and we’ve shown that the insulating component in our molecule is less conducting than a vacuum gap of same dimensions. At the same time, our work also improves on recent research into carbon-based systems, which were thought to be the best molecular insulators until now.”

Destructive quantum interference occurs when the peaks and valleys of two waves are placed exactly out of phase, annulling oscillation. Electronic waves can be thought of as analogous to sound waves–flowing through barriers just as sound waves “leak” through walls. The unique properties exhibited by the team’s synthetic molecule mitigated tunneling without requiring, in this analogy, a thicker wall.

Their silicon-based strategy also presents a potentially more factory-ready solution. While recent research into carbon nanotubes holds promise for industrial applications over the next decade or so, this insulator–compatible with current industry standards–could be more readily implemented.

“Congratulations to the team on this breakthrough,” said Mark Ratner, a pioneer in the field of molecular electronics and professor emeritus at Northwestern University who was not involved in the study. “Using interference to create an insulator has been ignored up to this date. This paper demonstrates the ability of interference, in a silicon-based sigma system, which is quite impressive.”

This breakthrough grew out of the team’s larger project on silicon-based molecule electronics, begun in 2010. The group arrived at their latest discovery by bucking the trend. Most research in this field aims to create highly conducting molecules, as low conductance is rarely considered a desirable property in electronics. Yet insulating components may actually prove to be of greater value to future optimization of transistors, due to the inherent energy inefficiencies caused by leakage currents in smaller devices.

As a result, their work has yielded new understanding of the fundamental underlying mechanisms of conduction and insulation in molecular scale devices. The researchers will build on this insight by next clarifying the details of structure-function relationships in silicon-based molecular components.

“This work has been extremely gratifying for us, because in the course of it we have repeatedly discovered new phenomena,” said Venkataraman. “We have previously shown that silicon molecular wires can function as switches, and now we’ve demonstrated that by altering their structure, we can create insulators. There is a lot to be learned in this area that will help shape the future of nanoscale electronics.”