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Toyoda Gosei Co., Ltd. has achieved state-of-the-art high current operation1 in a vertical GaN power semiconductor developed using gallium nitride (GaN), a main material in blue LEDs.

Power semiconductors are widely used in power converters2 such as power sources and adaptors for electronic devices. However, simultaneous achievement of both high breakdown voltage3 and low loss4 (low conduction loss and switching loss) at high levels has been difficult with conventional silicon due to its material properties.

In its power semiconductors, Toyoda Gosei uses GaN, which has material properties of high breakdown voltage and low loss, and employs a vertical device structure in which electrical current flows vertically from or to a substrate. These changes have enabled a GaN power transistor chip with operating current of over 50A, highest ever reported for vertical GaN transistors2, and high-frequency (several megahertz) operation. Some prospective applications are shown below.

Promising areas of use (examples)

Power converters
More compact & lighter weight, higher efficiency

 Power control units (PCUs) for automobiles, etc.
DC-DC converters

High frequency power sources
Higher output

 Wireless power supply

Toyoda Gosei will continue development of these power semiconductors for improved reliability, aiming to achieve practical applications in cooperation with semiconductor and electronics manufacturers.

The newly developed vertical GaN power transistors (MOSFET)5 and Schottky barrier diodes6 will be presented on panel displays at the Techno-Frontier 2018 Advanced Electronic & Mechatronic Devices and Components Exhibition, held at Makuhari Messe, Chiba, Japan from April 18 to April 20. The world’s first full vertical-GaN DC-DC converter equipped with these devices will also be demonstrated at the company’s booth (6F-11, Hall 6).

1 According to internal Toyoda Gosei survey (as of April 2018).
2 Power conversion refers to conversion between direct and alternating current, direct current transformation, alternating current frequency conversion, etc.
3 The property of withstanding the high breakdown voltage during power conversion and not allowing current flow during off operation (non-conductance).
4 Heat loss generated by electrical resistance during electric conduction or when switching on/off.
5 Semiconductor used in power on/off.
MOSFET: Metal-oxide-semiconductor field-effect-transistor.
6 Semiconductor used in converting (rectification) from alternating current to direct current. Toyoda Gosei uses a trench MOS structure, in which trenches are formed at fixed intervals in the chip surface of the diode, achieving low leakage current operation at high temperatures.

When power generators like windmills and solar panels transfer electricity to homes, businesses and the power grid, they lose almost 10 percent of the generated power. To address this problem, scientists are researching new diamond semiconductor circuits to make power conversion systems more efficient.

The view of the H-diamond MOSFET NOR logic circuit from above (left), and the operation of the NOR logic circuits, showing that the circuit only produces voltage when both inputs are at zero. Credit: Liu et al.

The view of the H-diamond MOSFET NOR logic circuit from above (left), and the operation of the NOR logic circuits, showing that the circuit only produces voltage when both inputs are at zero. Credit: Liu et al.

A team of researchers from Japan successfully fabricated a key circuit in power conversion systems using hydrogenated diamond (H-diamond.) Furthermore, they demonstrated that it functions at temperatures as high as 300 degrees Celsius. These circuits can be used in diamond-based electronic devices that are smaller, lighter and more efficient than silicon-based devices. The researchers report their findings this week in Applied Physics Letters, from AIP Publishing.

Silicon’s material properties make it a poor choice for circuits in high-power, high-temperature and high-frequency electronic devices. “For the high-power generators, diamond is more suitable for fabricating power conversion systems with a small size and low power loss,” said Jiangwei Liu, a researcher at Japan’s National Institute for Materials Science and a co-author on the paper.

In the current study, researchers tested an H-diamond NOR logic circuit’s stability at high temperatures. This type of circuit, used in computers, gives an output only when both inputs are zero. The circuit consisted of two metal-oxide-semiconductor field-effect transistors (MOSFETs), which are used in many electronic devices, and in digital integrated circuits, like microprocessors. In 2013, Liu and his colleagues were the first to report fabricating an E-mode H-diamond MOSFET.

When the researchers heated the circuit to 300 degrees Celsius, it functioned correctly, but failed at 400 degrees. They suspect that the higher temperature caused the MOSFETs to breakdown. Higher temperatures may be achievable however, as another group reported successful operation of a similar H-diamond MOSFET at 400 degrees Celsius. For comparison, the maximum operation temperature for silicon-based electronic devices is about 150 degrees.

In the future, the researchers plan to improve the circuit’s stability at high temperatures by altering the oxide insulators and modifying the fabrication process. They hope to construct H-diamond MOSFET logic circuits that can operate above 500 degrees Celsius and at 2.0 kilovolts.

“Diamond is one of the candidate semiconductor materials for next-generation electronics, specifically for improving energy savings,” said Yasuo Koide, a director at the National Institute for Materials Science and co-author on the paper. “Of course, in order to achieve industrialization, it is essential to develop inch-sized single-crystal diamond wafers and other diamond-based integrated circuits.”

The 2018 Symposia on VLSI Technology & Circuits will deliver a unique perspective into the technological ecosystem of converging industry trends – machine learning, IoT, artificial intelligence, wearable/implantable biomedical applications, big data, and cloud computing – the emerging technologies needed for ‘smart living.’ In a weeklong conference packed with technical presentations, a demonstration session, panel discussions, focus sessions, short courses, and a new “Friday Forum” on machine learning, the microelectronics industry’s premiere international conference covers technology, circuits, and systems with a range and scope unlike any other conference.

Built around the theme of “Technology, Circuits & Systems for Smart Living,” the Symposia programintegrates advanced technology developments, innovative circuit design, and the applications that they enable as part of our global society’s adoption of smart, connected devices and systems that change the way humans interact with each other.

Plenary Sessions (June 19):
The Symposia will open with two technology plenary sessions, including “Memory Technology: The Core to Enable Future Computing Systems” by Scott DeBoer, executive VP for technology development, Micron; and “Revolutionizing Cancer Genomic Medicine by Artificial Intelligence & Supercomputing with Big Data” by Satoru Miyano, director of the Human Genome Center, Institute of Medical Science at University of Tokyo.

The following Circuits plenary sessions include “Hardware-Enabled Artificial Intelligence” by Dr. Bill Dally, chief scientist & senior VP, Nvidia; and “Semiconductor Technologies Accelerate Our Future Vision: ‘ANSHIN Platform'” by Tsuneo Komatsuzaki, advisor, SECOM.

Focus Sessions (June 19, 20 & 21):
As part of the Symposia’s ongoing program integration, a series of joint focus sessions will be held to present contributed papers from the Technology and Circuits Symposia on June 20 and 21. Topics will include: “Heterogeneous System Integration,” “Power Devices & Circuits,” “New Devices & Systems for AI,” and “Design & Technology Co-Optimization (DTCO) in Advanced CMOS Technology.”

On June 19, the Technology focus sessions will include: “Back-End Compatible Devices & Advanced Thermal Management“ and “Sensors and Devices for IoT, Medicine, & Smart Living.” The Circuits focus sessions, held on June 21, include “Machine Learning Circuits & SoCs,” and “Advanced Wireline Techniques.”

Evening Panel Sessions (June 18 & 19):
A joint panel discussion, bringing together leading experts from Technology & Circuits programs will be held June 18 to answer the question, “Is the CPU Dying or Dead? Are Accelerators the Future of Computation?”

As Moore’s Law slows down and processor architecture innovations move away from single thread performance, the future of computing seems to be moving away from the general purpose CPU. Is the era of the CPU over? Will future CPUs simply coordinate activity among accelerators and other specialized processing units? The panel will examine future computing workloads as well as the innovative technology and circuit solutions that enable them, from moving computation closer to memory, and developing bio-inspired systems.

The Technology evening panel session panel discussion, held on June 19 will examine “Storage Class Memories: Who Cares? DRAM is Scaling Fine, NAND Stacking is Great.” Memory – DRAM and NAND scaling – though difficult, has persisted due to rapid innovations and continued engineering. Although there are new economic and fundamental challenges posed to continued memory scaling, a new class of memories – Storage Class memories, appears to bridge the latency gap that exists in the memory hierarchy and promises to improve system performance. Now the real question becomes – who really cares now? System architects, DRAM/NAND manufacturers? End users? The panel will discuss the challenges and opportunities of storage class memories in the environment where DRAM and NAND scaling continue.

The question to be addressed by the Circuits evening panel session, also held on June 19, is “What’s The Next Big Thing After Smartphones?” Although smartphones have driven the industry for more than a decade, the pace of innovation is slowing, and market saturation is occurring. What will be the next big thing? The Internet of Things? Automotive electronics? Virtual reality? Something else? A set of panelists with diverse expertise will discuss the possibilities.

Thursday Luncheon (June 21):
Continuing the Symposia’s tradition of thought-provoking presentations centered around the conference theme is the Thursday luncheon talk, entitled “The Hardware of The Mind, from Turing to Today,” by Grady Booch, chief scientist for software engineering at IBM Research. As scientists continue to the computing power of the human mind, they strive to bridge the gap between the physicality of silicon and the exquisite wonder of the brain. This presentation examines the journey of the hardware of the mind – from the Iliad, to da Vinci, to Edison, to Turing, to today – including an examination of how the growing understanding of the brain transforms the engineering of silicon, and how the laws of physics as well as the laws of humanity constrain that journey.

Full Day Short Courses (June 18):
The Technology Short Course – “Device & Integration Technologies for Sub-5nm CMOS & the Next Wave of Computing” will cover a range of topics, including CMOS technology beyond the 5nm node, MOL/BEOL interconnects, atomic-level analysis for FinFET & Nanowire design, 3D integration for image sensors, neuromorphic AI hardware, memory technologies for AI/machine learning, and sensors & analog devices for next generation computing.

The first Circuits Short Course – “Designing for the Next Wave of Cloud Computing” will address advanced computer architectures, GPU applications and FPGA acceleration, the evolution of memory and in-memory computation, and advanced packaging, power delivery and cooling for cloud computing, as well as the impact of quantum computing.

The second Circuits Short Course – “Bio-Sensors, Circuits & Systems for Wearable & Implantable Medical Devices” will cover circuits and systems for mobile healthcare, analog front-ends for bio-sensors, digital phenotyping using wearable sensors, bi-directional neural interfacing, body-area networking and body-coupled communications, ultrasound-on-a-chip, as well as a CMOS-based implantable retinal prosthesis.

Demonstration Session (June 18):
Following a successful launch last year in Kyoto, the popular demonstration session will again be part of the Symposia program, providing participants an opportunity for in-depth interaction with authors of selected papers from both Technology and Circuits sessions. These demonstrations will illustrate technological concepts and analyses through table-top presentations that show device characterization, chip operational results, and potential applications for circuit-level innovations.

Friday Forum (June 22):
New to the Symposia program this year will be the Friday Forum – a full-day series of presentations focusing on how technology and circuit designers engage in and drive the future of AI/machine learning systems, a subject area that continues to evolve as an impactful driver of the integrated systems that are part of the Symposia’s “Smart Living” theme. “Machine Learning Today & Tomorrow: A Technology, Circuits & Systems View” will provide the foundations and performance metrics for machine learning systems, an examination of advanced and emerging circuit architectures for next-generation systems, as well as highlighting tools and datasets for benchmarking and evaluating service-oriented architecture (SoA) machine learning systems.

The annual Symposium on VLSI Technology & Circuits will be held at the Hilton Hawaiian Village in Honolulu, Hawaii from June 18-22, 2018, with Short Courses held on June 18 and a special Friday Forum dedicated to machine learning/AI topics on June 22. The two conferences have been held together since 1987, providing an opportunity for the world’s top device technologists, circuit and system designers to exchange leading edge research on microelectronics technology, with alternating venues between Hawaii and Japan. A single registration enables participants to attend both Symposia.

Today, research and innovation hub in nanoelectronics and digital technologies imec, and fabless technology innovator Qromis, have announced the development of high performance enhancement mode p-GaN power devices on 200mm engineered Coefficient of Thermal Expansion (CTE)-matched substrates, processed in imec’s silicon pilot line. The substrates are offered by Qromis as commercial 200mm QST® substrates as part of their patented product portfolio. The results will be presented at next week’s CS international Conference (April 10-11, Brussels, Belgium).

Today, GaN-on-Si technology is the industry standard platform for commercial GaN power switching devices for wafer diameters up to 150mm/6 inch.  Imec has pioneered the development of GaN-on-Si power technology for 200mm/8 inch wafers and qualified enhancement mode HEMT and Schottky diode power devices for 100V, 200V and 650V operating voltage ranges, paving the way to high volume manufacturing applications. However, for applications beyond 650V such as electric cars and renewable energy, it has become difficult to further increase the buffer thickness on 200mm wafers to the levels required for higher breakdown and low leakage levels, because of the mismatch in coefficient of thermal expansion (CTE) between the GaN/AlGaN epitaxial layers and the silicon substrate.  One can envisage to use thicker Si substrates to keep wafer warp and bow under control for 900V and 1200V applications, but practice has learned that for these higher voltage ranges, the mechanical strength is a concern in high volume manufacturing, and the ever thicker wafers can cause compatibility issues in wafer handling in some processing tools.

Carefully engineered and CMOS fab-friendly QST® substrates with a CTE-matched core having a thermal expansion that very closely matches the thermal expansion of the GaN/AlGaN epitaxial layers, are paving the way to 900V-1200V buffers and beyond, on a standard semi-spec thickness 200mm substrate. Moreover, QST® substrates open perspectives for very thick GaN buffers, including realization of free-standing and very low dislocation density GaN substrates by >100 micron thick fast-growth epitaxial layers. These unique features will enable long awaited commercial vertical GaN power switches and rectifiers suitable for high voltage and high current applications presently dominated by Si IGBTs and SiC power FETs and diodes.

“QST® is revolutionizing GaN technologies and businesses for 200mm and 300mm platforms”, stated Cem Basceri, President and CEO of Qromis.  “I am very pleased to see the successful demonstration of high performance GaN power devices by stacking leading edge technologies from Qromis, imec and AIXTRON,” Basceri said.

In this specific collaboration, imec and Qromis developed enhancement mode p-GaN power device specific GaN epitaxial layers on 200mm QST®substrates, with buffers grown in AIXTRON’s G5+ C 200mm high volume manufacturing MOCVD system.

Imec then ported its p-GaN enhancement mode power device technology to the 200mm GaN-on- QST® substrates in their silicon pilotline and demonstrated high performance power devices with threshold voltage of 2.8 Volt.  “The engineered QST® substrates from Qromis facilitated a seamless porting of our process of reference from thick GaN-on-Si substrates to standard thickness GaN-on- QST® substrates using the AIX G5+ C system, in a joint effort of imec, Qromis and AIXTRON,” stated Stefaan Decoutere, program director for GaN power technology at imec. The careful selection of the material for the core of the substrates, and the development of the light-blocking wrapping layers resulted in fab-compatible standard thickness substrates and first-time-right processing of the power devices.

quormis

A further step has been taken along the road to manufacturing solar cells from lead-free perovskites. High quality films based on double perovskites, which show promising photovoltaic properties, have been developed in collaboration between Linköping University, Sweden, and Nanyang Technological University in Singapore.

The lead-free double perovskite solar cells (yellow, in the front) compared with the lead-based device (dark, in the background). The next step is tune the color of the double perovskites into dark, so that they can absorb more light for efficient solar cells. Credit: Thor Balkhed

The lead-free double perovskite solar cells (yellow, in the front) compared with the lead-based device (dark, in the background). The next step is tune the color of the double perovskites into dark, so that they can absorb more light for efficient solar cells. Credit: Thor Balkhed

Research groups around the world have recognised the potential of perovskites as one of the most promising materials for the development of cheap, environmentally friendly and efficient solar cells. In just a few years, the power conversion efficiency has increased from a few percent to over 22%. The perovskites currently available for use in solar cells, however, contain lead, and Feng Gao, senior lecturer at LiU, was appointed in the autumn of 2017 as Wallenberg Academy Fellow to develop lead-free double perovskites, in which a monovalent metal and a trivalent metal replace the divalent lead.

In the laboratory at the Division of Biomolecular and Organic Electronics, LiU, postdoc researchers Weihua Ning and Feng Wang have successfully manufactured single-layer thin films of densely packed crystals of double perovskites. The films are of extremely high quality and can be used as the active layer in solar cells, in which sunlight is absorbed and charge carriers created.

“Our colleagues at Nanyang Technological University in Singapore have shown that the charge carriers demonstrate long diffusion lengths in the material, which is necessary if the material is to be appropriate for application in solar cells,” says Feng Gao.

The power conversion efficiency of the solar cells is still low – only around 1% of the energy in sunlight is converted to electricity – but neither Feng Gao or Weihua Ning are worried.

“No, we have taken the first major step and developed a method to manufacture the active layer. We have several good ideas of how to proceed to increase the efficiency in the near future,” says Feng Gao.

Weihua Ning nods in agreement.

Researchers have calculated that over 4,000 different combinations of materials can form double perovskites. They will also use theoretical calculations to identify the combinations that are most suitable for use in solar cells.

This breakthrough for research in double perovskites is also a result of the joint PhD programme in Materials- and nanoscience/technology at Linköping University and Nanyang Technological University.

“This publication is a spin-off of the discussions in relation to the joint PhD programme between NTU-LiU. Two PhD students, one on each side, have been recruited to work on this project. This is an excellent start for the program.” says Professor Tze Chien Sum from NTU.

“We complement each other very well, the group led by Professor Sum in NTU are experts in photophysics and we are experts in materials science and device physics,” says Feng Gao.

Tre results is published in the prestigious scientific journal Advanced Materials.

AKHAN Semiconductor, a technology company specializing in the fabrication and application of lab-grown, electronics-grade diamonds, announced today that it has obtained official notifications from both the United States Patent and Trademark Office (USPTO) and Taiwan Intellectual Property Office (TIPO) for the Miraj Diamond trademark registration and patent allowance.

The official registration of the Miraj Diamond mark by the USPTO (Registration No. 5,438,740) follows nearly six years of completed filings fulfilled by the Illinois-based technology company following its launch in December 2012. The TIPO issued patent I615943 is the second AKHAN patent to be granted by the country– well-known to be strategic in the global semiconductor marketplace. The patent is a foreign counterpart of other issued and pending patents owned by AKHAN Semiconductor, Inc. that are used in the company’s Miraj Diamond® products. The claims protect uses far beyond the existing applications, including microprocessor applications. Covering the base materials common to nearly all semiconductor components, the intellectual property can be realized in everything from diodes, transistors, and power inverters, to fully functioning diamond chips such as integrated circuitry.

“The official declarations from both the USPTO and TIPO significantly add to the critical protections of the Miraj Diamond intellectual property portfolio and brand,” said Adam Khan, Founder & Chief Executive Officer of AKHAN Semiconductor. “Less than six years after our founding, the Miraj Diamond trademark is not only gaining global attention from the consumer electronics and semiconductor market places, but is also synonymous for next-generation performance, breakthrough capability, and flagship technology with diamond.”

“The notices of these issuances are very timely as we complete the construction of our cleanroom pilot production facility in northern Illinois,” added Carl Shurboff, AKHAN President and Chief Operating Officer. “With the targeted 2019 launch of our Miraj Diamond® Glass products for Smartphone devices and the concurrent development of our Miraj Diamond® electronics products for aerospace and defense, the brand equity we deliver in diamond continues unparalleled.”

“Safeguarding the technology and trademark from infringement, improper use, and other challenges, benefits not only our OEM Customers, by preserving their market value and time-based exclusivity, but also our shareholders, corporate development partners, and technology partners around the world,” said company Sales Advisor to the Board, Jeffrey G. Miller.

Plastics are excellent insulators, meaning they can efficiently trap heat – a quality that can be an advantage in something like a coffee cup sleeve. But this insulating property is less desirable in products such as plastic casings for laptops and mobile phones, which can overheat, in part because the coverings trap the heat that the devices produce.

Now a team of engineers at MIT has developed a polymer thermal conductor — a plastic material that, however counterintuitively, works as a heat conductor, dissipating heat rather than insulating it. The new polymers, which are lightweight and flexible, can conduct 10 times as much heat as most commercially used polymers.

Researchers at MIT have designed a new way to engineer a polymer structure at the molecular level, via chemical vapor deposition. This allows for rigid, ordered chains, versus the messy, 'spaghetti-like strands' that normally make up a polymer. This chain-like structure enables heat transport both along and across chains. Credit: MIT News Office / Chelsea Turner

Researchers at MIT have designed a new way to engineer a polymer structure at the molecular level, via chemical vapor deposition. This allows for rigid, ordered chains, versus the messy, ‘spaghetti-like strands’ that normally make up a polymer. This chain-like structure enables heat transport both along and across chains. Credit: MIT News Office / Chelsea Turner

“Traditional polymers are both electrically and thermally insulating. The discovery and development of electrically conductive polymers has led to novel electronic applications such as flexible displays and wearable biosensors,” says Yanfei Xu, a postdoc in MIT’s Department of Mechanical Engineering. “Our polymer can thermally conduct and remove heat much more efficiently. We believe polymers could be made into next-generation heat conductors for advanced thermal management applications, such as a self-cooling alternative to existing electronics casings.”

Xu and a team of postdocs, graduate students, and faculty, have published their results today in Science Advances. The team includes Xiaoxue Wang, who contributed equally to the research with Xu, along with Jiawei Zhou, Bai Song, Elizabeth Lee, and Samuel Huberman; Zhang Jiang, physicist at Argonne National Laboratory; Karen Gleason, associate provost of MIT and the Alexander I. Michael Kasser Professor of Chemical Engineering; and Gang Chen, head of MIT’s Department of Mechanical Engineering and the Carl Richard Soderberg Professor of Power Engineering.

Stretching spaghetti

If you were to zoom in on the microstructure of an average polymer, it wouldn’t be difficult to see why the material traps heat so easily. At the microscopic level, polymers are made from long chains of monomers, or molecular units, linked end to end. These chains are often tangled in a spaghetti-like ball. Heat carriers have a hard time moving through this disorderly mess and tend to get trapped within the polymeric snarls and knots.

And yet, researchers have attempted to turn these natural thermal insulators into conductors. For electronics, polymers would offer a unique combination of properties, as they are lightweight, flexible, and chemically inert. Polymers are also electrically insulating, meaning they do not conduct electricity, and can therefore be used to prevent devices such as laptops and mobile phones from short-circuiting in their users’ hands.

Several groups have engineered polymer conductors in recent years, including Chen’s group, which in 2010 invented a method to create “ultradrawn nanofibers” from a standard sample of polyethylene. The technique stretched the messy, disordered polymers into ultrathin, ordered chains — much like untangling a string of holiday lights. Chen found that the resulting chains enabled heat to skip easily along and through the material, and that the polymer conducted 300 times as much heat compared with ordinary plastics.

But the insulator-turned-conductor could only dissipate heat in one direction, along the length of each polymer chain. Heat couldn’t travel between polymer chains, due to weak Van der Waals forces — a phenomenon that essentially attracts two or more molecules close to each other. Xu wondered whether a polymer material could be made to scatter heat away, in all directions.

Xu conceived of the current study as an attempt to engineer polymers with high thermal conductivity, by simultaneously engineering intramolecular and intermolecular forces — a method that she hoped would enable efficient heat transport along and between polymer chains.

The team ultimately produced a heat-conducting polymer known as polythiophene, a type of conjugated polymer that is commonly used in many electronic devices.

Hints of heat in all directions

Xu, Chen, and members of Chen’s lab teamed up with Gleason and her lab members to develop a new way to engineer a polymer conductor using oxidative chemical vapor deposition (oCVD), whereby two vapors are directed into a chamber and onto a substrate, where they interact and form a film. “Our reaction was able to create rigid chains of polymers, rather than the twisted, spaghetti-like strands in normal polymers.” Xu says.

In this case, Wang flowed the oxidant into a chamber, along with a vapor of monomers – individual molecular units that, when oxidized, form into the chains known as polymers.

“We grew the polymers on silicon/glass substrates, onto which the oxidant and monomers are adsorbed and reacted, leveraging the unique self-templated growth mechanism of CVD technology,” Wang says.

Wang produced relatively large-scale samples, each measuring 2 square centimeters – about the size of a thumbprint.

“Because this sample is used so ubiquitously, as in solar cells, organic field-effect transistors, and organic light-emitting diodes, if this material can be made to be thermally conductive, it can dissipate heat in all organic electronics,” Xu says.

The team measured each sample’s thermal conductivity using time-domain thermal reflectance — a technique in which they shoot a laser onto the material to heat up its surface and then monitor the drop in its surface temperature by measuring the material’s reflectance as the heat spreads into the material.

“The temporal profile of the decay of surface temperature is related to the speed of heat spreading, from which we were able to compute the thermal conductivity,” Zhou says.

On average, the polymer samples were able to conduct heat at about 2 watts per meter per kelvin – about 10 times faster than what conventional polymers can achieve. At Argonne National Laboratory, Jiang and Xu found that polymer samples appeared nearly isotropic, or uniform. This suggests that the material’s properties, such as its thermal conductivity, should also be nearly uniform. Following this reasoning, the team predicted that the material should conduct heat equally well in all directions, increasing its heat-dissipating potential.

Going forward, the team will continue exploring the fundamental physics behind polymer conductivity, as well as ways to enable the material to be used in electronics and other products, such as casings for batteries, and films for printed circuit boards.

“We can directly and conformally coat this material onto silicon wafers and different electronic devices” Xu says. “If we can understand how thermal transport [works] in these disordered structures, maybe we can also push for higher thermal conductivity. Then we can help to resolve this widespread overheating problem, and provide better thermal management.”

Mattson Technology introduces Novyka product family, an innovative technology for atomic level surface treatment and ultra-selective etching of extremely thin and delicate materials for continued scaling of 3D logic and memory devices.

“There are significant challenges in scaling with 3D structures for advanced memory and logic chips that include small, narrow, deep and complicated features composed of thin layers of different materials. Among these manufacturing challenges is selective removal of certain layers without damaging or removing other layers and without affecting other features,” said Dr. Subhash Deshmukh, Chief Business Officer of Mattson Technology. “Another challenge is cleaning of these complex structures, as wet chemistry is no longer able to meet the requirements of cleaning the very bottom of the high-aspect ratio features while maintaining device structure integrity.”

“Our new Novyka™ products offer proprietary chemistries in surface cleaning, surface treatment and surface modification. The unique designs of Novyka™ products further extend to enable ultra-high selectivity in removal of thin and delicate layers in 3D device structures,” said Dr. Michael Yang, Executive Vice President and Chief Technology Officer of Mattson Technology. “In addition to delivering the most innovative process solutions to some of the key technical challenges in the industry, Novyka™ products have the lowest running cost, or the best total cost of ownership in their class.”

“We are very excited about the potential of Novyka products as we are working closely with several of our most advanced customers on a variety of leading edge applications. With Mattson Technology achieving record revenue and profit in 2017, we continue to relentlessly drive technology innovations and provide uncompromising service to our global customer base,” commented Dr. Allen Lu, CEO and President of Mattson Technology.

Mattson Technology, a Delaware Company, headquartered in Fremont, California, designs, manufactures, markets and supports semiconductor wafer processing equipment. Mattson’s dry strip, plasma etch, rapid thermal processing and millisecond annealing equipment are used in high volume manufacturing by leading memory and logic chip makers around the world.

No dust mops needed here. The inside of a chip factory is cleaner than about any other place you can visit on Earth. To avoid contaminating the chip-making process, the air in an Intel fab clean room is filtered to 1,000 times fewer airborne particles than a sterile hospital operating room.

The “Team Room” inside Intel’s Fab D1X in Hillsboro, Oregon, is unique.

It’s the sole conference room inside this entire multibillion-dollar factory. Though the fab sprawls over four football fields, every square foot is supremely expensive and valuable. That’s why Intel designed leading-edge Fab D1X with one and only room like this.

Intel operations leaders gather for the daily "8:20" – a morning huddle inside Fab D1X to ensure that the Hillsboro, Oregon, chip factory is running smoothly. Up to 30 people may squeeze into this room to confer on factory tool status, parts availability, operating forecasts, experts who may be needed or other urgent issues. The fab – the size of four football fields – runs 24/7/365. (Credit: Walden Kirsch/Intel Corporation)

Intel operations leaders gather for the daily “8:20” – a morning huddle inside Fab D1X to ensure that the Hillsboro, Oregon, chip factory is running smoothly. Up to 30 people may squeeze into this room to confer on factory tool status, parts availability, operating forecasts, experts who may be needed or other urgent issues. The fab – the size of four football fields – runs 24/7/365. (Credit: Walden Kirsch/Intel Corporation)

Anything entering the fab – including the Fab D1X Team Room – must be thoroughly scrubbed or swabbed. Human skin and hair must be almost entirely covered. Workers wear head-to-toe bunny suits, protective glasses, two pairs of gloves, booties, hoods, and face masks. Workers often recognize one another by their build or their gait, not their face.

In the D1X Team Room, anything that could shed particulates is verboten. No makeup, for example. Common supplies like paper and pencils are off-limits too – they both can create micro-dust. Only ink pens and special fab-approved synthetic paper are allowed in. This is the first photo inside the D1X Team Room ever shared externally. See more images from Intel’s fabs: Intel Manufacturing Images

Single crystal tin selenide (SnSe) is a semiconductor and an ideal thermoelectric material; it can directly convert waste heat to electrical energy or be used for cooling. When a group of researchers from Case Western Reserve University in Cleveland, Ohio, saw the graphene-like layered crystal structure of SnSe, they had one of those magical “aha!” moments.

Electric charges in a nanostructured tin selenide (SnSe) thin film flow from the hot end to the cold end of the material and generate a voltage. Credit: Xuan Gao

Electric charges in a nanostructured tin selenide (SnSe) thin film flow from the hot end to the cold end of the material and generate a voltage. Credit: Xuan Gao

The group reports in the Journal of Applied Physics, from AIP Publishing, that they immediately recognized this material’s potential to be fabricated in nanostructure forms. “Our lab has been working on two-dimensional semiconductors with layered structures similar to graphene,” said Xuan Gao, an associate professor at Case Western.

Nanomaterials with nanometer-scale dimensions — such as thickness and grain size — have favorable thermoelectric properties. This inspired the researchers to grow nanometer-thick nanoflakes and thin films of SnSe to further study its thermoelectric properties.

The group’s work centers on the thermoelectric effect. They study how the temperature difference in a material can cause charge carriers — electrons or holes — to redistribute and generate a voltage across the material, converting thermal energy into electricity.

“Applying a voltage on a thermoelectric material can also lead to a temperature gradient, which means you can use thermoelectric materials for cooling,” said Gao. “Generally, materials with a high figure of merit have high electrical conductivity, a high Seebeck coefficient — generated voltage per Kelvin of temperature difference within a material — and low thermal conductivity,” he said.

A thermoelectric figure of merit, ZT, indicates how efficiently a material converts thermal energy to electrical energy. The group’s work focuses on the power factor, which is proportional to ZT and indicates a material’s ability to convert energy, so they measured the power factor of the materials they made.

To grow SnSe nanostructures, they used a chemical vapor deposition (CVD) process. They thermally evaporated a tin selenide powder source inside an evacuated quartz tube. Tin and selenium atoms react on a silicon or mica growth wafer placed at the low-temperature zone of the quartz tube. This causes SnSe nanoflakes to form on the surface of the wafer. Adding a dopant element like silver to SnSe thin films during material synthesis can further optimize its thermoelectric properties.

At the start, “the nanostructure SnSe thin films we fabricated had a power factor of only ~5 percent of that of single crystal SnSe at room temperature,” said Shuhao Liu, an author on the paper. But, after trying a variety of dopants to improve the material’s power factor, they determined that “silver was the most effective — resulting in a 300 percent power factor improvement compared to undoped samples,” Liu said. “The silver-doped SnSe nanostructured thin film holds promise for a high figure of merit.”

In the future, the researcher hope that SnSe nanostructures and thin films may be useful for miniaturized, environmentally friendly, low-cost thermoelectric and cooling devices.