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A new progress in the scaling of semiconductor quantum dot based qubit has been achieved at Key Laboratory of Quantum Information and Synergetic Innovation Center of Quantum Information & Quantum Physics of USTC. Professor GUO Guoping with his co-workers, XIAO Ming, LI Haiou and CAO Gang, designed and fabricated a quantum processor with six quantum dots, and experimentally demonstrated quantum control of the Toffoli gate. This is the first time for the realization of the Toffoli gate in the semiconductor quantum dot system, which motivates further research on larger scale semiconductor quantum processor. The result was published as ‘Controlled Quantum Operations of a Semiconductor Three-Qubit System ‘ (Physical Review Applied 9, 024015 (2018)).

This is the Toffoli Gate in a three-qubit system. Credit: University of Science and Technology of China

This is the Toffoli Gate in a three-qubit system. Credit: University of Science and Technology of China

Developing the scalable semiconductor quantum chip that is compatible with modern semiconductor-techniques is an important research area. In this area, the fabrication, manipulation and scaling of semiconductor quantum dot based qubits are the most important core technologies. Professor GUO Guoping’s group aims to master these technologies and has been devoted to this area for a long time. Before the demonstration of the three-qubit gate, they have realized ultrafast universal control of the charge qubit based on semiconductor quantum dots in 2013(Nature Communications. 4:1401 (2013)), and achieved the controlled rotation of two charge qubits in 2015(Nature Communications. 6:7681 (2015)).

The Toffoli gate is a three-qubit operation that changed the state of a target qubit conditioned on the state of two control qubits. It can be used for universal reversible classical computation and also forms a universal set of qubit gates in quantum computation together with a Hadamard gate. Furthermore, it is a key element in quantum error correction schemes. Implementation of the Toffoli gate with only single- and two-qubit operations requires six controlled-NOT gates and ten single-qubit operations.

As a result, a single-step Toffoli gate can reduce the number of quantum operations dramatically, which can break the limit of coherence time and improve the efficiency of quantum computing. Researchers from Guo’s group found the T-shaped six quantum dot architecture with openings between control qubits and the target qubit can strengthen the coupling between qubits with different function and minimize it between qubits with the same function, which satisfies the requirements of the Toffoli gate well. Using this architecture with optimized high frequency pulses, researchers demonstrated the Toffoli gate in semiconductor quantum dot system in the world for the first time, which paves the way and lays a solid foundation for the scalable semiconductor quantum processor.

The reviewer spoke highly of this work, and thought this is an important progress in the field of semiconductor quantum dot based quantum computing.”The work is detailed and clearly demonstrates a high level of experimental technique and would be of high interest to people working in the field of electrostatically defined quantum dots for quantum computation”.

 

The research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry’s first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence Innovus Implementation System and Genus Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

The Cadence Innovus Implementation System is a massively parallel physical implementation system that enables engineers to deliver high-quality designs with optimal power, performance and area (PPA) targets while accelerating time to market. The Cadence Genus Synthesis Solution is a next-generation, high-capacity RTL synthesis and physical synthesis engine that addresses the latest FinFET process node requirements, improving RTL designer productivity by up to 10X. For more information on the Innovus Implementation System, please visit www.cadence.com/go/innovus3nm, and to learn about the Genus Synthesis Solution, visit www.cadence.com/go/genus3nm.

For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions. For more information on EUV technology and 193i technology, visit https://www.imec-int.com/en/articles/imec-presents-patterning-solutions-for-n5-equivalent-metal-layers.

Post place and route layout of 21 nm pitch metal layers

Post place and route layout of 21 nm pitch metal layers

“As process dimensions reduce to the 3nm node, interconnect variation becomes much more significant,” said An Steegen, executive vice president for semiconductor technology and systems at imec. “Our work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated. Also, the Cadence digital solutions offered everything needed for this 3nm implementation. Due to Cadence’s well-integrated flow, the solutions were easy to use, which helped our engineering team stay productive when developing the 3nm rule set.”

“Imec’s state-of-the-art infrastructure enables pre-production innovations ahead of industry demands, making them a critical partner for us in the EDA industry,” said Dr. Chin-Chi Teng, corporate vice president and general manager in the Digital & Signoff Group at Cadence. “Expanding upon the work we did with imec in 2015 on the industry’s first 5nm tapeout, we are achieving new milestones together with this new 3nm tapeout, which can transform the future of mobile designs at advanced nodes.”

Brewer Science, Inc., today from SPIE Advanced Lithography 2018 introduced its OptiLign commercial-quality directed self-assembly (DSA) material set developed in collaboration with Arkema. The OptiLign system currently includes three materials required for self-assembly: block copolymers, neutral layers and guiding layers. Developed together for optimal performance, these DSA materials are manufactured on Brewer Science’s commercial manufacturing equipment and provide a cost-effective path to advanced-node wafer patterning processes for feature sizes down to 12nm.

Although Moore’s law is slowing, many foundries and integrated device manufacturers are continuing efforts to scale to finer nodes. As feature sizes shrink more aggressively with each node, the limits of manufacturing equipment are being stretched, and it has become cost-prohibitive to create them using existing patterning processes like self-aligned double patterning and self-aligned quadruple patterning. While the industry is close to the commercialization of extreme ultraviolet (EUV) lithography, the tool cost will limit its use. DSA offers an alternative to existing processes and can be performed on existing, installed fab tool sets. Additionally, DSA will serve as a complement to EUV when it becomes fully available.

“Taking OptiLign materials from pilot line to commercial-scale production represents the next significant milestone in making DSA a viable option for semiconductor manufacturing,” said

Dr. Srikanth (Sri) Kommu, executive director, Semiconductor Business, Brewer Science Inc. “Historically, the industry has relied on equipment enhancements to reach the next technology node. Now, materials solutions are stepping in to provide that edge and extend tool capabilities. The OptiLign product family is an example of this paradigm shift.”

Brewer Science’s OptiLign family of DSA products provides all the materials needed for self-assembly. Block copolymers define the pattern. Neutral layers allow the pattern to be formed on each layer. Lastly, guiding layers tell the material which way and how to orient. All the materials are designed to work together for optimal performance, and are dependent on material and surface energy. Additionally, through its partnership with Arkema, Brewer Science has tapped into a way to deliver DSA materials that allows for consistent feature sizes via a unique polymer production process. This process allows for the large scale needed to support an entire technology node, as well as a unique polymer quality and reproducibility, all of which sets OptiLign materials apart from the competition.

“Feature size is built into the molecular structure of the DSA materials and can vary from batch to batch, so securing a sub-nanometric reproducibility can be challenging,” explained Dr. Ian Cayrefourcq, Director of Emerging Technologies, Arkema. “Arkema’s special process for formulating large batches of polymers of the same size allows Brewer Science to supply a fab with consistent feature sizes for the technology node’s life span.”

To learn more about OptiLign materials, visit Brewer Science’s booth #110 at SPIE Advanced Lithography 2018, February 25 – March 1, 2018 in San Jose, California.

Researchers at North Carolina State University have developed a new technique that allows them to print circuits on flexible, stretchable substrates using silver nanowires. The advance makes it possible to integrate the material into a wide array of electronic devices.

Silver nanowires have drawn significant interest in recent years for use in many applications, ranging from prosthetic devices to wearable health sensors, due to their flexibility, stretchability and conductive properties. While proof-of-concept experiments have been promising, there have been significant challenges to printing highly integrated circuits using silver nanowires.

Silver nanoparticles can be used to print circuits, but the nanoparticles produce circuits that are more brittle and less conductive than silver nanowires. But conventional techniques for printing circuits don’t work well with silver nanowires; the nanowires often clog the printing nozzles.

“Our approach uses electrohydrodynamic printing, which relies on electrostatic force to eject the ink from the nozzle and draw it to the appropriate site on the substrate,” says Jingyan Dong, co-corresponding author of a paper on the work and an associate professor in NC State’s Edward P. Fitts Department of Industrial & Systems Engineering. “This approach allows us to use a very wide nozzle – which prevents clogging – while retaining very fine printing resolution.”

“And because our ‘ink’ consists of a solvent containing silver nanowires that are typically more than 20 micrometers long, the resulting circuits have the desired conductivity, flexibility and stretchability,” says Yong Zhu, a professor of mechanical engineering at NC State and co-corresponding author of the paper.

“In addition, the solvent we use is both nontoxic and water-soluble,” says Zheng Cui, a Ph.D. student at NC State and lead author of the paper. “Once the circuit is printed, the solvent can simply be washed off.”

What’s more, the size of the printing area is limited only by the size of the printer, meaning the technique could be easily scaled up.

The researchers have used the new technique to create prototypes that make use of the silver nanowire circuits, including a glove with an internal heater and a wearable electrode for use in electrocardiography. NC State has filed a provisional patent on the technique.

“Given the technique’s efficiency, direct writing capability, and scalability, we’re optimistic that this can be used to advance the development of flexible, stretchable electronics using silver nanowires – making these devices practical from a manufacturing perspective,” Zhu says.

SILTECTRA GmbH today reports that it has validated a breakthrough capability for its COLD SPLIT technology. COLD SPLIT is a proven wafer-thinning technique for substrate materials like silicon carbide (SiC), gallium nitride (GaN), silicon (Si) and sapphire. A disruptive laser-based technology, COLD SPLIT out-performs traditional grinding methods by thinning wafers to 100 microns and below in minutes, with virtually no material loss. Now, thanks to a novel adaptation known as “twinning,” SILTECTRA has demonstrated that COLD SPLIT can reclaim substrate material generated (and previously wasted) during backside grinding, and create a second fully optimizable bonus wafer in the process.

The breakthrough enriches SILTECTRA’s wafering solution and promises substantial benefits for manufacturers of SiC-based ICs like power electronics and RF devices. SILTECTRA believes that the solution’s combined advantages which include fewer process steps, potentially lower equipment costs, and ultra-efficient use of substrate material, could reduce total device production costs by as much as 30 percent.

SILTECTRA validated the process by producing a GaN on SiC high electron-mobility power transistor (HEMT) device on a split-off (or “twinned”) wafer at its new state-of-the-art facility in Dresden. The HEMT showed results that were superior to a non- COLD- SPLIT-enabled HEMT when measured for CMP characterization, as well as GaN EPI, metal layer and gate layer outcomes.

Leading integrated device manufacturers (IDMs) are now evaluating the technology.

SILTECTRA’s CEO, Dr. Harald Binder, called “twinning” the “holy grail” on the company’s technology roadmap, and noted that the breakthrough was achieved ahead of schedule. “We were confident that we could not only produce a faster and cheaper thinning solution for substrates like SiC, but that we could double the value for customers by extending COLD SPLIT’s reach to create a twin wafer from material previously lost during backside grinding,” he said. “We’re thrilled to report the validation milestone, and excited to help leading IDMs realize new performance and cost benefits in their manufacturing operations.”

New substrate materials present new lower-cost manufacturing imperatives

SiC is expected to be the go-to substrate for the production of power electronics, RF, and other devices. Devices made from SiC have a smaller form-factor than those manufactured on silicon, and can handle higher voltages and frequencies with lower power consumption. Although SiC is substantially more expensive than silicon, the market is growing fast thanks to the substrate’s inherent enabling advantages. Not surprisingly, IDMs are seeking new technologies to cut the cost of producing devices based on SiC and other costly substrates.

Until now, the traditional method to thin wafers to less than 20 percent of the original thickness was grinding, which involves the use of expensive diamond grinding wheels. While valued as a reliable solution for silicon, certain challenges make it difficult for grinding to achieve the extreme level of thinness required for SiC-based devices. Unlike silicon, which is relatively soft, SiC is an extraordinarily hard substance (second only to the hardness of a diamond), which makes cutting and grinding arduous and expensive. What’s more, grinding is not a fast process, and the cost of consumables for the grinding wheels can be substantial. Finally, grinding generates material loss, and the process lowers overall yield, which further drives up cost.

The COLD SPLIT advantage

SILTECTRA engineered COLD SPLIT as a faster, higher-yield, lower-cost alternative to grinding for advanced substrates like SiC. The technique employs a chemical-physical process that uses thermal stress to generate a force that splits the material with exquisite precision along the desired plane. The solution accomplishes the thinning task in minutes instead of an hour like traditional grinding tools, and cuts material loss by as much as 90 percent.

The “twinning” breakthrough extends COLD SPLIT’s capabilities. The adaptation provides a simple way for IDMs to avoid expensive kerf-loss when slicing ingots or boules into wafers. It effectively replaces backside grinding processes, while producing an identical wafer primed for a second device run.

SILTECTRA is qualifying the process on customers’ SiC material at its newly extended facility in Dresden, while preparing to apply the COLD SPLIT technique to additional substrate materials. The company also provides wafering and thinning services at the same location.

Imec continues to advance the readiness of EUV lithography with particular focus on EUV single exposure of Logic N5 metal layers, and of aggressive dense hole arrays. Imec’s approach to enable EUV single patterning at these dimensions is based on the co-optimization of various lithography enablers, including materials, metrology, design rules, post processing and a fundamental understanding of critical EUV processes. The results, that will be presented in multiple papers at this week’s 2018 SPIE Advanced Lithography Conference, are aimed at significantly impacting the technology roadmap and wafer cost of near-term technology nodes for logic and memory.

With the industry making significant improvements in EUV infrastructure readiness, first insertion of EUV lithography in high-volume manufacturing is expected in the critical back-end-of-line metal and via layers of the foundry N7 Logic technology node, with metal pitches in the range of 36–40nm.  Imec’s research focuses on the next node (32nm pitch and below), where various patterning approaches are being considered. These approaches vary considerably in terms of complexity, wafer cost, and time to yield, and include variations of EUV multipatterning, hybrid EUV and immersion multipatterning, and EUV single expose. At SPIE last year, imec presented many advances in hybrid multipatterning and revealed various challenges of the more cost-effective EUV single exposure solution. This year, imec and its partners show considerable progress towards enabling these dimensions with EUV single exposure.

Imec’s path comprises a co-optimization of various lithography enablers, including resist materials, stack and post processing, metrology, computational litho and design-technology co-optimization, and a fundamental understanding of EUV resist reaction mechanisms and of stochastic effects. Based on this comprehensive approach, imec has demonstrated promising advances including initial electrical results, on EUV single exposure focusing on two primary use cases: logic N5 32nm pitch metal-2 layer and 36nm pitch contact hole arrays.

Working with its many materials partners, imec assessed different resist materials strategies, including chemically amplified resists, metal-containing resists and sensitizer-based resists.  Particular attention was paid to the resist roughness, and to nano-failures such as nanobridges, broken lines or missing contacts that are induced by the stochastic EUV patterning regime. These stochastic failures are currently limiting the minimum dimensions for single expose EUV. Based on this work, imec delved into the fundemental understanding of stochastics and identified the primary dependencies influencing failures. Additionally, various metrology techniques and hybrid strategies have been employed to ensure an accurate picture of the reality of stochastics. Imec will report on this collective work, demonstrating the performance of various line-space and contact hole resists.

As resist materials advances alone will likely be inssufient to meet the requirements, imec has also focused on co-optimizing the photomask, film stack, EUV exposures and etch towards an integrated patterning flow to achieve full patterning of the structures. This was done using computational lithography techniques such as optical proximity correction and source mask optimization, complemented by design-technology co-optimization to reduce standard library cell areas. Finally, etch-based post-processing techniques aimed at smoothing the images after the lithography steps yields encouraging results for dense features. Co-optimization of these mulitple knobs is key to achieving optimized patterning and edge placement error control.

Greg McIntyre, Director of advanced patterning at imec summarizes: “We feel these are very promising advances towards enabling EUV to reliably achieve single patterning at these aggressive dimensions.  This would significantly impact the cost effectiveness of patterning solutions for the next few technology nodes.”

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In January, Gigaphoton Inc. (Head office: Oyama City, Tochigi Prefecture. President & CEO: Katsumi Uranaka), a major manufacturer of lithography light sources, announced the shipment of an ArF Excimer Laser for advanced immersion exposure (lithography) devices, the “GT65A” Unit 1, as a new product that meets the growing demand for semiconductors in recent years. The new technology of the GT65A significantly contributes to the rise in productivity of lithography equipment by providing stable operation of the laser and improvement of process margins.

The GT65A will also deliver a 50% reduction in service downtime. This key feature is realized by increasing chamber lifetime by 30% as well as improving maintenance efficiency through the utilization of extensive service data expertise acquired through many years of successful service execution.

In addition, the stabilization technology “eMPL Solid” and the control function “hMPL,” which form the spectrum control function, enable the improvement of CD uniformity as well as expanding process latitude.

Furthermore, the GT65A has successfully eliminated the need to use helium gas. Due to this, we are able to contribute to enhancing customers’ sustainability and CSR activities by not only reducing environmental impact, but also by greatly reducing risks associated with future helium gas supply deficits and price increases.

Katsumi Uranaka, President & CEO of Gigaphoton commented, “With the boom in recent years of the semiconductor market, improving the availability of lithography equipment is an important issue for each manufacturer. With the new technology in line with our new roadmap ‘RAM Enhancement,’ we have further strengthened and improved the Reliability, Availability and Maintainability of lithography light sources, contributing to the semiconductor manufacturing industry.”

Peter Trefonas, Ph.D., corporate fellow in Dow Electronic Materials, has recently been elected a Fellow of SPIE, for achievements in design for manufacturing and compact modeling.

SPIE, the international society for optics and photonics, will promote 73 new Fellows of the Society this year, to recognize the significant scientific and technical contributions of each in the multidisciplinary fields of optics, photonics, and imaging. SPIE Fellows are honored for their technical achievements and for their service to the general optics community and to SPIE in particular.

Trefonas has proven himself to be a leader in advanced lithographic technology with numerous highly cited and pioneering papers in key areas of advanced lithography. He contributed to the fundamental investigations of resist chemical mechanisms, such as polyphotolysis, a mechanism of nonlinear development and dissolution rate models based on first principles. He also contributed papers on percolation and reactive diffusion mechanisms. Trefonas authored some of the first papers on shot noise and stochastic effects, as well as the first paper on fractal analysis of development, and the first paper on information theory of lithography. He is coauthor on a simple method to measure the photoacid quantum efficiency, and contributed to a prominent paper on extreme ultraviolet (EUV) stochastics and stochastic development model. He has also published groundbreaking work on deterministic bottom-up/top-down materials designs.

Trefonas has given extensive service to the global optics community, through published literature and his role in technical conferences. He authored significant sections of the ITRS Semiconductor Roadmap, content dedicated to emerging materials. He organized and chaired a conference on emerging display materials for the Materials Research Society, chaired multiple conferences on microlithography for IEEE, and organized and chaired a conference on directed self-assembly (DSA) and block copolymers for the American Physical Society. As a lecturer, he has given full-day tutorials on lithography and antireflectant coatings at multiple locations in the US, Europe, and Asia. He is also helping to build up the next generation of innovators, responsible for hiring and mentoring over 40 scientists who are currently active and contributing to the science and materials of great interest to the optical community.

A long-time member of SPIE, Trefonas has also given significant service to the Society. He has published 41 papers in the Proceedings of SPIE and has published papers in the Journal of Micro/Nanolithography, MEMS, and MOEMS. He is currently an active reviewer of papers on lithographic materials for SPIE journals.

Trefonas’ work has been recognized with many prestigious honors and awards. Among them are the Society of Chemical Industry Perkin Medal for contributions in industrial chemistry, the American Chemical Society Heroes of Chemistry Award for organic fast plasma etch antireflectants, the C. Grant Willson Award for best oral paper at SPIE Advanced Lithography, Rohm and Haas Technology Awards for antireflectants and 248nm resists, the Shipley R&D Innovation Award for i-line photoresists, and the Monsanto Ex Obscura Award for creativity in innovation. He has also recently been elected as a member of the National Academy of Engineering.

Trefonas will be recognized as a new SPIE Fellow at SPIE Advanced Lithography later this month in San Jose, California.

Cymer, a developer of lithography light sources used by chipmakers to pattern advanced semiconductor chips, today announced the first shipment of the newly qualified XLR 800ix light source that improves performance and productivity, as well as lowers cost-of-ownership for leading-edge argon fluoride (ArF) immersion lithography systems.

Several leading semiconductor manufacturers received early access upgrades to the XLR 800ix and their performance exceeded specifications, achieving less than two femtometers total bandwidth variation in every exposure field. This is about 10 times better than existing technology used today.

As chipmakers extend the use of ArF immersion light sources with multi-patterning to the sub-10 nm technology nodes, it becomes increasingly critical to reduce variability across all processes. In partnership with chipmakers, Cymer found that lower bandwidth variation can lead to lower critical dimension (CD) variation, which improves patterning performance both within and wafer-to-wafer. The XLR 800ix introduces new bandwidth stabilization technology, enabling an eight times improvement in bandwidth measurement fidelity, which can be used to tightly control bandwidth stability.

“We are seeing a strong pull to upgrade our installed base light sources to the newest configuration because the XLR 800ix’s performance far exceeds customers’ expectations,” said David Knowles, vice president of the product development group at Cymer. “From technology improvements to application enhancements, the XLR 800ix brings together all our strengths into one platform to deliver powerful results for our customers.”

The XLR 800ix also delivers productivity and cost-of-ownership improvements, enabling a 33% increase in time between service intervals to 40 billion pulses. This is driven by Cymer’s new field-tested chamber and optics modules, which are in production in more than 250 XLR systems. These enhancements also support Cymer’s sustainability initiatives, by lowering total system power consumption by several percentage points.

A silicon-based quantum computing device could be closer than ever due to a new experimental device that demonstrates the potential to use light as a messenger to connect quantum bits of information — known as qubits — that are not immediately adjacent to each other. The feat is a step toward making quantum computing devices from silicon, the same material used in today’s smartphones and computers.

In a step forward for quantum computing in silicon -- the same material used in today's computers -- researchers successfully coupled a single electron's spin, represented by the dot on the left, to light, represented as a wave passing over the electron, which is trapped in a double-welled silicon chamber known as a quantum dot. The goal is to use light to carry quantum information to other locations on a futuristic quantum computing chip. Credit: Image courtesy of Emily Edwards, University of Maryland.

In a step forward for quantum computing in silicon — the same material used in today’s computers — researchers successfully coupled a single electron’s spin, represented by the dot on the left, to light, represented as a wave passing over the electron, which is trapped in a double-welled silicon chamber known as a quantum dot. The goal is to use light to carry quantum information to other locations on a futuristic quantum computing chip. Credit: Image courtesy of Emily Edwards, University of Maryland.

The research, published in the journal Nature, was led by researchers at Princeton University in collaboration with colleagues at the University of Konstanz in Germany and the Joint Quantum Institute, which is a partnership of the University of Maryland and the National Institute of Standards and Technology.

The team created qubits from single electrons trapped in silicon chambers known as double quantum dots. By applying a magnetic field, they showed they could transfer quantum information, encoded in the electron property known as spin, to a particle of light, or photon, opening the possibility of transmitting the quantum information.

“This is a breakout year for silicon spin qubits,” said Jason Petta, professor of physics at Princeton. “This work expands our efforts in a whole new direction, because it takes you out of living in a two-dimensional landscape, where you can only do nearest-neighbor coupling, and into a world of all-to-all connectivity,” he said. “That creates flexibility in how we make our devices.”

Quantum devices offer computational possibilities that are not possible with today’s computers, such as factoring large numbers and simulating chemical reactions. Unlike conventional computers, the devices operate according to the quantum mechanical laws that govern very small structures such as single atoms and sub-atomic particles. Major technology firms are already building quantum computers based on superconducting qubits and other approaches.

“This result provides a path to scaling up to more complex systems following the recipe of the semiconductor industry,” said Guido Burkard, professor of physics at the University of Konstanz, who provided guidance on theoretical aspects in collaboration with Monica Benito, a postdoctoral researcher. “That is the vision, and this is a very important step.”

Jacob Taylor, a member of the team and a fellow at the Joint Quantum Institute, likened the light to a wire that can connect spin qubits. “If you want to make a quantum computing device using these trapped electrons, how do you send information around on the chip? You need the quantum computing equivalent of a wire.”

Silicon spin qubits are more resilient than competing qubit technologies to outside disturbances such as heat and vibrations, which disrupt inherently fragile quantum states. The simple act of reading out the results of a quantum calculation can destroy the quantum state, a phenomenon known as “quantum demolition.”

The researchers theorize that the current approach may avoid this problem because it uses light to probe the state of the quantum system. Light is already used as a messenger to bring cable and internet signals into homes via fiber optic cables, and it is also being used to connect superconducting qubit systems, but this is one of the first applications in silicon spin qubits.

In these qubits, information is represented by the electron’s spin, which can point up or down. For example, a spin pointing up could represent a 0 and a spin pointing down could represent a 1. Conventional computers, in contrast, use the electron’s charge to encode information.

Connecting silicon-based qubits so that they can talk to each other without destroying their information has been a challenge for the field. Although the Princeton-led team successfully coupled two neighboring electron spins separated by only 100 nanometers (100 billionths of a meter), as published in Science in December 2017, coupling spin to light, which would enable long-distance spin-spin coupling, has remained a challenge until now.

In the current study, the team solved the problem of long-distance communication by coupling the qubit’s information — that is, whether the spin points up or down — to a particle of light, or photon, which is trapped above the qubit in the chamber. The photon’s wave-like nature allows it to oscillate above the qubit like an undulating cloud.

Graduate student Xiao Mi and colleagues figured out how to link the information about the spin’s direction to the photon, so that the light can pick up a message, such as “spin points up,” from the qubit. “The strong coupling of a single spin to a single photon is an extraordinarily difficult task akin to a perfectly choreographed dance,” Mi said. “The interaction between the participants — spin, charge and photon — needs to be precisely engineered and protected from environmental noise, which has not been possible until now.” The team at Princeton included postdoctoral fellow Stefan Putz and graduate student David Zajac.

The advance was made possible by tapping into light’s electromagnetic wave properties. Light consists of oscillating electric and magnetic fields, and the researchers succeeded in coupling the light’s electric field to the electron’s spin state.

The researchers did so by building on team’s finding published in December 2016 in the journal Science that demonstrated coupling between a single electron charge and a single particle of light.

To coax the qubit to transmit its spin state to the photon, the researchers place the electron spin in a large magnetic field gradient such that the electron spin has a different orientation depending on which side of the quantum dot it occupies. The magnetic field gradient, combined with the charge coupling demonstrated by the group in 2016, couples the qubit’s spin direction to the photon’s electric field.

Ideally, the photon will then deliver the message to another qubit located within the chamber. Another possibility is that the photon’s message could be carried through wires to a device that reads out the message. The researchers are working on these next steps in the process.

Several steps are still needed before making a silicon-based quantum computer, Petta said. Everyday computers process billions of bits, and although qubits are more computationally powerful, most experts agree that 50 or more qubits are needed to achieve quantum supremacy, where quantum computers would start to outshine their classical counterparts.

Daniel Loss, a professor of physics at the University of Basel in Switzerland who is familiar with the work but not directly involved, said: “The work by Professor Petta and collaborators is one of the most exciting breakthroughs in the field of spin qubits in recent years. I have been following Jason’s work for many years and I’m deeply impressed by the standards he has set for the field, and once again so with this latest experiment to appear in Nature. It is a big milestone in the quest of building a truly powerful quantum computer as it opens up a pathway for cramming hundreds of millions of qubits on a square-inch chip. These are very exciting developments for the field ¬– and beyond.”