Tag Archives: letter-wafer-tech

Everspin Technologies, Inc. (NASDAQ:MRAM), a developer and manufacturer of discrete and embedded MRAM, today announced the Company recorded revenue for its first 40nm 256Mb STT-MRAM products in the fourth quarter of 2017 and is in the process of ramping its volume production in 2018. This achievement represents an important milestone for STT-MRAM as it is the enabling step for bringing the persistent memory to market.

STT-MRAM is a significant advancement in magnetoresistive random access memory (MRAM) as the densities of this persistent memory technology open up new market opportunities beyond where MRAM has been deployed previously. While there are several companies committed to the MRAM market today, Everspin has the advantage of being the first to reach a volume production for STT-MRAM as well as the only company that is executing on both discrete and embedded MRAM (eMRAM) solutions. The 256Mb STT-MRAM also employs an innovative ST-DDR3 interface, unlocking performance previously unattainable in legacy MRAM components.

“Our 256Mb STT-MRAM is the first ever perpendicular MTJ STT-MRAM entering mass production. This is both a testament to the technical strength of Everspin’s team in design and technology as well as the joint productization strength provided by the collaboration with GLOBALFOUNDRIES,” said Kevin Conley, President and CEO of Everspin Technologies. “This is a bellwether milestone in the evolution of this disruptive technology and we are very excited about the advantages that the capacity and performance of this product brings to our customers.”

“GLOBALFOUNDRIES is excited to see the first STT-MRAM from the Everspin partnership reaching production. The movement of discrete STT-MRAM to volume production is an important milestone on the way to enabling our risk production release of 22FDX eMRAM for GLOBALFOUNDRIES’ customers later this year,” said Dave Eggleston, Vice President of Embedded Memory, GLOBALFOUNDRIES.

Kevin Conley, President and CEO, and Jeff Winzeler, CFO, will present tomorrow at Needham & Company’s 20th Annual Growth Conference from 12:50 – 1:30PM EST at the Lotte New York Palace Hotel. Management will be available to meet with investors at the conference. Copies of any presentation materials will be made available on www.Everspin.com.

A nanostructured gate dielectric may have addressed the most significant obstacle to expanding the use of organic semiconductors for thin-film transistors. The structure, composed of a fluoropolymer layer followed by a nanolaminate made from two metal oxide materials, serves as gate dielectric and simultaneously protects the organic semiconductor – which had previously been vulnerable to damage from the ambient environment – and enables the transistors to operate with unprecedented stability.

Image shows organic-thin film transistors with a nanostructured gate dielectric under continuous testing on a probe station. (Credit: Rob Felt, Georgia Tech)

Image shows organic-thin film transistors with a nanostructured gate dielectric under continuous testing on a probe station. (Credit: Rob Felt, Georgia Tech)

The new structure gives thin-film transistors stability comparable to those made with inorganic materials, allowing them to operate in ambient conditions – even underwater. Organic thin-film transistors can be made inexpensively at low temperature on a variety of flexible substrates using techniques such as inkjet printing, potentially opening new applications that take advantage of simple, additive fabrication processes.

“We have now proven a geometry that yields lifetime performance that for the first time establish that organic circuits can be as stable as devices produced with conventional inorganic technologies,” said Bernard Kippelen, the Joseph M. Pettit professor in Georgia Tech’s School of Electrical and Computer Engineering (ECE) and director of Georgia Tech’s Center for Organic Photonics and Electronics (COPE). “This could be the tipping point for organic thin-film transistors, addressing long-standing concerns about the stability of organic-based printable devices.”

The research was reported January 12 in the journal Science Advances. The research is the culmination of 15 years of development within COPE and was supported by sponsors including the Office of Naval Research, the Air Force Office of Scientific Research, and the National Nuclear Security Administration.

Transistors comprise three electrodes. The source and drain electrodes pass current to create the “on” state, but only when a voltage is applied to the gate electrode, which is separated from the organic semiconductor material by a thin dielectric layer. A unique aspect of the architecture developed at Georgia Tech is that this dielectric layer uses two components, a fluoropolymer and a metal-oxide layer.

“When we first developed this architecture, this metal oxide layer was aluminum oxide, which is susceptible to damage from humidity,” said Canek Fuentes-Hernandez, a senior research scientist and coauthor of the paper. “Working in collaboration with Georgia Tech Professor Samuel Graham, we developed complex nanolaminate barriers which could be produced at temperatures below 110 degrees Celsius and that when used as gate dielectric, enabled transistors to sustain being immersed in water near its boiling point.”

The new Georgia Tech architecture uses alternating layers of aluminum oxide and hafnium oxide – five layers of one, then five layers of the other, repeated 30 times atop the fluoropolymer – to make the dielectric. The oxide layers are produced with atomic layer deposition (ALD). The nanolaminate, which ends up being about 50 nanometers thick, is virtually immune to the effects of humidity.

“While we knew this architecture yielded good barrier properties, we were blown away by how stably transistors operated with the new architecture,” said Fuentes-Hernandez. “The performance of these transistors remained virtually unchanged even when we operated them for hundreds of hours and at elevated temperatures of 75 degrees Celsius. This was by far the most stable organic-based transistor we had ever fabricated.”

For the laboratory demonstration, the researchers used a glass substrate, but many other flexible materials – including polymers and even paper – could also be used.

In the lab, the researchers used standard ALD growth techniques to produce the nanolaminate. But newer processes referred to as spatial ALD – utilizing multiple heads with nozzles delivering the precursors – could accelerate production and allow the devices to be scaled up in size. “ALD has now reached a level of maturity at which it has become a scalable industrial process, and we think this will allow a new phase in the development of organic thin-film transistors,” Kippelen said.

An obvious application is for the transistors that control pixels in organic light-emitting displays (OLEDs) used in such devices as the iPhone X and Samsung phones. These pixels are now controlled by transistors fabricated with conventional inorganic semiconductors, but with the additional stability provided by the new nanolaminate, they could perhaps be made with printable organic thin-film transistors instead.

Internet of things (IoT) devices could also benefit from fabrication enabled by the new technology, allowing production with inkjet printers and other low-cost printing and coating processes. The nanolaminate technique could also allow development of inexpensive paper-based devices, such as smart tickets, that would use antennas, displays and memory fabricated on paper through low-cost processes.

But the most dramatic applications could be in very large flexible displays that could be rolled up when not in use.

“We will get better image quality, larger size and better resolution,” Kippelen said. “As these screens become larger, the rigid form factor of conventional displays will be a limitation. Low processing temperature carbon-based technology will allow the screen to be rolled up, making it easy to carry around and less susceptible to damage.

For their demonstration, Kippelen’s team – which also includes Xiaojia Jia, Cheng-Yin Wang and Youngrak Park – used a model organic semiconductor. The material has well-known properties, but with carrier mobility values of 1.6 cm2/Vs isn’t the fastest available. As a next step, they researchers would like to test their process on newer organic semiconductors that provide higher charge mobility. They also plan to continue testing the nanolaminate under different bending conditions, across longer time periods, and in other device platforms such as photodetectors.

Though the carbon-based electronics are expanding their device capabilities, traditional materials like silicon have nothing to fear.

“When it comes to high speeds, crystalline materials like silicon or gallium nitride will certainly have a bright and very long future,” said Kippelen. “But for many future printed applications, a combination of the latest organic semiconductor with higher charge mobility and the nanostructured gate dielectric will provide a very powerful device technology.”

Insulating oxides are oxygen containing compounds that do not conduct electricity, but can sometimes form conductive interfaces when they’re layered together precisely. The conducting electrons at the interface form a two-dimensional electron gas (2DEG) which boasts exotic quantum properties that make the system potentially useful in electronics and photonics applications.

Researchers at Yale University have now grown a 2DEG system on gallium arsenide, a semiconductor that’s efficient in absorbing and emitting light. This development is promising for new electronic devices that interact with light, such as new kinds of transistors, superconducting switches and gas sensors.

“I see this as a building block for oxide electronics,” said Lior Kornblum, now of the Technion – Israel Institute of Technology, who describes the new research appearing this week in the Journal of Applied Physics, from AIP publishing.

Oxide 2DEGs were discovered in 2004. Researchers were surprised to find that sandwiching together two layers of some insulating oxides can generate conducting electrons that behave like a gas or liquid near the interface between the oxides and can transport information.

Researchers have previously observed 2DEGs with semiconductors, but oxide 2DEGs have much higher electron densities, making them promising candidates for some electronic applications. Oxide 2DEGs have interesting quantum properties, drawing interest in their fundamental properties as well. For example, the systems seem to exhibit a combination of magnetic behaviors and superconductivity.

Generally, it’s difficult to mass-produce oxide 2DEGs because only small pieces of the necessary oxide crystals are obtainable, Kornblum said. If, however, researchers can grow the oxides on large, commercially available semiconductor wafers, they can then scale up oxide 2DEGs for real-world applications. Growing oxide 2DEGs on semiconductors also allows researchers to better integrate the structures with conventional electronics. According to Kornblum, enabling the oxide electrons to interact with the electrons in the semiconductor could lead to new functionality and more types of devices.

The Yale team previously grew oxide 2DEGs on silicon wafers. In the new work, they successfully grew oxide 2DEGs on another important semiconductor, gallium arsenide, which proved to be more challenging.

Most semiconductors react with oxygen in the air and form a disordered surface layer, which must be removed before growing these oxides on the semiconductor. For silicon, removal is relatively easy — researchers heat the semiconductor in vacuum. This approach, however, doesn’t work well with gallium arsenide.

Instead, the research team coated a clean surface of a gallium arsenide wafer with a layer of arsenic. The arsenic protected the semiconductor’s surface from the air while they transferred the wafer into an instrument that grows oxides using a method called molecular beam epitaxy. This allows one material to grow on another while maintaining an ordered crystal structure across the interface.

Next, the researchers gently heated the wafer to evaporate the thin arsenic layer, exposing the pristine semiconductor surface beneath. They then grew an oxide called SrTiO3 on the gallium arsenide and, immediately after, another oxide layer of GdTiO3. This process formed a 2DEG between the oxides.

Gallium arsenide is but one of a whole class of materials called III-V semiconductors, and this work opens a path to integrate oxide 2DEGs with others.

“The ability to couple or to integrate these interesting oxide two-dimensional electron gases with gallium arsenide opens the way to devices that could benefit from the electrical and optical properties of the semiconductor,” Kornblum said. “This is a gateway material for other members of this family of semiconductors.”

Multibeam Corporation today disclosed a new patent that describes the innovative use of e-beam technology for highly localized precision etching in manufacturing advanced memory and logic ICs. The vast improvement enabled by the new patent highlights the company’s leadership in innovating a high-throughput e-beam platform to enhance the industry’s fabrication capability.

Multibeam’s dynamic e-beam platform concurrently addresses four major applications: Complementary E-Beam Lithography (CEBL) to reduce litho cost; Direct Electron Writing (DEW) to enhance device security; Direct Deposition/Etch (DDE) for highly localized precision etch and deposition using directed electron activation; and E-Beam Inspection (EBI) to speed defect detection and yield ramp.

The new patent describes innovative techniques utilizing electrons to enhance selective removal of material from the substrate at precise locations. The techniques are especially useful for advanced-IC fabrication.

The electrons deliver incremental activation energy to initiate chemical reactions on the wafer surface in the plasma, while leveraging existing etch chemistry. The electrons are directed to exact locations in accordance with the layout database, eliminating optical patterning (including multi-patterning) and masks. The electron-enhancement techniques reduce cost and complexity while complementing conventional plasma etching.

The etch process is further enhanced by innovative kinetic lens technology described in the patent. Each e-beam column is augmented with a gas “lens” that increases local partial pressure of select gas components to accelerate desired chemical reactions. The gas lens also eliminates gas-purge cycles to increase throughput.

A photon lens focuses on the etch target to modulate gas adsorption rate and speed etching. The photon lenses can also act as detectors to ensure precision process monitoring and control.

Each e-beam in the multi-column array is individually controlled. Multiple e-beam process chambers can be integrated into a cluster tool for higher throughput.

Complementary E-Beam technology

Multibeam’s expanding IP portfolio in advanced chip-making and device-security applications seeks to complement and enhance established technology solutions, not to supplant them. Electrons have different properties than the photons used in conventional optical lithography. The e-beam can be controlled directly from a database with no need for masks. Multibeam’s proprietary mini-column makes the process chamber compact and small, enabling multi-chamber clustering to boost throughput. The company’s complementary e-beam technology promises to extend IC fabrication capability, benefiting both semiconductor device manufacturers and their customers.

Multibeam Corporation is a leading electron-beam technology innovator in wafer fab equipment.

Semtech Corporation (Nasdaq:SMTC), a supplier of high performance analog and mixed-signal semiconductors and advanced algorithms, announced its next generation LoRa devices and wireless radio frequency (RF) technology (LoRa Technology) chipsets enabling innovative LPWAN use cases for consumers with its advanced technology. Addressing the need for cost-effective and reliable sensor-to-cloud connectivity in any type of RF environment, the new features and capabilities will significantly improve the performance and capability of Internet of Things (IoT) sensor applications that demand ultra-low power, small form factor and long range wireless connectivity with a shortened product development cycle.

The next generation LoRa radios extends Semtech’s link budget by 20% with a 50% reduction in receiver current (4.5 mA) and a high power +22 dBm option. This extends battery life of LoRa-based sensors up to 30%, which reduces the frequency of battery replacement. The extended connectivity range, with the ability to reach deep indoor and outdoor sensor locations, will create new markets as different types of verticals integrate LoRa Technology in their IoT applications including healthcare and pharmaceuticals, media and advertising, logistics/shipping, and asset tracking.

In addition, the new platform has a command interface that simplifies radio configuration and shortens the development cycle, needing only 10 lines of code to transmit or receive a packet, which will allow users to focus on applications. The small footprint, 45% less than the current generation, is highly configurable to meet different application requirements utilizing the global LoRaWAN open standard. The chipsets also supports FSK modulation to allow compatibility with legacy protocols that are migrating to the LoRaWAN™ open protocol for all the performance benefits LoRa Technology provides.

“LPWAN IoT applications are going through a massive transformation, shifting from trials to large deployments in smart cities, buildings, healthcare, logistics, and agriculture,” said Marc Pegulu, Vice President and General Manager for Semtech’s Wireless and Sensing Products Group. “LoRa Technology enables an infinite amount of IoT use cases as Semtech pushes for the last mile of connectivity and reinforces its position as the defacto platform for LPWAN.”

Carbon nanotubes bound for electronics need to be as clean as possible to maximize their utility in next-generation nanoscale devices, and scientists at Rice and Swansea universities have found a way to remove contaminants from the nanotubes.

Rice chemist Andrew Barron, also a professor at Swansea in the United Kingdom, and his team have figured out how to get nanotubes clean and in the process discovered why the electrical properties of nanotubes have historically been so difficult to measure.

Scientists at Rice and Swansea universities have demonstrated that heating carbon nanotubes at high temperatures eliminates contaminants that make nanotubes difficult to test for conductivity. They found when measurements are taken within 4 microns of each other, regions of depleted conductivity caused by contaminants overlap, which scrambles the results. The plot shows the deviation when probes test conductivity from minus 1 to 1 volt at distances greater or less than 4 microns. Credit: Barron Research Group/Rice University

Scientists at Rice and Swansea universities have demonstrated that heating carbon nanotubes at high temperatures eliminates contaminants that make nanotubes difficult to test for conductivity. They found when measurements are taken within 4 microns of each other, regions of depleted conductivity caused by contaminants overlap, which scrambles the results. The plot shows the deviation when probes test conductivity from minus 1 to 1 volt at distances greater or less than 4 microns. Credit: Barron Research Group/Rice University

Like any normal wire, semiconducting nanotubes are progressively more resistant to current along their length. But over the years, conductivity measurements of nanotubes have been anything but consistent. The Rice-Swansea team wanted to know why.

“We are interested in the creation of nanotube-based conductors, and while people have been able to make wires, their conduction has not met expectations,” Barron said. “We wanted to determine the basic science behind the variability observed by other researchers.”

They discovered that hard-to-remove contaminants — leftover iron catalyst, carbon and water — could easily skew the results of conductivity tests. Burning those contaminants away, Barron said, creates new possibilities for carbon nanotubes in nanoscale electronics.

The new study appears in the American Chemical Society journal Nano Letters.

The researchers first made multiwalled carbon nanotubes between 40 and 200 nanometers in diameter and up to 30 microns long. They then either heated the nanotubes in a vacuum or bombarded them with argon ions to clean their surfaces.

They tested individual nanotubes the same way one would test any electrical conductor: by touching them with two probes to see how much current passes through the material from one tip to the other. In this case, tungsten probes were attached to a scanning tunneling microscope.

In clean nanotubes, resistance got progressively stronger as the distance increased, as it should. But the results were skewed when the probes encountered surface contaminants, which increased the electric field strength at the tip. And when measurements were taken within 4 microns of each other, regions of depleted conductivity caused by contaminants overlapped, which further scrambled the results.

“We think this is why there’s such inconsistency in the literature,” Barron said. “If nanotubes are to be the next-generation lightweight conductor, then consistent results, batch-to-batch and sample-to-sample, are needed for devices such as motors and generators as well as power systems.”

Heating the nanotubes in a vacuum above 200 degrees Celsius (392 degrees Fahrenheit) reduced surface contamination, but not enough to eliminate inconsistent results, they found. Argon ion bombardment also cleaned the tubes but led to an increase in defects that degrade conductivity.

Ultimately the researchers discovered vacuum annealing nanotubes at 500 degrees Celsius (932 Fahrenheit) reduced contamination enough to measure resistance accurately.

Barron said engineers who use nanotube fibers or films in devices currently modify the material through doping or other means to get the conductive properties they require. But if the source nanotubes are sufficiently decontaminated, they should be able to get the desired conductivity by simply putting their contacts in the right spot.

“A key result of our work is that if contacts on a nanotube are less than 1 micron apart, the electronic properties of the nanotube change from conductor to semiconductor, due to the presence of overlapping depletion zones, which shrink but are still present even in clean nanotubes,” Barron said.

“This has a potential limiting factor on the size of nanotube-based electronic devices,” he said. “Carbon-nanotube devices would be limited in how small they could become, so Moore’s Law would only apply to a point.”

eVaderis, a semiconductor IP start-up that provides design solutions to improve the functionality, power efficiency and performance of its customers’ semiconductor chips, has successfully demonstrated a fully functioning design platform through an ultra-low-power microcontroller (MCU) in Beyond Semiconductor‘s BA2X product line. The software, system and memory IP developed by eVaderis make Beyond Semiconductor’s new MCU ideally suited for battery-powered applications in IoT and wearable electronics.

By incorporating the latest perpendicular, spin-transfer-torque magnetoresistive random-access memory (STT-MRAM) technology from international R&D institute Imec, Beyond Semiconductor’s new MCU can achieve non-volatile operation with high-speed read/write and low voltage. In addition, the device is designed for manufacturability using GLOBALFOUNDRIES’ 40-nm low-power CMOS production process.

“The tape-out of this innovative MRAM-based, memory-centric MCU demonstrates our proficiency in disruptive, non-volatile embedded IP design and flow for low-power, digital devices,” said Virgile Javerliac, deputy CEO and head of technology and marketing at eVaderis. “We now plan to license the underlying IP to semiconductor manufacturers making sub-40-nm chips.”

“Power consumption is still the key challenge for any battery-powered device,” said Matjaz Breskvar, Beyond Semiconductor’s CEO. “We have been working with eVaderis since the company’s inception to jointly realize a vision of battery-powered, always-on devices with unprecedented energy efficiencies.”

Three megabits (3 Mb) of on-chip memory are fully distributed across the system though different instances, covering different functions such as working memory, configuration, state retention, code execution and data storage. eVaderis’ memory IP architectures are built to be compiler-friendly, helping chip makers to achieve faster time to market.

eVaderis’ innovative memory-centric architecture based on embedded MRAM technology allows a MCU to achieve power, performance and functional gains at the system and software levels. These gains include for instance energy-efficient, non-volatile checkpointing or normally-off/instant-on operation with near zero latency boot.

Researchers at the Center for Integrated Nanostructure Physics, within the Institute for Basic Science (IBS), have shown that defects in monolayer molybdenum disulfide (MoS2) exhibit electrical switching, providing new insights into the electrical properties of this material. As MoS2 is one of the most promising 2D semiconductors, it is expected that these results will contribute to its future use in opto-electronics.

The study on 2-D molybdenum disulfide (MoS2) defects employed low frequency noise measurements and conductive atomic force microscopy (C-AFM). The enlarged image shows an AFM cantilever tip pointing to an area with one sulfur monovacancy (area shaded red). As current flows through the AFM tip and the sample, switching events between different ionization states (neutral and charged -1) are measured. With a radius of around 25 nanometers, the AFM tip covers an area that contains around 1-8 sulfur monovacancies. Credit: IBS, published on Nature Communications

The study on 2-D molybdenum disulfide (MoS2) defects employed low frequency noise measurements and conductive atomic force microscopy (C-AFM). The enlarged image shows an AFM cantilever tip pointing to an area with one sulfur monovacancy (area shaded red). As current flows through the AFM tip and the sample, switching events between different ionization states (neutral and charged -1) are measured. With a radius of around 25 nanometers, the AFM tip covers an area that contains around 1-8 sulfur monovacancies. Credit: IBS, published on Nature Communications

Defects can cause major changes in the properties of a material, leading to either desirable or unwanted effects. For example, petrochemical industry has long taken advantage of the catalytic activity of MoS2edges, characterized by the presence of a high concentration of defects, to produce petroleum products with reduced sulfur dioxide (SO2) emissions. On the other hand, having a pristine material is a must in electronics. Currently, silicon rules the industry, because it can be prepared in a virtually defect-free manner. In the case of MoS2, its suitability for electronic applications is currently limited by the presence of naturally occurring defects. So far, the precise link between these defects and the degraded properties of MoS2 has been an open question.

In IBS, a team of physicists, material scientists, and electrical engineers worked closely together to explore the electronic properties of sulfur vacancies in MoS2 monolayers, using a combination of atomic force microscopy (AFM) and noise analysis. The scientists used a metallic AFM tip to measure the noise signal, i.e., the variation of electrical current passing through a single layer of MoS2 placed on a metal substrate.

The most common defects in MoS2 are instances of missing single sulfur atoms, also known as sulfur monovacancies. In a perfect sample, each sulfur atom has two valence electrons that bind to two molybdenum electrons. However, where a sulfur atom is missing, these two molybdenum electrons are left unsaturated, defining the neutral state (0 state) of the defect. However, the team observed rapid switching events in their noise measurements, indicating the state of the vacancy switched between neutral (0 state) and charged (-1 state).

“The switching between 0 and -1 is happening continuously. While an electron resides at the vacancy for a while, it is missing from the current, such that we observe a current drop,” explains Michael Neumann, one of the co-first authors of the study. “This goes a long way towards understanding the known anomalies of MoS2, and it is very interesting that sulfur vacancies alone are enough to explain these anomalies, without requiring more complex defects.” According to the experiments and earlier calculations, two electrons can be also trapped at the vacancy (-2 state), but this does not seem to be energetically favored.

The new observation that sulfur vacancies can be charged (-1 and -2 states) sheds light on several MoS2 anomalies, including its reduced electron mobility observed in MoS2 monolayer samples: electrons move following the direction of an applied voltage, but get scattered by charged defects. “The -1 state is occupied around 50% of the time, which would lead to scattering of electrons, and thus explain why MoS2 has such poor mobility,” clarifies Neumann. Other MoS2 characteristics which can be explained by this study are the n-type doping of MoS2, and the unexpectedly large resistance at the MoS2-metal junction.

“This research opens up the possibility of developing a new noise nanospectroscopy device capable of mapping one or more defects on a nanoscale scale over a wide area of a 2D material,” concludes the corresponding author Young Hee Lee.

The full study is available on Nature Communications.

Samsung Electronics Co., Ltd. announced today that it has begun mass producing the industry’s first 2nd-generation of 10-nanometer class (1y-nm), 8-gigabit (Gb) DDR4. For use in a wide range of next-generation computing systems, the new 8Gb DDR4 features the highest performance and energy efficiency for an 8Gb DRAM chip, as well as the smallest dimensions.

Samsung_1y-nm_8Gb_DDR4_Chp+Mod

“By developing innovative technologies in DRAM circuit design and process, we have broken through what has been a major barrier for DRAM scalability,” said Gyoyoung Jin, president of Memory Business at Samsung Electronics. “Through a rapid ramp-up of the 2nd-generation 10nm-class DRAM, we will expand our overall 10nm-class DRAM production more aggressively, in order to accommodate strong market demand and continue to strengthen our business competitiveness.”

Samsung’s 2nd-generation 10nm-class 8Gb DDR4 features an approximate 30 percent productivity gain over the company’s 1st-generation 10nm-class 8Gb DDR4. In addition, the new 8Gb DDR4’s performance levels and energy efficiency have been improved about 10 and 15 percent respectively, thanks to the use of an advanced, proprietary circuit design technology. The new 8Gb DDR4 can operate at 3,600 megabits per second (Mbps) per pin, compared to 3,200 Mbps of the company’s 1x-nm 8Gb DDR4.

To enable these achievements, Samsung has applied new technologies, without the use of an EUV process. The innovation here includes use of a high-sensitivity cell data sensing system and a progressive “air spacer” scheme.

In the cells of Samsung’s 2nd-generation 10nm-class DRAM, a newly devised data sensing system enables a more accurate determination of the data stored in each cell, which leads to a significant increase in the level of circuit integration and manufacturing productivity.

The new 10nm-class DRAM also makes use of a unique air spacer that has been placed around its bit lines to dramatically decrease parasitic capacitance**. Use of the air spacer enables not only a higher level of scaling, but also rapid cell operation.

With these advancements, Samsung is now accelerating its plans for much faster introductions of next-generation DRAM chips and systems, including DDR5, HBM3, LPDDR5 and GDDR6, for use in enterprise servers, mobile devices, supercomputers, HPC systems and high-speed graphics cards.

Samsung has finished validating its 2nd-generation 10nm-class DDR4 modules with CPU manufacturers, and next plans to work closely with its global IT customers in the development of more efficient next-generation computing systems.

In addition, the world’s leading DRAM producer expects to not only rapidly increase the production volume of the 2nd-generation 10nm-class DRAM lineups, but also to manufacture more of its mainstream 1st-generation 10nm-class DRAM, which together will meet the growing demands for DRAM in premium electronic systems worldwide.

In today’s “internet of things,” devices connect primarily over short ranges at high speeds, an environment in which surface acoustic wave (SAW) devices have shown promise for years, resulting in the shrinking size of your smartphone. To obtain ever faster speeds, however, SAW devices need to operate at higher frequencies, which limits output power and can deteriorate overall performance. A new SAW device looks to provide a path forward for these devices to reach even higher frequencies.

A team of researchers in China has demonstrated a SAW device that can achieve frequencies six times higher than most current devices. With embedded interdigital transducers (IDTs) on a layer of combined aluminum nitride and diamond, the team’s device was also able to boost output significantly. Their results are published this week in Applied Physics Letters, from AIP Publishing.

“We have found the acoustic field distribution is quite different for the embedded and conventional electrode structures,” said Jinying Zhang, one of the paper’s authors. “Based on the numerical simulation analysis and experimental testing results, we found that the embedded structures bring two benefits: higher frequency and higher output power.”

Surface acoustic wave devices transmit a high-frequency signal by converting electric energy to acoustic energy. This is often done with piezoelectric materials, which are able to change shape in the presence of an electric voltage. IDT electrodes are typically placed on top of piezoelectric materials to perform this conversion.

Ramping up the operational frequency of IDTs — and the overall signal speed — has proven difficult. Most current SAW devices top out at a frequency of about 3 gigahertz, Zhang said, but in principle it is possible to make devices that are 10 times faster. Higher frequencies, however, demand more power to overcome the signal loss, and in turn, some features of the IDTs need to be increasingly small. While a 30 GHz device could transmit a signal more quickly, its operational range becomes limited.

“The major challenge is still the fabrication of the IDTs with such small feature sizes,” Zhang said. “Although we made a lot of efforts, there are still small gaps between the side walls of the electrodes and the piezoelectric materials.”

To ensure that the transducers had the proper feature size, Zhang’s team needed a material with a high acoustic velocity, such as diamond. They then coupled diamond, a material that changes its shape very little with electric voltage, with aluminum nitride, a piezoelectric material, and embedded the IDT inside their new SAW device.

The resulting device operated at a frequency of 17.7 GHz and improved power output by 10 percent compared to conventional devices using SAWs.

“The part which surprised us most is that the acoustic field distribution is quite different for the embedded and conventional electrode structures,” Zhang said. “We had no idea at all about it before.”

Zhang said she hopes this research will lead to SAW devices used in monolithic microwave integrated circuits (MMICs), low-cost, high-bandwidth integrated circuits that are seeing use in a variety of forms of high speed communications, such as cell phones.