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Researchers from North Carolina State University have found that the transfer of triplet excitons from nanomaterials to molecules also creates a feedback mechanism that returns some energy to the nanocrystal, causing it to photoluminesce on long time scales. The mechanism can be adjusted to control the amount of energy transfer, which could be useful in optoelectronic applications.

Pyrenecarboxylic acid-functionalized CdSe quantum dots undergo thermally activated delayed photoluminescence. Credit: Cedric Mongin

Pyrenecarboxylic acid-functionalized CdSe quantum dots undergo thermally activated delayed photoluminescence. Credit: Cedric Mongin

Felix N. Castellano, Goodnight Innovation Distinguished Chair of Chemistry at NC State, had previously shown that semiconductor nanocrystals could transfer energy to molecules, thereby extending their excited state lifetimes long enough for them to be useful in photochemical reactions.

In a new contribution, Castellano and Cédric Mongin, a former postdoctoral researcher currently an assistant professor at École normale supérieure Paris-Saclay in France, have shown that not only does the transfer of triplet excitons extend excited state lifetimes, but also that some of the energy gets returned to the original nanomaterial in the process.

“When we looked at triplet exciton transfers from nanomaterials to molecules, we noticed that after the initial transfer the nanomaterial would still luminesce in a delayed fashion, which was unexpected,” says Castellano. “So we decided to find out what exactly was happening at the molecular level.”

Castellano and Mongin utilized cadmium selenide (CdSe) quantum dots as the nanomaterial and pyrenecarboxylic acid (PCA) as the acceptor molecule. At room temperature, they found that the close proximity of the relevant energy levels created a feedback mechanism that thermally repopulated the CdSe excited state, causing it to photoluminesce.

Taking the experiment one step further, the researchers then systematically varied the CdSe-PCA energy gap by changing the size of the nanocrystals. This resulted in predictable changes to the resultant excited state lifetimes. They also examined this process at different temperatures, yielding results consistent with a thermally activated energy transfer mechanism.

“Depending on relative energy separation, the system can be tuned to behave more like PCA or more like the CdSe nanoparticle,” says Castellano. “It’s a control dial for the system. We can make materials with unique photoluminescent properties simply by controlling the size of the nanoparticle and the temperature of the system.”

More materials for electronic applications could be identified, thanks to the discovery of a new metal-organic framework (MOF) that displays electrical semiconduction with a record high photoresponsivity, by a global research collaboration involving the University of Warwick.

Research published today in Nature Communications shows how high photoconductivity and semiconductor behaviour can be added to MOFs – which already have a huge international focus for their applications in gas storage, sensing and catalysis.

The new work, conducted by Universities in Brazil, the United Kingdom and France – including researchers at Warwick’s Department of Chemistry – found that the new MOF has a photoresponsivity of 2.5 × 105 A.W-1- the highest ever observed.

The MOF has been prepared using cobalt (II) ions and naphthalene diimides and acid as ligands. The structure shows anisotropic redox conduction, according to the directions of the crystal lattice. The conduction mechanism is sensitive to light, and may be modified or modulated according to the incident wavelength.

Photoactive and semiconducting MOFs are rare but desirable for electrical and photoelectrical devices.

These results are the first of this kind concerning MOFs and are the starting point for the possibility of discovery of even more functional materials, displaying properties suitable for practical applications.

The potential for use in electronic components and photoconversion devices, such as solar cells and photocatalysts provides a very exciting future for such materials.

Professor Richard Walton, from Warwick’s Department of Chemistry, commented:

“The material we have discovered paves the way for new applications of a topical family of materials in many areas ranging from technology to energy conversion. We illustrate how MOFs that combine organic and inorganic components can produce unique functional materials from readily available chemicals.

“Our work was underpinned by Warwick’s strengthening collaborative links with Brazilian universities and our exceptional equipment for materials analysis “

In a major step toward making a quantum computer using everyday materials, a team led by researchers at Princeton University has constructed a key piece of silicon hardware capable of controlling quantum behavior between two electrons with extremely high precision. The study was published Dec. 7 in the journal Science.

The researchers demonstrated the ability to control with precision the behavior of two silicon-based quantum bits, or qubits, paving the way for making complex, multi-qubit devices using technology that is less expensive and easier to manufacture than other approaches. Credit: David Zajac, Princeton University

The researchers demonstrated the ability to control with precision the behavior of two silicon-based quantum bits, or qubits, paving the way for making complex, multi-qubit devices using technology that is less expensive and easier to manufacture than other approaches. Credit: David Zajac, Princeton University

The team constructed a gate that controls interactions between the electrons in a way that allows them to act as the quantum bits of information, or qubits, necessary for quantum computing. The demonstration of this nearly error-free, two-qubit gate is an important early step in building a more complex quantum computing device from silicon, the same material used in conventional computers and smartphones.

“We knew we needed to get this experiment to work if silicon-based technology was going to have a future in terms of scaling up and building a quantum computer,” said Jason Petta, a professor of physics at Princeton University. “The creation of this high-fidelity two-qubit gate opens the door to larger scale experiments.”

Silicon-based devices are likely to be less expensive and easier to manufacture than other technologies for achieving a quantum computer. Although other research groups and companies have announced quantum devices containing 50 or more qubits, those systems require exotic materials such as superconductors or charged atoms held in place by lasers.

Quantum computers can solve problems that are inaccessible with conventional computers. The devices may be able to factor extremely large numbers or find the optimal solutions for complex problems. They could also help researchers understand the physical properties of extremely small particles such as atoms and molecules, leading to advances in areas such as materials science and drug discovery.

Building a quantum computer requires researchers to create qubits and couple them to each other with high fidelity. Silicon-based quantum devices use a quantum property of electrons called “spin” to encode information. The spin can point either up or down in a manner analogous to the north and south poles of a magnet. In contrast, conventional computers work by manipulating the electron’s negative charge.

Achieving a high-performance, spin-based quantum device has been hampered by the fragility of spin states — they readily flip from up to down or vice versa unless they can be isolated in a very pure environment. By building the silicon quantum devices in Princeton’s Quantum Device Nanofabrication Laboratory, the researchers were able to keep the spins coherent — that is, in their quantum states — for relatively long periods of time.

To construct the two-qubit gate, the researchers layered tiny aluminum wires onto a highly ordered silicon crystal. The wires deliver voltages that trap two single electrons, separated by an energy barrier, in a well-like structure called a double quantum dot.

By temporarily lowering the energy barrier, the researchers allow the electrons to share quantum information, creating a special quantum state called entanglement. These trapped and entangled electrons are now ready for use as qubits, which are like conventional computer bits but with superpowers: while a conventional bit can represent a zero or a 1, each qubit can be simultaneously a zero and a 1, greatly expanding the number of possible permutations that can be compared instantaneously.

“The challenge is that it’s very difficult to build artificial structures small enough to trap and control single electrons without destroying their long storage times,” said David Zajac, a graduate student in physics at Princeton and first-author on the study. “This is the first demonstration of entanglement between two electron spins in silicon, a material known for providing one of the cleanest environments for electron spin states.”

The researchers demonstrated that they can use the first qubit to control the second qubit, signifying that the structure functioned as a controlled NOT (CNOT) gate, which is the quantum version of a commonly used computer circuit component. The researchers control the behavior of the first qubit by applying a magnetic field. The gate produces a result based on the state of the first qubit: If the first spin is pointed up, then the second qubit’s spin will flip, but if the first spin is down, the second one will not flip.

“The gate is basically saying it is only going to do something to one particle if the other particle is in a certain configuration,” Petta said. “What happens to one particle depends on the other particle.”

The researchers showed that they can maintain the electron spins in their quantum states with a fidelity exceeding 99 percent and that the gate works reliably to flip the spin of the second qubit about 75 percent of the time. The technology has the potential to scale to more qubits with even lower error rates, according to the researchers.

“This work stands out in a worldwide race to demonstrate the CNOT gate, a fundamental building block for quantum computation, in silicon-based qubits,” said HongWen Jiang, a professor of physics and astronomy at the University of California-Los Angeles. “The error rate for the two-qubit operation is unambiguously benchmarked. It is particularly impressive that this extraordinarily difficult experiment, which requires a sophisticated device fabrication and an exquisite control of quantum states, is done in a university lab consisting of only a few researchers.”

SUNY Polytechnic Institute (SUNY Poly) Professor of Nanoengineering Bin Yu has been named a Fellow of the National Academy of Inventors (NAI), the organization announced Tuesday. Election to NAI Fellow status is one of the highest professional accolades bestowed solely to academic inventors who have demonstrated a prolific spirit of innovation in creating or facilitating outstanding inventions that have made a tangible impact on quality of life, economic development, and the welfare of society.

“I am proud to congratulate Dr. Yu on his selection as Fellow of the NAI, which is a strong reflection of his research that has helped to advance cutting-edge nanotechnologies,” said SUNY Poly Interim President Dr. Bahgat Sammakia. “Dr. Yu’s numerous patents and continued SUNY Poly-based research in exciting areas such as nanomaterials and advanced nano-devices continues to hold promise for further developments that can enhance energy efficiency and boost computing speeds to improve the technologies that our society relies on each day.”

Those elected to the rank of NAI Fellow are named inventors on U.S. patents and were nominated by their peers for outstanding contributions to innovation, as well as for patents and licensing, innovative discovery and technology, and providing significant impact on society.

Dr. Yu has a number of significant accomplishments in the areas of nano electronic devices, nano-based sensors, nano-based energy harvesting, emerging data storage devices, next-generation interconnects, and smart nano-manufacturing, including work as the lead researcher for the world’s first 10 nm gate-length 3D transistor FinFET (IEEE-IEDM’2002), and for the world’s first THz silicon logic switch (IEEE-IEDM’2001).

Dr. Yu is the recipient of multiple awards and honors, including the NASA Innovation Award and IBM Faculty Award, and was ranked #3 by the National Science Foundation for Supported Investigators with Most Patents in 2011; as an inventor, he holds more than 300 awarded U.S. patents.

“I am honored that I have been selected to become a National Academy of Inventors Fellow, a powerful recognition of the work undertaken at SUNY Poly which can help to advance technology based on a wide variety of applied nanostrucutures,” said Dr. Yu. “I congratulate my fellow inductees and appreciate the acknowledgement of the importance of these research contributions that have led to more than 300 U.S. patents. I look forward to continuing to pursue efforts utilizing SUNY Poly’s state-of-the-art resources and capabilities for research related to nano-inspired technologies targeted for the next-generation of computing, sensing, and energy generation, as well as research related to emerging nanomaterials for smart nanomanufacturing.”

Dr. Yu has published books and book chapters on topics ranging from graphene-based electronics to 2D layered semiconductor-based emerging solar photovoltaics. He has also served as Editor of IEEE Electron Device Letters from 2001-2007, Associate Editor of IEEE Transactions on Nanotechnology from 2007-2010, and is currently an Editorial Board Member for Nano-Micro Letters and an Editorial Advisory Board Member for Nanoelectronics and Spintronics, among other leadership positions. Dr. Yu has been invited as a speaker to more than 100 highlight/invited talks, seminars, and tutorials to international conferences, universities, industry national labs, and professional societies. He is also an Institute of Electrical and Electronics Engineers (IEEE) Fellow and IEEE Electronic Device Society Distinguished Lecturer. More information about Dr. Yu’s background can be found here.

With the election of the 2017 class there are now 912 NAI Fellows, representing over 250 research universities and governmental and non-profit research institutes. The 2017 Fellows are named inventors on nearly 6,000 issued U.S. patents, bringing the collective patents held by all NAI Fellows to more than 32,000 issued U.S. patents.

Included among all NAI Fellows are more than 100 presidents and senior leaders of research universities and non-profit research institutes; 439 members of the National Academies of Sciences, Engineering, and Medicine; 36 inductees of the National Inventors Hall of Fame; 52 recipients of the U.S. National Medal of Technology and Innovation and U.S. National Medal of Science; 29 Nobel Laureates; 261 AAAS Fellows; 168 IEEE Fellows; and 142 Fellows of the American Academy of Arts & Sciences, among other awards and distinctions.

In April 2018 the 2017 NAI Fellows will be inducted as part of the Seventh Annual NAI Conference of the National Academy of Inventors at the Mayflower Hotel, Autograph Collection in Washington, D.C., and Andrew H. Hirshfeld, U.S. Commissioner for Patents, will provide the keynote address for the induction ceremony.

The 2017 class of NAI Fellows was evaluated by the 2017 Selection Committee, which included 18 members comprising NAI Fellows, U.S. National Medals recipients, National Inventors Hall of Fame inductees, members of the National Academies of Sciences, Engineering, and Medicine and senior officials from the USPTO, National Institute of Standards and Technology, Association of American Universities, American Association for the Advancement of Science, Association of Public and Land-grant Universities, Association of University Technology Managers, and National Inventors Hall of Fame, among other organizations.

University of Alabama at Birmingham physicists have taken the first step in a five-year effort to create novel compounds that surpass diamonds in heat resistance and nearly rival them in hardness.

They are supported by a five-year, $20 million National Science Foundation award to create new materials and improve technologies using the fourth state of matter — plasma.

Plasma — unlike the other three states of matter, solid, liquid and gas — does not exist naturally on Earth. This ionized gaseous substance can be made by heating neutral gases. In the lab, Yogesh Vohra, a professor and university scholar in the UAB Department of Physics, uses plasma to create thin diamonds film. Such films have many potential uses, such as coatings to make artificial joints long-lasting or to maintain the sharpness of cutting tools, developing sensors for extreme environments or creating new super-hard materials.

To make a diamond film, Vohra and colleagues stream a mix of gases into a vacuum chamber, heating them with microwaves to create plasma. The low pressure in the chamber is equivalent to the atmosphere 14 miles above the Earth’s surface. After four hours, the vapor has deposited a thin diamond film on its target.

In a paper in the journal Materials, Vohra and colleagues in the UAB College of Arts and Sciences investigated how the addition of boron, while making a diamond film, changed properties of the diamond material.

It was already known that, if the gases are a mix of methane and hydrogen, the researchers get a microcrystalline diamond film made up of many tiny diamond crystals that average about 800 nanometers in size. If nitrogen is added to that gas mixture, the researchers get nanostructured diamond, made up of extremely tiny diamond crystals averaging just 60 nanometers in size.

In the present study, the Vohra team added boron, in the form of diborane, or B2H6, to the hydrogen/methane/nitrogen feed gas and found surprising results. The grain size in the diamond film abruptly increased from the 60-nanometer, nanostructured size seen with the hydrogen/methane/nitrogen feed gas to an 800-nanometer, microcrystalline size. Furthermore, this change occurred with just minute amounts of diborane, only 170 parts per million in the plasma.

Using optical emission spectroscopy and varying the amounts of diborane in the feed gas, Vohra’s group found that the diborane decreases the amounts of carbon-nitrogen radicals in the plasma. Thus, Vohra said, “our study has clearly identified the role of carbon-nitrogen species in the synthesis of nanostructured diamond and suppression of carbon-nitrogen species by addition of boron to the plasma.”

Since the addition of boron can also change the diamond film from a nonconductor into a semiconductor, the UAB results offer a new control of both diamond film grain size and electrical properties for various applications.

Over the next several years, Vohra and colleagues will probe the use of the microwave plasma chemical vapor deposition process to make thin films of boron carbides, boron nitrides and carbon-boron-nitrogen compounds, looking for compounds that survive heat better than diamonds and also have a diamond-like hardness. In the presence of oxygen, diamonds start to burn at about 1,100 degrees Fahrenheit.

Power electronics, which do things like modify voltages or convert between direct and alternating current, are everywhere. They’re in the power bricks we use to charge our portable devices; they’re in the battery packs of electric cars; and they’re in the power grid itself, where they mediate between high-voltage transmission lines and the lower voltages of household electrical sockets.

Power conversion is intrinsically inefficient: A power converter will never output quite as much power as it takes in. But recently, power converters made from gallium nitride have begun to reach the market, boasting higher efficiencies and smaller sizes than conventional, silicon-based power converters.

Commercial gallium nitride power devices can’t handle voltages above about 600 volts, however, which limits their use to household electronics.

At the Institute of Electrical and Electronics Engineers’ International Electron Devices Meeting this week, researchers from MIT, semiconductor company IQE, Columbia University, IBM, and the Singapore-MIT Alliance for Research and Technology, presented a new design that, in tests, enabled gallium nitride power devices to handle voltages of 1,200 volts.

That’s already enough capacity for use in electric vehicles, but the researchers emphasize that their device is a first prototype manufactured in an academic lab. They believe that further work can boost its capacity to the 3,300-to-5,000-volt range, to bring the efficiencies of gallium nitride to the power electronics in the electrical grid itself.

That’s because the new device uses a fundamentally different design from existing gallium nitride power electronics.

“All the devices that are commercially available are what are called lateral devices,” says Tomás Palacios, who is an MIT professor of electrical engineering and computer science, a member of the Microsystems Technology Laboratories, and senior author on the new paper. “So the entire device is fabricated on the top surface of the gallium nitride wafer, which is good for low-power applications like the laptop charger. But for medium- and high-power applications, vertical devices are much better. These are devices where the current, instead of flowing through the surface of the semiconductor, flows through the wafer, across the semiconductor. Vertical devices are much better in terms of how much voltage they can manage and how much current they control.”

For one thing, Palacios explains, current flows into one surface of a vertical device and out the other. That means that there’s simply more space in which to attach input and output wires, which enables higher current loads.

For another, Palacios says, “when you have lateral devices, all the current flows through a very narrow slab of material close to the surface. We are talking about a slab of material that could be just 50 nanometers in thickness. So all the current goes through there, and all the heat is being generated in that very narrow region, so it gets really, really, really hot. In a vertical device, the current flows through the entire wafer, so the heat dissipation is much more uniform.”

Narrowing the field

Although their advantages are well-known, vertical devices have been difficult to fabricate in gallium nitride. Power electronics depend on transistors, devices in which a charge applied to a “gate” switches a semiconductor material — such as silicon or gallium nitride — between a conductive and a nonconductive state.

For that switching to be efficient, the current flowing through the semiconductor needs to be confined to a relatively small area, where the gate’s electric field can exert an influence on it. In the past, researchers had attempted to build vertical transistors by embedding physical barriers in the gallium nitride to direct current into a channel beneath the gate.

But the barriers are built from a temperamental material that’s costly and difficult to produce, and integrating it with the surrounding gallium nitride in a way that doesn’t disrupt the transistor’s electronic properties has also proven challenging.

Palacios and his collaborators adopt a simple but effective alternative. The team includes first authors Yuhao Zhang, a postdoc in Palacios’s lab, and Min Sun, who received his MIT PhD in the Department of Electrical Engineering and Computer Science (EECS) last spring; Daniel Piedra and Yuxuan Lin, MIT graduate students in EECS; Jie Hu, a postdoc in Palacios’s group; Zhihong Liu of the Singapore-MIT Alliance for Research and Technology; Xiang Gao of IQE; and Columbia’s Ken Shepard.

Rather than using an internal barrier to route current into a narrow region of a larger device, they simply use a narrower device. Their vertical gallium nitride transistors have bladelike protrusions on top, known as “fins.” On both sides of each fin are electrical contacts that together act as a gate. Current enters the transistor through another contact, on top of the fin, and exits through the bottom of the device. The narrowness of the fin ensures that the gate electrode will be able to switch the transistor on and off.

“Yuhao and Min’s brilliant idea, I think, was to say, ‘Instead of confining the current by having multiple materials in the same wafer, let’s confine it geometrically by removing the material from those regions where we don’t want the current to flow,'” Palacios says. “Instead of doing the complicated zigzag path for the current in conventional vertical transistors, let’s change the geometry of the transistor completely.”

Leti, a research institute of CEA Tech, demonstrated significant improvements in the field of memory systems at IEDM 2017 this week.

These include reconfiguring Static Random-Access Memory (SRAM) into Content-Addressable Memory (CAM), improving non-volatile crossbar memories and using advanced Tunnel Field-Effect Transistors (TFET). Another breakthrough presents a high-density SRAM bitcell on Leti’s CoolCubeTM 3D platform, which reduces the area required for memory by 30 percent, while maintaining full device functionality. This breakthrough points the way to easing the major memory bottleneck in more complex systems on chip (SoC), where up to 90 percent of the SoC area might be taken by SRAM.

The breakthroughs were reported Dec. 5 at IEDM 2017 in a paper titled “Advanced Memory Solutions for Emerging Circuits and Systems.”

A key obstacle to shrinking SRAM on SoCs is bitcell-area limitations linked to required performance and yield, both of which become more challenging as technology scales. Lowering system power consumption is also limited by memory, as the SRAM performance and its stability scale less successfully than logic performance at lower voltages. Other memories like CAM might be affected even more by voltage scaling.

“All of these obstacles become particularly important for the Internet of Things, where ultralow-power consumption and the cost of individual nodes are crucial, and SRAM limitations have a big impact on both,” said Bastien Giraud, one of the paper authors.

Leti approached these challenges with a CoolCubeTM SRAM design focusing on the development of a compact and functional four-transistor bitcell, along with other innovations:

  • Reconfiguring memory between the CAM and SRAM, depending on the application
  • Optimizing memory using TFET, focusing on the exploitation of its negative differential-resistance effect to build ultralow-power SRAM, Flip Flops (FF) and refresh-free Dynamic Random Access Memory (DRAM)
  • A new compensation technique for crosspoint memory that reduces the voltage drop and leads to larger memory arrays.

Leti said its proposed CAM/SRAM outperforms memories, with operations at 1.56GHz and 0.13fJ/bit energy per search. In addition, the proposed TFET designs are competitive in terms of area, performance and static power consumption. Leti’s proposed compensation technique in crosspoint memory also enables the design of cost-efficient large memory arrays, while reducing the impact of temporal and spatial variations.

Short-term applications include crossbar circuits for storage-class memory and flexible SOCs with SRAM/CAM re-configurability.

“In the longer term, Leti’s CoolCubeTM technology will be able to deliver very high-density SRAM,” Giraud said. “Enabling TFET-based DRAM and integrating TFET standard cells into CMOS designs will allow circuit designers to take advantage of the best features of both technologies.”

By Inna Skvortsova, SEMI

Electromagnetic interference (EMI) is an increasingly important topic across the global electronics manufacturing supply chain.  Progressively smaller geometries of ICs, lower supply voltages, and higher data rates all make devices and processes more vulnerable to EMI. Electrical noise, EMI-induced signal generated by equipment, and factors such as power line transients affect manufacturing processes, from wafer handling to wire bonding to PCB assembly and test, causing millions of dollars in losses to the industry. Furthermore, conducted emission capable of causing electrical overstress (EOS) can damage sensitive semiconductor devices.  Intel consistently names EOS as the “number one source of damage to IC components.” (Intel® Manufacturing Enabling Guide 2001, 2010, 2016).

While EMC (Electromagnetic Compatibility) standards, such as the European EMC Directive and FCC Testing and Certification, etc. provide limits on allowed emission levels of equipment, once the equipment is installed along with other tools, the EMI levels in actual operating environments can be substantially different and therefore impact the equipment operation, performance, and reliability. For example, (i) Occasional transients induce “extra” pulses in rotary feedback of the servo motor which in time contributes to robotic arm’s erroneous position eventually damaging the wafer; (ii) Combination of high-frequency noise from servo motors and switched mode power supplies in the tool creates difference in voltage between the bonding wire/funnel and the device which causes high current and eventual electrical overstress to the devices; (iii) Wafer probe test provides inconsistent results due to high level of EMI on the wafer chuck caused by a combination of several servo motors in the wafer handler.  Field cases like these illustrate the gap between EMC test requirements and real-life EMI tolerance levels and its impact on semiconductor manufacturing and handling.

EMI on AC power lines

EMI on AC power lines

New standard, SEMI E176-1017, Guide to Assess and Minimize Electromagnetic Interference (EMI) in a Semiconductor Manufacturing Environment, developed by the NA Chapter of the Global Metrics Technical Committee bridges this gap. Targeted to IC manufacturers and anyone handling semiconductor devices, such as PCB assembly and integration of electronic devices, SEMI E176 is a practical guide as well as an educational document. SEMI E176 provides a concise summary of EMI origins, EMI propagation, measurement techniques and recommendations on mitigation of undesirable electromagnetic emission to enable equipment co-existence and proper operation as well as reduction of EOS in its intended usage environment. Specifically, E176 provides recommended levels for different types of EMI based on IC geometries.

“SEMI E176 is likely the only active Standard in the entire industry providing recommendations on both acceptable levels of EMI in manufacturing environments and the means of achieving and maintaining these numbers,” said Vladimir Kraz, co-Chair of the NA Metrics Technical Committee and president of OnFILTER, Inc. “E176 is also unique because it is not limited just to semiconductor manufacturing, but has application across other industries.  Back-end assembly and test, as well as PCB assembly are just as affected by EMI and can benefit from SEMI E176 implementation as there are strong similarities between handling of semiconductor devices in IC manufacturing and in PCB assemblies and prevention of defects is often shared between IC and PCBA manufacturers.”

The newly published SEMI E176 and recently updated SEMI E33-0217, Guide for Semiconductor Manufacturing Equipment Electromagnetic Compatibility (EMC),provide complete documentation for establishing and maintaining low EMI levels in the manufacturing environment.

Undesirable emission has operational, liability and regulatory consequences.  Taming it is a challenging task and requires a comprehensive approach that starts from proper system design practices and ends with developing EMI expertise in the field.  The new SEMI 176 provides practical guidance on reducing EMI to the levels necessary for effective high yield semiconductor manufacturing today and in the future.

SEMI Standards development activities take place throughout the year in all major manufacturing regions. To get involved, join the SEMI International Standards Program at: www.semi.org/standardsmembership.

 

A research group in Japan announced that it has quantified for the first time the impacts of three electron-scattering mechanisms for determining the resistance of silicon carbide (SiC) power semiconductor devices in power semiconductor modules. The university-industry team consisting of researchers from the University of Tokyo and Mitsubishi Electric Corporation has found that resistance under the SiC interface can be reduced by two-thirds by suppressing electron scattering by the charges, a discovery that is expected to help reduce energy consumption in electric power equipment by lowering the resistance of SiC power semiconductors.

Electron scattering under the silicon carbide (SiC) interface is limited by three factors: roughness of the SiC interface, charges under the SiC interface and atomic vibration. Credit: 2017 Mitsubishi Electric Corporation.

Electron scattering under the silicon carbide (SiC) interface is limited by three factors: roughness of the SiC interface, charges under the SiC interface and atomic vibration. Credit: 2017 Mitsubishi Electric Corporation.

Electric power equipment used in home electronics, industrial machinery, trains and other apparatuses requires a combination of maximized efficiency and minimized size. Mitsubishi Electric, a leading Japanese electronics and electrical equipment manufacturer, is accelerating use of SiC devices for power semiconductor modules, which are key components in electric power equipment. SiC power devices offer lower resistance than conventional silicon power devices, so to further lower their resistance it is important to understand correctly the characteristics of the resistance under the SiC interface.

“Until now, however, it had been difficult to measure separately resistance-limiting factors that determine electron scattering,” says Satoshi Yamakawa, senior manager of the SiC Device Development Center at Mitsubishi Electric’s Advanced Technology R&D Center.

Electron scattering focusing on atomic vibration was measured using technology from the University of Tokyo. The impact that charges and atomic vibration have on electron scattering under the SiC interface was revealed to be dominant in Mitsubishi Electric’s analyses of fabricated devices. Although it has been recognized that electron scattering under the SiC interface is limited by three factors, namely, the roughness of the SiC interface, the charges under the SiC interface and the atomic vibration, the contribution of each factor had been unclear. A planar-type SiC metal-oxide-semiconductor field-effect transistor (SiC-MOSFET), in which electrons conduct away from the SiC interface to around several nanometers, was fabricated to confirm the impact of the charges.

“We were able to confirm at an unprecedented level that the roughness of the SiC interface has little effect while charges under the SiC interface and atomic vibration are dominant factors,” says Koji Kita, an associate professor at the University of Tokyo’s Graduate School of Engineering and one of scientists leading the research.

Using an earlier planar-type SiC-MOSFET device for comparison, resistance was reduced by two-thirds owing to suppression of electron scattering, which was achieved by making the electrons conduct away from the charges under the SiC interface. The previous planar-type device has the same interface structure as that of the SiC-MOSFET fabricated by the electronics maker.

For the test, Mitsubishi Electric handled the design, fabrication and analysis of the resistance-limiting factors and the University of Tokyo handled the measurement of electron-scattering factors.

“Going forward, we will continue refining the design and specifications of our SiC MOSFET to further lower the resistance of SiC power devices,” says Mitsubishi Electric’s Yamakawa.

This research achievement was announced at the 63rd International Electron Devices Meeting (IEDM) in San Francisco, California, on December 4, 2017.

Smartphones and computers wouldn’t be nearly as useful without room for lots of apps, music and videos.

Devices tend to store that information in two ways: through electric fields (think of a flash drive) or through magnetic fields (like a computer’s spinning hard disk). Each method has advantages and disadvantages. However, in the future, our electronics could benefit from the best of each.

“There’s an interesting concept,” says Chang-Beom Eom, the Theodore H. Geballe Professor and Harvey D. Spangler Distinguished Professor of Materials Science and Engineering at the University of Wisconsin-Madison. “Can you cross-couple these two different ways to store information? Could we use an electric field to change the magnetic properties? Then you can have a low-power, multifunctional device. We call this a ‘magnetoelectric’ device.”

In research published recently in the journal Nature Communications, Eom and his collaborators describe not only their unique process for making a high-quality magnetoelectric material, but exactly how and why it works.

Physics graduate student Julian Irwin checks equipment in the lab of materials science and engineering Professor Chang-Beom Eom, where researchers have produced a material that could exhibit the best qualities of both solid-state and spinning disk digital storage. Credit: Sarah Page/UW-Madison College of Engineering

Physics graduate student Julian Irwin checks equipment in the lab of materials science and engineering Professor Chang-Beom Eom, where researchers have produced a material that could exhibit the best qualities of both solid-state and spinning disk digital storage. Credit: Sarah Page/UW-Madison College of Engineering

Magnetoelectric materials — which have both magnetic and electrical functionalities, or “orders” — already exist. Switching one functionality induces a change in the other.

“It’s called cross-coupling,” says Eom. “Yet, how they cross-couple is not clearly understood.”

Gaining that understanding, he says, requires studying how the magnetic properties change when an electric field is applied. Up to now, this has been difficult due to the complicated structure of most magnetoelectric materials.

In the past, says Eom, people studied magnetoelectric properties using very “complex” materials, or those that lack uniformity. In his approach, Eom simplified not only the research, but the material itself.

Drawing on his expertise in material growth, he developed a unique process, using atomic “steps,” to guide the growth of a homogenous, single-crystal thin film of bismuth ferrite. Atop that, he added cobalt, which is magnetic; on the bottom, he placed an electrode made of strontium ruthenate.

The bismuth ferrite material was important because it made it much easier for Eom to study the fundamental magnetoelectric cross-coupling.

“We found that in our work, because of our single domain, we could actually see what was going on using multiple probing, or imaging, techniques,” he says. “The mechanism is intrinsic. It’s reproducible — and that means you can make a device without any degradation, in a predictable way.”

To image the changing electric and magnetic properties switching in real time, Eom and his colleagues used the powerful synchrotron light sources at Argonne National Laboratory outside Chicago, and in Switzerland and the United Kingdom.

“When you switch it, the electrical field switches the electric polarization. If it’s ‘downward,’ it switches ‘upward,'” he says. “The coupling to the magnetic layer then changes its properties: a magnetoelectric storage device.”

That change in direction enables researchers to take the next steps needed to add programmable integrated circuits — the building blocks that are the foundation of our electronics — to the material.

While the homogenous material enabled Eom to answer important scientific questions about how magnetoelectric cross-coupling happens, it also could enable manufacturers to improve their electronics.

“Now we can design a much more effective, efficient and low-power device,” he says.