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The 63rd annual IEEE International Electron Devices Meeting (IEDM), to be held December 2-6, 2017 at the Hilton San Francisco Union Square hotel, may go down as one of the most memorable editions for the sheer variety and depth of its talks, sessions, courses and events.

Among the most-anticipated talks are presentations by Intel and Globalfoundries, which will each detail their forthcoming competing FinFET transistor technology platforms in a session on Wednesday morning. FinFET transistors are a major driver of the continuing progress of the electronics industry, and these platforms are as important for their commercial potential as they are for their technical innovations.*

Each year at the IEDM, the world’s best technologists in micro/nano/bioelectronics converge to participate in a technical program consisting of more than 220 presentations, along with other events.

“Those who attend IEDM 2017 will find much that is familiar, beginning with a technical program describing breakthroughs in areas ranging from mainstream CMOS technology to innovative nanoelectronics to medical devices. The Sunday Short Courses are also a perennial favorite because they are not only comprehensive but are also taught by accomplished world experts,” said Dr. Barbara De Salvo, Scientific Director at Leti. “But we have added some new features this year. One is a fourth Plenary session, on Wednesday morning, featuring Nobel winner Hiroshi Amano. Another is a revamped Tuesday evening panel. Not only will it focus on a topic of great interest to many people, it is designed to be more open and less formal.”

Other features of the IEDM 2017 include:

  • Focus Sessions on the following topics: 3D Integration and Packaging; Modeling Challenges for Neuromorphic Computing; Nanosensors for Disease Diagnostics; and Silicon Photonics: Current Status and Perspectives.
  • A vendor exhibition will be held, based on the success of last year’s event at the IEDM.
  • The IEEE Magnetics Society will again host a joint poster session on MRAM (magnetic RAM) in the exhibit area. New for this year, though, is that the Society will also hold its annual MRAM Global Innovation Forum on Thursday, Dec. 7 at the same hotel, enabling IEDM attendees to participate. (Refer to the IEEE Magnetics Society website.) The forum consists of invited talks by leading experts and a panel discussion.

Here are details of some of the events that will take place at this year’s IEDM:

90-Minute Tutorials – Saturday, Dec. 2
These tutorials on emerging technologies will be presented by leading technical experts in each area, with the goal of bridging the gap between textbook-level knowledge and cutting-edge current research.

  • The Evolution of Logic Transistors Toward Low Power and High Performance IoT Applications, Dr. Dae Won Ha, Samsung Electronics
  • Negative Capacitance Transistors, Prof. Sayeef Salahuddin, UC Berkeley
  • Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Prof. Eric Pop, Stanford University
  • Hardware Opportunities in Cognitive Computing: Near- and Far-Term, Dr. Geoffrey Burr, Principal Research Staff Member, IBM Research-Almaden
  • 2.5D Interposers and High-Density Fanout Packaging as Enablers for Future Systems Integration, Dr. Venkatesh Sundaram, Associate Director, Georgia Tech 3D Systems Packaging Research Center
  • Silicon Photonics for Next-Generation Optical Interconnects, Dr. Joris Van Campenhout, Program Director Optical I/O, Imec

Short Courses – Sunday, Dec. 3
The day-long Short Courses provide the opportunity to learn about important developments in key areas, and they enable attendees to network with the industry’s leading technologists.

Boosting Performance, Ensuring Reliability, Managing Variability in Sub-5nm CMOS, organized by Sandy Liao of Intel, will feature the following sections:

  • Transistor Performance Elements for 5nm Node and Beyond, Gen Tsutsui, IBM
  • Multi-Vt Engineering and Gate Performance Control for Advanced FinFET Architecture, Steve CH Hung, Applied Materials
  • Sub-5nm Interconnect Trends and Opportunities, Zsolt Tokei, Imec
  • Transistor Reliability: Physics, Current Status, and Future Considerations, Stephen M. Ramey, Intel
  • Back End Reliability Scaling Challenges, Variation Management, and Performance Boosters for sub-5nm CMOS,Cathyrn Christiansen, Globalfoundries
  • Design-Technology Co-Optimization for Beyond 5nm Node, Andy Wei, TechInsights

Merged Memory-Logic Technologies and Their Applications, organized by Kevin Zhang of TSMC, will feature the following sections:

  • Embedded Non Volatile Memory for Automotive Applications, Alfonso Maurelli, STMicroelectronics
  • 3D ReRAM: Crosspoint Memory Technologies, Nirmal Ramaswamy, Micron
  • Ferroelectric Memory in CMOS Processes, Thomas Mikolajick, Namlab
  • Embedded Memories Technology Scaling & STT-MRAM for IoT & Automotive, Danny P. Shum, Globalfoundries
  • Embedded Memories for Energy-Efficient Computing, Jonathan Chang, TSMC
  • Abundant-Data Computing: The N3XT 1,000X, Subhasish Mitra, Stanford University

Plenary Presentations – Monday, Dec. 4

  • Driving the Future of High-Performance Computing, Lisa Su, President & CEO, AMD
  • Energy-Efficient Computing and Sensing: From Silicon to the Cloud, Adrian Ionescu, Professor, EPFL
  • System Scaling Innovation for Intelligent Ubiquitous Computing, Jack Sun, VP of R&D, TSMC

Plenary Presentation – Wednesday, Dec. 6

  • Development of a Sustainable Smart Society by Transformative Electronics, Hiroshi Amano, Professor, Nagoya University. Dr. Amano received the 2014 Nobel Prize in Physics along with Isamu Akasaki and Shuji Nakamura for the invention of efficient blue LEDs, which sparked a revolution in innovative, energy-saving lighting. His talk will be preceded by the Focus Session on silicon photonics.

Evening Panel Session – Tuesday evening, Dec. 5

  • Where will the Next Intel be Headquartered?  Moderator: Prof. Philip Wong, Stanford

Entrepreneurs Lunch
Jointly sponsored by IEDM and IEEE EDS Women in Engineering, this year’s Entrepreneurs Lunch will feature Courtney Gras, Executive Director for Launch League, a local nonprofit focused on developing a strong startup ecosystem in Ohio. The moderator will be Prof. Leda Lunardi from North Carolina State University. Gras is an engineer by training and an entrepreneur by nature. After leaving her job as a NASA power systems engineer to work for on own startup company, she discovered a passion for building startup communities and helping technology-focused companies meet their goals. Named to the Forbes ’30 Under 30′ list in 2016, among many other recognitions and awards, Gras enjoys sharing her stories of founding a cleantech company with young entrepreneurs. She speaks on entrepreneurship, women in technology and clean energy at venues such as TEDx Budapest, the Pioneers Festival, and the IEEE WIE International Women’s Leadership Conference.

 

On 14-17 November in Munich, SEMICON Europa will co-locate with productronica for the first time, for a focus on innovation and the future of the electronics manufacturing supply chain. Gathering key stakeholders from across the electronics manufacturing supply chain, the extensive range and depth, programs and networking events make the platform a necessity for players across the European electronics industry. SEMICON Europa will take place at Messe München Hall B1.

An Opening Ceremony will include a welcome speech by Ajit Manocha, president and CEO of SEMI, followed by Laith Altimime, president, SEMI Europe, plus four keynotes:

  • Bosch Sensortec: Stefan Finkbeiner, CEO, on how environmental sensing can contribute to a better quality of life in the context of the IoT
  • Rinspeed Inc.: Frank M. Rinderknecht, founder and CEO, on how to create innovative technologies, materials and mobility means of tomorrow
  • SOITEC: Carlos Mazure, CTO, executive VP, on contributions and benefits of engineered substrates solutions and thin-layer transfer technologies, focusing on applications in the smart space
  • TSMC Europe: Maria Marced, president, on opportunities for new business models to apply in the Smart City

“We are at the brink of a new wave of innovation ─ called the “Fourth Industrial Revolution” or “Smart Manufacturing.” It’s driven by connected devices and smart applications known as the IoT. This presents many opportunities for closer collaborations at global level, connecting key players, key ecosystems and building on the strengths of players in the value chain,” said Laith Altimime, president of SEMI Europe.

New programs on Flexible Electronics, Materials, and Automotive expand SEMICON Europa’s impact:

Returning programs include:

Register for programs before 12 November for a discount: http://www.semiconeuropa.org/register

SEMICON Europa offers free programs available on the exhibition show floor, including the TechARENA sessions ─ from MedTech to Lithography, Smart Manufacturing and Photonics, and many other topics.

For the fourth time at SEMICON Europa, INNOVATION VILLAGE will bring early-stage technology companies, the semiconductor industry’s top strategic investors, and leading technology partners together. This year sponsors include the City of Dresden and Volkswagen.

More than ever, there are unique opportunities to network with peers and connect with a large number of stakeholders at SEMICON Europa as attendees gather at the SEMICON CXO Luncheon, SEMI Member Breakfast, and SEMI Networking Night.

Connect! Register here and stay in touch via Twitter at http://www.twitter.com (use #SEMICONEuropa)

Scientists have long searched for the next generation of materials that can catalyze a revolution in renewable energy harvesting and storage.

One candidate appears to be metal-organic frameworks. Scientists have used these very small, flexible, ultra-thin, super-porous crystalline structures to do everything from capturing and converting carbon into fuels to storing hydrogen and other gases. Their biggest drawback has been their lack of conductivity.

Now, according to USC scientists, it turns out that metal-organic frameworks can conduct electricity in the same way metals do.

This opens the door for metal organic-frameworks to one day efficiently store renewable energy at a very large, almost unthinkable scale.

The cobalt-based metal-organic framework used by the USC scientists, with purple representing cobalt, yellow representing sulfur and gray representing carbon. Credit: Smaranda Marinescu

The cobalt-based metal-organic framework used by the USC scientists, with purple representing cobalt, yellow representing sulfur and gray representing carbon. Credit: Smaranda Marinescu

“For the first time ever, we have demonstrated a metal-organic framework that exhibits conductivity like that of a metal. The natural porosity of the metal-organic framework makes it ideal for reducing the mass of material, allowing for lighter, more compact devices” said Brent Melot, assistant professor of chemistry at the USC Dornsife College of Letters, Arts & Sciences.

“Metallic conductivity in tandem with other catalytic properties would add to its potential for renewable energy production and storage” said Smaranda Marinescu, assistant professor of chemistry at the USC Dornsife College.

Their findings were published July 13 in the Journal of the American Chemical Society.

An emerging catalyst for long-term renewable energy storage

Metal-organic frameworks are so porous that they are well-suited for absorbing and storing gases like hydrogen and carbon dioxide. Their storage is highly concentrated: 1 gram of surface area provides the equivalent of thousands of square feet in storage.

Solar has not yet been maximized as an energy source. The earth receives more energy from one hour of sunlight than is consumed in one year by the entire planet, but there is currently no way to use this energy because there is no way to conserve all of it. This intermittency is intrinsic to nearly all renewable power sources, making it impossible to harvest and store energy unless, say, the sun is shining or the wind is blowing.

If scientists and industries could one day regularly reproduce the capability demonstrated by Marinescu, it would go a long way to reducing intermittency, allowing us to finally make solar energy an enduring and more permanent resource.

Metal or semiconductor: why not both?

Metal-organic frameworks are two-dimensional structures that contain cobalt, sulfur, and carbon atoms. In many ways, they very broadly resemble something like graphene, which is also a very thin layer of two-dimensional, transparent material.

As temperature goes down, metals become more conductive. Conversely, as the temperature goes up, it is semiconductors that become more conductive.

In the experiments run by Marinescu’s group, they used a cobalt-based metal-organic framework that mimicked the conductivity of both a metal and semiconductor at different temperatures. The metal-organic framework designed by the scientists demonstrated its greatest conductivity at both very low and very high temperatures.

GLOBALFOUNDRIES today unveiled AutoPro, a new platform designed to provide automotive customers a broad set of technology solutions and manufacturing services that minimize certification efforts and speed time-to-market. The company offers the industry’s broadest set of solutions for a full range of driving system applications, from informational Advanced Driver Assistance Systems (ADAS) to high-performance real-time processors for autonomous cars.

Today, the automobile semiconductor market is approximately $35 billion, and is expected to grow to an estimated $54 billion by 2023. This is driven by a need for new technologies that promise to enhance the driving experience such as navigation, remote roadside assistance and advanced systems that combine data from multiple sensors with high-performance processors that make control decisions.

“As vehicles move rapidly toward greater autonomy, auto manufacturers and parts suppliers are designing new ICs,” said Gregg Bartlett, senior vice president of the CMOS Business Unit at GF. “GF’s diverse automotive platform combines a range of technologies and services that meet the complexity and requirements for applications that enable connected intelligence for the automotive industry.”

Building on 10 years of automotive experience, the company’s AutoPro technology platform includes offerings in silicon germanium (SiGe), FD-SOI (FDX), CMOS and advanced FinFET nodes, combined with a broad range of ASIC design services, packaging and IP.

GF’s CMOS and RF solutions deliver an optimal combination of performance, integration and power efficiency for advanced sensors (radar, lidar, cameras), ADAS and autonomous processing (sensor fusion and AI compute) and body and powertrain control, with embedded eNVM technology for in-vehicle MCUs, as well as connectivity and infotainment systems. The company’s BCD and BCDLite® technologies provide high-voltage capabilities, with a path to supporting 48 volts that enable automotive power solutions for electric powertrain, Hybrid-electric (HEVs) and Internal Combustion Engine (ICE) vehicles.

These automotive solutions are available now, with additional access to quality and service across GF’s manufacturing fabs in the U.S., Europe, and Asia. GF AutoPro solutions support the full range of AEC-Q100 quality grades from Grade 2 to Grade 0.

AutoPro Service Package

In addition to GF’s technology platform, the company has initiated its AutoPro Service Package designed to ensure technology readiness, operational excellence and a robust automotive-ready quality system to continually improve quality and reliability throughout the product life-cycle.

GF’s Service Package builds on the company’s proven automotive quality and operational controls, providing customers access to the latest technologies which are designed to meet strict automotive quality requirements defined in the ISO, International Automotive Task Force (IATF), Automotive Electronics Council (AEC), and VDA (German) standards.

GF is currently working with major OEM customers and suppliers to develop and produce chips of the optimum quality and reliability as required by the various automotive applications.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, and SwissLitho AG, a manufacturer of novel nanolithography tools, today announced a joint solution to enable the production of 3D structures down to the single-nanometer scale. Initially demonstrated within the “Single Nanometer Manufacturing for Beyond CMOS Devices (SNM)” project funded by the Seventh Framework Program of the European Union, the joint solution involves SwissLitho’s novel NanoFrazor thermal scanning probe lithography system to produce master templates with 3D structures for nanoimprint lithography (NIL), and EVG’s HERCULES NIL system with SmartNIL® technology to replicate those structures at high throughput.

Target applications

EVG and SwissLitho will initially target the joint solution for developing diffractive optical elements and other related optical components that support photonics, data communications, augmented/virtual reality (AR/VR) and other applications, with the potential to expand into biotechnology, nanofluidics and other nanotechnology applications.

As part of the joint solution, SwissLitho’s NanoFrazor system will be used to create imprint masters. Compared to conventional approaches, including electron beam (e-beam) and grayscale lithography, the novel technology has the unique ability to print 3D structures with unsurpassed accuracy. EVG’s HERCULES NIL system will then be used to create working templates for production use, cost-effectively and at high throughput, using the company’s proprietary large-area nanoimprint SmartNIL technology.

Dr. Thomas Glinsner, corporate technology director at EV Group, noted, “SwissLitho’s NanoFrazor solution is highly complementary to EVG’s SmartNIL technology. Together we can offer a complete NIL solution for photonics and other applications involving 3D structure patterning, providing significant opportunity for both companies to expand our customer base and market reach. Our NILPhotonics® Competence Center will be the first point of contact for customers interested in this joint solution, where we will be able to offer feasibility studies, demonstrations and pilot-line production.”

A closer look at the technologies

Thermal scanning probe lithography, the technology behind the NanoFrazor, was invented at IBM Research in Zurich and acquired by SwissLitho AG. This maskless, direct-write lithography approach involves spin-coating a unique, thermally sensitive resist onto the sample surface before patterning. A heated ultra-sharp tip is then used to decompose and evaporate the resist locally while simultaneously inspecting the written nanostructures. The resulting arbitrary resist pattern can then be transferred into almost any other material using lift-off, etching, plating, molding or other methodologies.

“We developed our NanoFrazor line to provide a high-performance, affordable alternative and extension to costly e-beam lithography systems,” said Dr. Felix Holzner, SwissLitho CEO. “The technology allows manufacturing of the master with many ‘levels’ in a single step. In particular, 3D structures with single nanometer accuracy can be produced more easily and with greater fidelity compared to traditional e-beam or grayscale lithography methods. We look forward to working with customers to combine our technology with EVG’s successful SmartNIL process at their NILPhotonics Competence Center in Austria.”

The HERCULES NIL combines EVG’s extensive expertise in NIL, resist processing and high-volume manufacturing solutions into a single integrated system that offers throughput of up to 40 wph for 200-mm wafers. The system’s configurable, modular platform accommodates a variety of imprint materials and structure sizes–giving customers greater flexibility in addressing their manufacturing needs. In addition, its ability to fabricate multiple-use soft stamps helps extend the lifetime of master imprint templates.

As microchips become ever smaller and therefore faster, the shrinking size of their copper interconnects leads to increased electrical resistivity at the nanoscale. Finding a solution to this impending technical bottleneck is a major problem for the semiconductor industry.

One promising possibility involves reducing the resistivity size effect by altering the crystalline orientation of interconnect materials. A pair of researchers from Rensselaer Polytechnic Institute conducted electron transport measurements in epitaxial single-crystal layers of tungsten (W) as one such potential interconnect solution. They performed first-principles simulations, finding a definite orientation-dependent effect. The anisotropic resistivity effect they found was most marked between layers with two particular orientations of the lattice structure, namely W(001) and W(110). The work is published this week in the Journal of Applied Physics, from AIP Publishing.

The measured resistivity of epitaxial tungsten layers with (001) and (011) crystal orientation vs thickness d. The tungsten Fermi surface is color coded according to the wave vector dependent Fermi velocity vf. At small thickness, where surface scattering dominates, W(011) is nearly twice as conductive as W(001). Transport simulations indicate that this is due to the anisotropy in the Fermi surface. These results indicate how narrow wires in future computer chips can be made two times more conductive, effectively reducing the required electric power by 50 percent. Credit: Daniel Gall, Rensselaer Polytechnic Institute

The measured resistivity of epitaxial tungsten layers with (001) and (011) crystal orientation vs thickness d. The tungsten Fermi surface is color coded according to the wave vector dependent Fermi velocity vf. At small thickness, where surface scattering dominates, W(011) is nearly twice as conductive as W(001). Transport simulations indicate that this is due to the anisotropy in the Fermi surface. These results indicate how narrow wires in future computer chips can be made two times more conductive, effectively reducing the required electric power by 50 percent. Credit: Daniel Gall, Rensselaer Polytechnic Institute

Author Pengyuan Zheng noted that both the 2013 and 2015 International Technology Roadmap for Semiconductors (ITRS) called for new materials to replace copper as interconnect material to limit resistance increase at reduced scale and minimize both power consumption and signal delay.

In their study, Zheng and co-author Daniel Gall chose tungsten because of its asymmetric Fermi surface — its electron energy structure. This made it a good candidate to demonstrate the anisotropic resistivity effect at the small scales of interest. “The bulk material is completely isotropic, so the resistivity is the same in all directions,” Gall said. “But if we have thin films, then the resistivity varies considerably.”

To test the most promising orientations, the researchers grew epitaxial W(001) and W(110) films on substrates and conducted resistivity measurements of both while immersed in liquid nitrogen at 77 Kelvin (about -196 degrees Celsius) and at room temperature, or 295 Kelvin. “We had roughly a factor of 2 difference in the resistivity between the 001 oriented tungsten and 110 oriented tungsten,” Gall said, but they found considerably smaller resistivity in the W(011) layers.

Although the measured anisotropic resistance effect was in good agreement with what they expected from calculations, the effective mean free path — the average distance electrons can move before scattering against a boundary — in the thin film experiments was much larger than the theoretical value for bulk tungsten.

“An electron travels through a wire on a diagonal, it hits a surface, gets scattered, and then continues traveling until it hits something else, maybe the other side of the wire or a lattice vibration,” Gall said. “But this model looks wrong for small wires.”

The experimenters believe this may be explained by quantum mechanical processes of the electrons that arise at these limited scales. Electrons may be simultaneously touching both sides of the wire or experiencing increased electron-phonon (lattice vibrations) coupling as the layer thickness decreases, phenomena that could affect the search for another metal to replace copper interconnects.

“The envisioned conductivity advantages of rhodium, iridium, and nickel may be smaller than predicted,” said Zheng. Findings like these will prove increasingly important as quantum mechanical scales become more commonplace for the demands of interconnects.

The research team is continuing to explore the anisotropic size effect in other metals with nonspherical Fermi surfaces, such as molybdenum. They found that the orientation of the surface relative to the layer orientation and transport direction is vital, as it determines the actual increase in resistivity at these reduced dimensions.

“The results presented in this paper clearly demonstrate that the correct choice of crystalline orientation has the potential to reduce nanowire resistance,” said Zheng. The importance of the work extends beyond current nanoelectronics to new and developing technologies, including transparent flexible conductors, thermoelectrics and memristors that can potentially store information. “It’s the problem that defines what you can do in the next technology,” Gall said.

Advanced Linear Devices Inc. (ALD), a designer of analog semiconductors, today announced a zero-gate threshold voltage EPAD P-Channel MOSFET Array launching the industry’s first precision sub-threshold circuit. The MOSFET currently has the industry’s lowest operating voltage of 0.2 Volt (V) and current of less than one nano amp (nA). These chips enable the operating regions required for the next generations of development in energy harvesting, Internet of Things (IoT) sensors applications.

The ALD310700A/ALD310700 quad zero threshold MOSFET is intended for the development of small signal precision applications utilizing 0.00V Zero Threshold Voltage. The circuit is ideal for designs requiring very low operating voltages of < +0.5V power supplies. Allowing circuits to operate in the subthreshold region for the first time ever, expands the MOSFET’s operating range into never-before achieved signal levels.

The new MOSFET simplifies circuit biasing schemes and reduces component counts while providing greater precision and sensitivity of sensor applications for IoT engineers. The P-Channel MOSFET can work in conjunction with ALD N-Channel Zero Threshold MOSFET devices in matched sensor applications. The ALD310700A/ALD310700 is the P-channel version of the popular ALD110800A/ALD110800 Precision Zero Threshold N-channel device. Together, these two MOSFET series deliver complementary precision performance. These complementary paired devices enable the design of 0.5% precision current mirrors, current sources, and circuits referenced to power or ground sources including differential amplifier input stages, transmission gates and multiplexers.

Notable device features

  •     Precision offset voltages (VOS): 2mV max.; 10mV max.;
  •     Low minimum operating voltage of less than 0.2V;
  •     Ultra-low minimum operating current of less than 1nA:
  •     Matched and tracked temperature characteristics.

“These devices operate at a point with 100 times lower power than comparable MOSFET arrays. More importantly they enable the next generation of applications at power levels and precision that were impossible until now,” said Robert Chao, President, and Founder, Advanced Linear Devices Inc. “These arrays offer circuit designers working on IoT nodes that require matched sensor activity a method to collect power from supercapacitors or deep cycle batteries.”

As an example, some potential energy harvesting sources, such as thermal electric generators that yield just 0.2V, produce such low levels of energy that they are barely useful for driving power in electronic circuitry. The ALD P-Channel Zero-Threshold (VGS(th)=0.00) EPAD MOSFET arrays can be coupled with a low voltage step-up converter to give low-level power sources a greater range as an energy harvesting source.

This device is available in a quad version and is a member of the EPAD® Matched Pair MOSFET Family. The parts can be ordered directly from ALD or DigiKey and Mouser. Prices start at $2.00 at 100 pieces.

Perovskite solar cells (PSCs) can offer high light-conversion efficiency with low manufacturing costs. But to be commercially viable, perovskite films must also be durable and not degrade under solar light over time. EPFL scientists have now greatly improved the operational stability of PSCs, retaining more than 95% of their initial efficiencies of over 20% under full sunlight illumination at 60oC for more than 1000 hours. The breakthrough, which marks the highest stability for perovskite solar cells, is published in Science.

Challenges of stability

Conventional silicon solar cells have reached a point of maturation, with efficiencies plateauing around 25% and problems of high-cost manufacturing, heavyweight, and rigidity has remained largely unresolved. On the contrary, a relatively new photovoltaic technology based on perovskite solar cells has already achieved more than 22% efficiency.

Given the vast chemical versatility, and the low-cost processability of perovskite materials, the PSCs hold the promise to lead the future of photovoltaic technology by offering cheap, light weight and highly efficient solar cells. But until now, only highly expensive, prototype organic hole-transporting materials (HTMs,selectively transporting positive charges in a solar cell) have been able to achieve power-conversion efficiencies over 20%. And by virtue of their ingredients, these hole-transporting materials adversely affect the long-term operational stability of the PSC.

Therefore, investigating cheap and stable hole transporters that produce equally high efficiencies is in great demand to enable large-scale deployment of perovskite solar cells. Among various inorganic HTMs, cuprous thiocyanate (CuSCN) stands out as a stable, efficient and cheap candidate ($0.5/gr versus $500 /gr for the commonly used spiro-OMeTAD). But previous attempts to use CuSCN as a hole transporter in perovskite solar cells have yielded only moderately stabilized efficiencies and poor device stability, due to problems associated with depositing a high-quality CuSCN layer atop of the perovskite film, as wells as the chemical instability of the CuSCN layer when integrated into a perovskite solar cell.

A stable solution

Now, researchers at Michael Grätzel’s lab at EPFL, in a project led by postdocs Neha Arora and M. Ibrahim Dar, have introduced two new concepts that overcome the major shortcomings of CuSCN-based perovskite solar cells. First, they developed a simple dynamic solution-based method for depositing highly conformal, 60-nm thick CuSCN layers that allows the fabrication of perovskite solar cells with stabilized power-conversion efficiencies exceeding 20%. This is comparable to the efficiencies of the best performing, state-of-the-art spiro-OMeTAD-based perovskite solar cells.

Second, the scientists introduced a thin spacer layer of reduced graphene oxide between the CuSCN and a gold layer. This innovation allowed the perovskite solar cells to achieve excellent operational stability, retaining over 95% of their initial efficiency while operating at a maximum power point for 1000 hours under full-sun illumination at 60 °C. This surpasses even the stability of organic HTM-based perovskite solar cells that are heavily researched and have recently dominated the field.

The researchers also discovered that the instability of the perovskite devices originates from the degradation of CuSCN/gold contact during the solar cell’s operation.

“This is a major breakthrough in perovskite solar-cell research and will pave the way for large-scale commercial deployment of this very promising new photovoltaic technology,” says Michael Grätzel. “It will benefit the numerous scientists in the field that have been intensively searching for a material that could replace the currently used, prohibitively expensive organic hole-transporters,” adds M. Ibrahim Dar.

OEM Group announced today a Post-Dice Clean solution on the proven Cintillio™ Batch Spray platform following plasma and laser dicing methods. Designed specifically to remove residue and particles left behind from these dicing methods, OEM Group’s Cintillio™ SST (Spray Solvent Tool) and Cintillio™ Eco-Clean systems utilize their patented Enhanced Spray Technology (EST) to deliver process improvement through uniform media flow with a nozzle-per-wafer concept ensuring uniform flow and increased rinse efficiency.

After wafers are singulated prior to “pick and place,” the conventional method of cleaning is by water rinsing; however, some singulation methods, particularly plasma and laser, may leave behind residues that water cannot clean. Slag, polymers, and other residues impede device performance and may cause corrosion or affect downstream processes. The Cintillio™ post-dice clean process successfully removes these residues to maintain final device performance. Chris Forgey, CTO for OEM Group says, “We’re pleased to leverage our patented Ozone process specifically for post dice clean applications, delivering value and superior process capability for this specific application.”

Along with the patented Enhanced Spray Technology (EST), both platforms adapt wafer carriers and rotors to hold multiple “diced wafer-on-tape-on-frame” substrates, delivering greater throughput, reduced chemical utilization, space efficient footprint, and excellent overall performance. According to OEM Group Applications Lab Manager, Joshua Levinson, Ph.D., “Any device manufacturer who performs back-end processing of wafers and who employs wafer singulation to create diced substrates will benefit from our solutions. Batch processing also reduces the number of cleaning tools required in a fab and lowers overall cost of ownership, waste generation, and DI water usage.”

With global headquarters in metro Phoenix, Arizona and additional sites throughout the North America, Europe, Japan and Asia, OEM Group, LLC is a semiconductor capital equipment manufacturer and innovator in new and remanufactured 75mm–200mm tools and services.

Solar-Tectic LLC (“ST”) announced today that a patent application for a method of making III-V thin-film tandem solar cells with high performance has been allowed by the US Patent and Trademark Office. The patent, the first ever for a thin III-V layer on crystalline silicon thin-film, covers group III-V elements such as Gallium Arsenide (GaAs), and Indium Gallium Phosphide (InGaP), for the top layer, as well as all inorganic materials, including, silicon, germanium, etc., for the bottom layer.  Group III-V compounds such as Gallium Arsenide (GaAs) are proven photovoltaic materials with high efficiencies but until now have been cost prohibitive because high quality III-V material such as GaAs is expensive. Moreover, the cost of substrates on which to grow III-V materials, such as germanium, which is known to be an ideal material, has kept the technology from market entry. In the breakthrough technology here, ultra-thin films of III-V materials and silicon (or germanium) replace expensive, thicker wafers thereby lowering the costs dramatically. The inventor is Ashok Chaudhari, CEO of Solar-Tectic LLC.

III-V tandem (or multi-junction) cells built on wafers such as silicon are currently being developed in labs, with high efficiencies of around ~30%.  The highest dual-junction cell efficiency (32.8%) came from a tandem cell that stacked a layer of gallium arsenide (GaAs) atop crystalline silicon. Manufacturing costs are expensive especially if a germanium wafer is used as the bottom material in the two layer tandem structure.  In order to compete with low cost silicon wafer technology which is 90% of the global solar panel market, efficiencies must not only be as high as silicon wafers or greater (21.7% and 26.7% are lab records for poly- and monocrystalline silicon wafer cells, respectively), but manufacturing costs must also be lower. This is achievable in the Solar-Tectic LLC patented technology, which uses common industrial manufacturing processes and at low temperature. There is no wafer involved which saves material and energy; instead a thin film allows for precise control of growth parameters. A glass substrate instead of wafer also allows for a bifacial cell design for increased efficiency. A cost effective ~30% efficient III-V tandem solar cell in today’s market would revolutionize the solar energy industry by dramatically reducing the balance of system (BoS) costs, and thereby reduce the need for fossil fuel generated electricity. Silicon wafer technology based on polycrystalline or monocrystalline silicon could become obsolete.

Importantly, the entire patented process for the Solar-Tectic LLC III-V tandem cell can be environmentally friendly since non-toxic metals can be used to deposit the crystalline thin-film materials for both the bottom layer in the tandem configuration as well as in the top, III-V, layer.

The technology also has great promise for LED manufacturing using for example Gallium Nitride.

A “Tandem Series” of solar cell technologies has been launched by Solar-Tectic LLC, which includes a variety of different proven semiconductor photovoltaic materials for the top layer on silicon and/or germanium bottom layers. Recently patents for a tin perovskite and germanium perovskite thin-film tandem solar cell were also granted.

The ITC ruling on September 22 means that it is likely that tariffs will be imposed on crystalline silicon wafers sold in the US. These tariffs will not apply to thin-film solar cell technology, such as ST’s.