Tag Archives: letter-wafer-tech

Today, Mobile Semiconductor announced a new 55nm HD (High Density) memory compiler targeted at the cost sensitive IoT market. The new memory compiler boasts one of the highest density footprints in the industry dramatically reducing the die area and reducing customer product costs for sensors, smart locks, trackers and smart light bulbs.

Cameron Fisher, CEO and Founder of Mobile Semiconductor, said, “We believe that our success in the current 55nm Memory Compilers sets us apart from competitive offerings.  This new high-density product is well positioned to support our customer’s IoT products as they grow in features and capabilities. Our goal is to ensure that our customers can meet and exceed their silicon area goals and therefore reduce their costs.”

Key features include:

  • 15% to 33% smaller than previous 55nm compilers
  • At least 11% smaller than competitive solutions
  • Built on Mobile Semi’s volume designs at 55nm and 65nm
  • Available off the shelf today

Fisher continued, “Mobile Semiconductor remains the leader in providing memory compliers that target the needs of specific industries. We are proud of the fact that repeat customer purchases are close to 100%.  This includes customers moving to the next smaller node or building new products on the same node. Reducing the memory size offered by this new 55nm memory compiler gives our customers a compelling reason to choose Mobile Semiconductor for their cost sensitive IoT products.”

The 55nm HD memory compiler takes advantage of industry standard Bitcells provided by the top foundries.  All Mobile Semiconductor memory compilers are supported by a wide range of industry leading licensing options.

Water molecules distort the electrical resistance of graphene, but a team of European researchers has discovered that when this two-dimensional material is integrated with the metal of a circuit, contact resistance is not impaired by humidity. This finding will help to develop new sensors -the interface between circuits and the real world- with a significant cost reduction.

The many applications of graphene, an atomically-thin sheet of carbon atoms with extraordinary conductivity and mechanical properties, include the manufacture of sensors. These transform environmental parameters into electrical signals that can be processed and measured with a computer.

Due to their two-dimensional structure, graphene-based sensors are extremely sensitive and promise good performance at low manufacturing cost in the next years.

To achieve this, graphene needs to make efficient electrical contacts when integrated with a conventional electronic circuit. Such proper contacts are crucial in any sensor and significantly affect its performance.

But a problem arises: graphene is sensitive to humidity, to the water molecules in the surrounding air that are adsorbed onto its surface. H2O molecules change the electrical resistance of this carbon material, which introduces a false signal into the sensor.

However, Swedish scientists have found that when graphene binds to the metal of electronic circuits, the contact resistance (the part of a material’s total resistance due to imperfect contact at the interface) is not affected by moisture.

“This will make life easier for sensor designers, since they won’t have to worry about humidity influencing the contacts, just the influence on the graphene itself,” explains Arne Quellmalz, a PhD student at KTH Royal Institute of Technology (Sweden) and the main researcher of the research.

The study, published in the journal ACS Applied Materials & Interfaces, has been carried out experimentally using graphene together with gold metallization and silica substrates in transmission line model test structures, as well as computer simulations.

“By combining graphene with conventional electronics, you can take advantage of both the unique properties of graphene and the low cost of conventional integrated circuits.” says Quellmalz, “One way of combining these two technologies is to place the graphene on top of finished electronics, rather than depositing the metal on top the graphene sheet.”

As part of the European CO2-DETECT project, the authors are applying this new approach to create the first prototypes of graphene-based sensors. More specifically, the purpose is to measure carbon dioxide (CO2), the main greenhouse gas, by means of optical detection of mid-infrared light and at lower costs than with other technologies.

In addition to the KTH Royal Institute of Technology, the companies SenseAir AB from Sweden and Amo GmbH from Germany are likewise participants in the CO2-DETECT project, as is the Catalan Institute of Nanotechnology (ICN) from Barcelona.

Organic semiconductors enable the fabrication of large-scale printed and mechanically flexible electronic applications, and have already successfully established themselves on the market for displays in the form of organic light-emitting diodes (OLEDs). In order to break into further market segments, however, improvements in performance are still needed. Doping is the answer. In semiconductor technology, doping refers to the targeted introduction of impurities (also called dopants) into the semiconductor material of an integrated circuit. These dopants function as intentional “disturbances” in the semiconductor that can be used to specifically control the behaviour of the charge carriers and thus the electrical conductivity of the original material. Even the smallest amounts of these can have a very strong influence on electrical conductivity. Molecular doping is an integral part of the majority of commercial organic electronics applications. Until now, however, an insufficient fundamental physical understanding of the transport mechanisms of charges in doped organic semiconductors has prevented a further increase in conductivity to match the best inorganic semiconductors such as silicon.

Researchers from the Dresden Integrated Center for Applied Physics and Photonic Materials (IAPP) and the Center for Advancing Electronics Dresden (cfaed) at TU Dresden, in cooperation with Stanford University and the Institute for Molecular Science in Okazaki, have now identified key parameters that influence electrical conductivity in doped organic conductors. The combination of experimental investigations and simulations has revealed that introducing dopant molecules into organic semiconductors creates complexes of two oppositely charged molecules. The properties of these complexes like the Coulomb attraction and the density of the complexes significantly determine the energy barriers for the transport of charge carriers and thus the level of electrical conductivity. The identification of important molecular parameters constitutes an important foundation for the development of new materials with even higher conductivity.

The results of this study have just been published in the renowned journal Nature Materials. While the experimental work and a part of the simulations were conducted at the IAPP, the Computational Nanoelectronics Group at the cfaed under the leadership of Dr. Frank Ortmann verified the theoretical explanations for the observations by means of simulations at the molecular level. In doing so, a comprehensive foundation for new applications for organic semiconductor technology has been created.

An international team of researchers has reported a breakthrough in fabricating atom-thin processors – a discovery that could have far-reaching impacts on nanoscale chip production and in labs across the globe where scientists are exploring 2D materials for ever-smaller and -faster semiconductors.

The team, headed by New York University Tandon School of Engineering Professor of Chemical and Biomolecular Engineering Elisa Riedo, outlined the research results in the latest issue of Nature Electronics.

They demonstrated that lithography using a probe heated above 100 degrees Celsius outperformed standard methods for fabricating metal electrodes on 2D semiconductors such as molybdenum disulfide (MoS2). Such transitional metals are among the materials that scientists believe may supplant silicon for atomically small chips. The team’s new fabrication method – called thermal scanning probe lithography (t-SPL) – offers a number of advantages over today’s electron beam lithography (EBL).

First, thermal lithography significantly improves the quality of the 2D transistors, offsetting the Schottky barrier, which hampers the flow of electrons at the intersection of metal and the 2D substrate. Also, unlike EBL, the thermal lithography allows chip designers to easily image the 2D semiconductor and then pattern the electrodes where desired. Also, t-SPL fabrication systems promise significant initial savings as well as operational costs: They dramatically reduce power consumption by operating in ambient conditions, eliminating the need to produce high-energy electrons and to generate an ultra-high vacuum. Finally, this thermal fabrication method can be easily scaled up for industrial production by using parallel thermal probes.

Riedo expressed hope that t-SPL will take most fabrication out of scarce clean rooms – where researchers must compete for time with the expensive equipment – and into individual laboratories, where they might rapidly advance materials science and chip design. The precedent of 3D printers is an apt analogy: Someday these t-SPL tools with sub-10 nanometer resolution, running on standard 120-volt power in ambient conditions, could become similarly ubiquitous in research labs like hers.

“Patterning Metal Contacts on Monolayer MoS2 with Vanishing Schottky Barriers Using Thermal Nanolithography” appears in the January 2019 edition of Nature Electronics and can be accessed at http://dx.doi.org/10.1038/s41928-018-0191-0 with a “News & Views” analysis at https://www.nature.com/articles/s41928-018-0197-7.

Riedo’s work on thermal probes dates back more than a decade, first with IBM Research – Zurich and subsequently SwissLitho, founded by former IBM researchers. A process based on a SwissLitho system was developed and used for the current research. She began exploring thermal lithography for metal nanomanufacturing at the City University of New York (CUNY) Graduate Center Advanced Science Research Center (ASRC), working alongside co-first-authors of the paper, Xiaorui Zheng and Annalisa Calò, who are now post-doctoral researchers at NYU Tandon; and Edoardo Albisetti, who worked on the Riedo team with a Marie Curie Fellowship.

LED lights and monitors, and quality solar panels were born of a revolution in semiconductors that efficiently convert energy to light or vice versa. Now, next-generation semiconducting materials are on the horizon, and in a new study, researchers have uncovered eccentric physics behind their potential to transform lighting technology and photovoltaics yet again.

Comparing the quantum properties of these emerging so-called hybrid semiconductors with those of their established predecessors is about like comparing the Bolshoi Ballet to jumping jacks. Twirling troupes of quantum particles undulate through the emerging materials, creating, with ease, highly desirable optoelectronic (light-electronic) properties, according to a team of physical chemists led by researchers at the Georgia Institute of Technology.

Laser light in the visible range is processed for use in the testing of quantum properties in materials in Carlos Silva’s lab at Georgia Tech. Credit: Georgia Tech / Rob Felt

These same properties are impractical to achieve in established semiconductors.

The particles moving through these new materials also engage the material itself in the quantum action, akin to dancers enticing the floor to dance with them. The researchers were able to measure patterns in the material caused by the dancing and relate them to the emerging material’s quantum properties and to energy introduced into the material.

These insights could help engineers work productively with the new class of semiconductors.

Unusually flexible semiconductors

The emerging material’s ability to house diverse, eccentric quantum particle movements, analogous to the dancers, is directly related to its unusual flexibility on a molecular level, analogous to the dancefloor that joins in the dances. By contrast, established semiconductors have rigid, straight-laced molecular structures that leave the dancing to quantum particles.

The class of hybrid semiconductors the researchers examined is called halide organic-inorganic perovskite (HOIP), which will be explained in more detail at bottom along with the “hybrid” semiconductor designation, which combines a crystal lattice — common in semiconductors — with a layer of innovatively flexing material.

Beyond their promise of unique radiance and energy-efficiency, HOIPs are easy to produce and apply.

Paint them on

“One compelling advantage is that HOIPs are made using low temperatures and processed in solution,” said Carlos Silva, a professor in Georgia Tech’s School of Chemistry and Biochemistry. “It takes much less energy to make them, and you can make big batches.” Silva co-led the study alongside Ajay Ram Srimath Kandada from Georgia Tech and the Istituto Italiano di Tecnologia.

It takes high temperatures to make most semiconductors in small quantities, and they are rigid to apply to surfaces, but HOIPs could be painted on to make LEDs, lasers or even window glass that could glow in any color from aquamarine to fuchsia. Lighting with HOIPs may require very little energy, and solar panel makers could boost photovoltaics’ efficiency and slash production costs.

The team led by Georgia Tech included researchers from the Université de Mons in Belgium and the Istituto Italiano di Tecnologia. The results were published on January 14, 2019, in the journal Nature Materials. The work was funded by the U.S. National Science Foundation, EU Horizon 2020, the Natural Sciences and Engineering Research Council of Canada, the Fond Québécois pour la Recherche, and the Belgian Federal Science Policy Office.

Quantum jumping jacks

Semiconductors in optoelectronic devices can either convert light into electricity or electricity into light. The researchers concentrated on processes connected to the latter: light emission.

The trick to getting a material to emit light is, broadly speaking, to apply energy to electrons in the material, so that they take a quantum leap up from their orbits around atoms then emit that energy as light when they hop back down to the orbits they had vacated. Established semiconductors can trap electrons in areas of the material that strictly limit the electrons’ range of motion then apply energy to those areas to make electrons do quantum leaps in unison to emit useful light when they hop back down in unison.

“These are quantum wells, two-dimensional parts of the material that confine these quantum properties to create these particular light emission properties,” Silva said.

Imaginary particle excitement

There is a potentially more attractive way to produce the light, and it is a core strength of the new hybrid semiconductors.

An electron has a negative charge, and an orbit it vacates after having been excited by energy is a positive charge called an electron hole. The electron and the hole can gyrate around each other forming a kind of imaginary particle, or quasiparticle, called an exciton.

“The positive-negative attraction in an exciton is called binding energy, and it’s a very high-energy phenomenon, which makes it great for light emitting,” Silva said.

When the electron and the hole reunite, that releases the binding energy to make light. But usually, excitons are very hard to maintain in a semiconductor.

“The excitonic properties in conventional semiconductors are only stable at extremely cold temperatures,” Silva said. “But in HOIPs the excitonic properties are very stable at room temperature.”

Ornate quasiparticle twirling

Excitons get freed up from their atoms and move around the material. In addition, excitons in an HOIP can whirl around other excitons, forming quasiparticles called biexcitons. And there’s more.

Excitons also spin around atoms in the material lattice. Much the way an electron and an electron hole create an exciton, this twirl of the exciton around an atomic nucleus gives rise to yet another quasiparticle called a polaron. All that action can result in excitons transitioning to polarons back. One can even speak of some excitons taking on a “polaronic” nuance.

Compounding all those dynamics is the fact that HOIPs are full of positively and negatively charged ions. The ornateness of these quantum dances has an overarching effect on the material itself.

Wave patterns resonate

The uncommon participation of atoms of the material in these dances with electrons, excitons, biexcitons and polarons creates repetitive nanoscale indentations in the material that are observable as wave patterns and that shift and flux with the amount of energy added to the material.

“In a ground state, these wave patterns would look a certain way, but with added energy, the excitons do things differently. That changes the wave patterns, and that’s what we measure,” Silva said. “The key observation in the study is that the wave pattern varies with different types of excitons (exciton, biexciton, polaronic/less polaronic).”

The indentations also grip the excitons, slowing their mobility through the material, and all these ornate dynamics may affect the quality of light emission.

Rubber band sandwich

The material, a halide organic-inorganic perovskite, is a sandwich of two inorganic crystal lattice layers with some organic material in between them – making HOIPs an organic-inorganic hybrid material. The quantum action happens in the crystal lattices.

The organic layer in between is like a sheet of rubber bands that makes the crystal lattices into a wobbly but stable dancefloor. Also, HOIPs are put together with many non-covalent bonds, making the material soft.

Individual units of the crystal take a form called perovskite, which is a very even diamond shape, with a metal in the center and halogens such as chlorine or iodine at the points, thus “halide.” For this study, the researchers used a 2D prototype with the formula (PEA)2PbI4.

By Emmy Yi

SEMI Taiwan Testing Committee founded to strengthen the last line of defense to ensure the reliability of advanced semiconductor applications.

Mobile, high-performance computing (HPC), automotive, and IoT – the four future growth drivers of semiconductor industry, plus the additional boost from artificial intelligence (AI) and 5G – will spur exponential demand for multi-function and high-performance chips. Today, a 3D IC semiconductor structure is beginning to integrate multiple chips to extend functionality and performance, making heterogeneous integration an irreversible trend.

As the number of chips integrated in a single package increases, the structural complexity also rises. Not only will this make identifying chip defects harder, but the compatibility and interconnection between components will also introduce uncertainties that can undermine the reliability of the final ICs. Add to these challenges the need for tight cost control and a faster time to market, and it’s clear that semiconductor testing requires disruptive, innovative change. Traditional final-product testing focusing on finished components is now giving way to wafer- and system-level testing.

In addition, the traditional notion of design for testing, an approach that enhances testing controllability and observability, is now coupled with the imperative to test for design, which emphasizes drawing analytics insights from collected test data to help reduce design errors and shorten development cycles. Going forward, the relationship among design, manufacturing, packaging, and testing will no longer be un-directional. Instead, it will be a cycle of continuous improvement.

This paradigm shift in semiconductor testing, however, will also create a need for new industry standards and regulations, elevate visibility and security levels for shared data, require the optimization of testing time and costs, and lead to a shortage of testing professionals. Solving all these issues will require a joint effort by the industry and academia.

“With leading technologies and $4.7 billion in market value, Taiwan still holds the top spot in global semiconductor testing market,” said Terry Tsao, President of SEMI Taiwan. “When testing extends beyond the manufacturing process, it can play a critical role in ensuring quality throughout the entire life cycle from design and manufacturing to system integration while maintaining effective controls on development costs and schedules. Taiwan’s semiconductor industry is in dire need of a common testing platform to enable the cross-disciplinary collaboration necessary for technical breakthroughs.”

The new SEMI Taiwan Testing Committee was formed to meet that need, gathering testing experts and academics from MediaTek, Intel, NXP Semiconductors, TSMC, UMC, ASE Technology, SPIL, KYEC, Teradyne, Advantest, FormFactor, MJC, Synopsys, Cadence, Mentor, and National Tsing Hua University to collaborate in building a complete testing ecosystem. The committee addresses common technical challenges faced by the industry and cultivates next-generation testing professionals to enable Taiwan to maintain its global leadership in semiconductor testing.

The SEMI Taiwan Testing Platform spans communities, expositions, programs, events, networking, business matching, advocacy, and market and technology insights. For more information about the SEMI Taiwan Testing platform, please contact Elaine Lee ([email protected]) or Ana Li ([email protected]).

Emmy Yi is a marketing specialist at SEMI Taiwan.  

This story originally appeared on the SEMI blog.

By Paul Trio

SCIS is a SEMI Technology Community that tackles critical component defectivity for the semiconductor manufacturing industry. The organization develops test methods for measuring defects in these critical components. Originally, this SEMI community was looking at challenges surrounding sub-10nm process nodes, but our constituents – Integrated Device Manufacturers (IDMs), capital equipment OEMs, and (sub)component suppliers – felt that the immediate need was for standards that would apply to process nodes that are already being used for volume semiconductor device manufacturing.

IDMs need ways to tell their supply chain how defects attributable to these critical components factor into the overall process-node defect budgets and wafer-contamination limits. Chipmakers and IDMs needed to start with a baseline: How problematic are existing critical components in the overall fab systems and how do these contaminants contribute to defects and how do they affect overall process yields?

These questions must be answered for every component in the fab’s process line including the drums that hold the fab chemistries, fluid delivery systems, and components used in the wafer-processing chamber. All of these critical fab-line components come into contact with each manufactured wafer, in one way or another, and each is a suspect with respect to contamination, defects, and yield problems. SCIS develops test methods for these fab-line critical components testing that are used to identify the defects caused by these components and for establishing baselines.

SCIS has seven working groups dealing with various critical components. Each is developing various test methods for many critical fab-line components. There are many facets with respect to testing each of these critical components.

Take something as simple as a seal, such as an FFKM (perfluoroelastomer, made from polymers) seal. These seals are ubiquitous in fab lines. In harsher environments, such as inside of a processing chamber, these seals are exposed to high temperatures and harsh chemistries. Different FFKM seals will have different characteristics such as thermal resistivity and chemical resistance, depending on customer specifications, and can also vary from one manufacturer to another. In addition, these characteristics can change depending on environmental conditions – or just the passage of time.

SCIS looks at defect traits from the perspective of each component in the fab line and decides which of the components’ parameters contribute most to process defects. Initially, the SCIS Seals & Valves Group collected a list of seal-related issues or parameters. The working group then cross-checked these parameters against different manufacturing processes used in the fab including ALD (atomic layer deposition) and CVD (chemical vapor deposition). Some processes are harder on seals than others. Then the working group prioritized these various parameters according to their contribution to the overall process defect budget. IDMs provided important input during these steps because they work with these seals on a daily basis. At this point, the SCIS working group had a prioritized list of parameters, vetted by various stakeholders in the semiconductor manufacturing industry. The group then set to develop standardized measurement methods for these critical parameters.

Based on this work, the SCIS Seals & Valves Group has already published two documents. The first is a standard that specifies methods for testing seal-induced impurities such as ashing (analysis of metals content of the ash) and TOC (total organic content).

The second document published by the Seals & Valves Group is a guide that documents BKMs (best known methods) for handling seals – from the moment they’re cured in an oven to packaging, shipping, handling in a fab, and installation – a to reduce contamination problems during use. For example, some seals are sensitive to light. Some polymer seals degrade when they come into contact with IPA (isopropyl alcohol), which is often used for prepping. A degraded seal can emit contamination particles during processing, which will cause yields to fall. (This latter bit of information came directly from a major IDM, which demonstrates the invaluable role that users of these components can play in the development of testing standards.)

The Seals & Valves Group’s current work focuses on developing a standard for measuring seal leak rates. This standard will define test methods for evaluating a seal’s ability to maintain pressure under vacuum. Although there are well-established standard for testing seal CSR (compressive stress relaxation) in the aerospace industry, there’s no such standard for the semiconductor industry. So originally, the Seals & Valves Group tried to tackle that challenge by developing a similar standard for SEMI’s constituents. However, a more practical and immediate parametric challenge turned out to be seal leakage rates.

Installed seals are exposed to high temperatures and harsh chemistries in the semiconductor fabrication process. The Seals & Valves Group decided to develop a test method that would determine how well seals perform over time with respect to leakage rates as the seals are exposed to cyclic harsh conditions. The goal is to simulate the working conditions for these seals, as closely as possible and in a repeatable manner.

There are, of course, some challenges associated with this work. For example, IDMs and equipment OEMs don’t want to reveal their exact process conditions as they are proprietary. So the Seals & Valves Group took a step back and focused on developing a test method based solely on exposure to elevated temperatures.

Development of this thermal test requires the design of a standardized test jig to help ensure consistent, repeatable tests, shown in Figure 1.

Figure 1: Elastomer seal test jig developed by the SCIS Seals & Valves Group.

The seal under test, shown in red in Figure 1, sits at the center of the jig. A second seal, shown in green, is used to seal the actual test environment. Two thermocouples in the jig’s top and bottom monitor of the temperature inside of the jig. There are gas and purge lines for controlling the ambient pressures on either side of the seal under test.

Figure 2 illustrates how the jig is connected to the gas sources.

Figure 2: The Seals Test Jig is connected to helium and nitrogen gas sources and to a calibrated leak (vacuum) line.

The seals leak test is based on a helium leak test. Helium is one of the smallest atoms so it will leak through just about any small gap and, with time, permeate through the material as well. In addition, helium is inert, and testing for helium using a mass spectrometer is a well-established technique for leak testing. Helium leak testing can be one thousand to one million times more sensitive than using mechanical, pressure-decay test techniques. The jig’s nitrogen lines serve to purge the test chambers of helium between leak tests.

Developing just a test jig is not sufficient. The Seals & Valves Group also developed a test sequence for using the jig. There were no existing standard, so the group needed to use its knowledge of the seals’ composition and operating conditions to develop certain test parameters. For example, the group elected to use 200°C as the maximum temperature for the high-temperature portion of the test because FFKM seals start to degrade at 250°C.

At this point, the Seals & Valves Group has gone through several iterations of a proposed test sequence. There was some initial reluctance to provide detailed inputs, but after a few iterations of the proposed method (and an understanding that this would become an industry standard to hold suppliers accountable), inputs have become more forthcoming.

This is an excellent example that demonstrates why it’s so important for SCIS working groups to get chipmakers, IDMs, component vendors, and even feedstock materials vendors to participate in these standardization efforts. Standards are far more useful if they’re based on real-world conditions.

Currently, the SCIS Seals & Valves Group is working towards finalizing the seals-leak test sequence. The jig has been designed in AutoCAD and a prototype will soon be manufactured. Although the test and jig have been developed with significant industry participation, the validity of the test has yet to be determined. The validity will be verified though Alpha testing before the jig design and test method are incorporated into a standard.

However, SEMI is not a test house. It’s a facilitator. The testing will therefore be performed by a neutral third party capable of carrying out the test under fab-like conditions. SEMI’s role is to work with different testing entities such as SUNY Polytechnic Institute in Utica, New York or IMEC in Belgium.

SEMI will solicit bids for this work through its SCIS Executive Advisory Committee, which consists of C-level executives from device makers, semiconductor capital equipment OEMs, and major critical component suppliers. This project has leveraged many of the relationships that SEMI has developed over the years and has broken new ground in standards making for SCIS and for SEMI.

For those looking to learn more about SCIS or engage in ongoing efforts, please contact Paul Trio, senior manager of Strategic Initiatives at SEMI, at [email protected].

SEMI and imec are joining forces to drive innovation and deepen industry alignment on technology roadmaps and international standards while adding technology depth to SEMI’s five vertical application platforms including Smart Transportation, Smart MedTech and Smart Data.

Under a Memorandum of Understanding announced today at ISS 2019, the two organizations have set their sights on bringing together key industry players to advance cutting-edge technologies including Internet of Things (IoT), artificial intelligence (AI) and machine learning that enable new capabilities across healthcare, automotive and semiconductor manufacturing. The partnership also aims to speed the time to better business results for SEMI and imec members and partners.

SEMI brings to the partnership access to the $2 trillion global electronics manufacturing supply chain and imec its global research and development (R&D) and innovation leadership in nanoelectronics and digital technologies.

Under the MOU, the two organizations will co-produce SEMI Think Tanks, extend SEMI’s International Standards platform to non-CMOS technologies, identify and fill gaps in technology roadmaps, and tighten imec’s engagement with SEMI in European workforce development efforts.

UNSW researchers at the Centre of Excellence for Quantum Computation and Communication Technology (CQC2T) have shown for the first time that they can build atomic precision qubits in a 3D device – another major step towards a universal quantum computer.

The team of researchers, led by 2018 Australian of the Year and Director of CQC2T Professor Michelle Simmons, have demonstrated that they can extend their atomic qubit fabrication technique to multiple layers of a silicon crystal – achieving a critical component of the 3D chip architecture that they introduced to the world in 2015. This new research was published today in Nature Nanotechnology.

The group is the first to demonstrate the feasibility of an architecture that uses atomic-scale qubits aligned to control lines – which are essentially very narrow wires – inside a 3D design.

What’s more, the team was able to align the different layers in their 3D device with nanometer precision – and showed they could read out qubit states single shot, i.e. within one single measurement, with very high fidelity.

“This 3D device architecture is a significant advancement for atomic qubits in silicon,” says Professor Simmons. “To be able to constantly correct for errors in quantum calculations – an important milestone in our field – you have to be able to control many qubits in parallel.

“The only way to do this is to use a 3D architecture, so in 2015 we developed and patented a vertical crisscross architecture. However, there were still a series of challenges related to the fabrication of this multi-layered device. With this result we have now shown that engineering our approach in 3D is possible in the way we envisioned it a few years ago.”

In this paper, the team has demonstrated how to build a second control plane or layer on top of the first layer of qubits.

“It’s a highly complicated process, but in very simple terms, we built the first plane, and then optimized a technique to grow the second layer without impacting the structures in first layer,” explains CQC2T researcher and co-author, Dr Joris Keizer.

“In the past, critics would say that that’s not possible because the surface of the second layer gets very rough, and you wouldn’t be able to use our precision technique anymore – however, in this paper, we have shown that we can do it, contrary to expectations.”

The team also demonstrated that they can then align these multiple layers with nanometer precision.

“If you write something on the first silicon layer and then put a silicon layer on top, you still need to identify your location to align components on both layers. We have shown a technique that can achieve alignment within under 5 nanometers, which is quite extraordinary,” Dr Keizer says.

Lastly, the researchers were able to measure the qubit output of the 3D device with what’s called single shot – i.e. with one single, accurate measurement, rather than having to rely on averaging out millions of experiments. “This will further help us scale up faster,” Dr Keizer explains.

Towards commercialisation

Professor Simmons says that this research is a major milestone in the field.

“We are working systematically towards a large-scale architecture that will lead us to the eventual commercialisation of the technology.

“This is an important development in the field of quantum computing, but it’s also quite exciting for SQC,” says Professor Simmons, who is also the founder and a director of SQC.

Since May 2017, Australia’s first quantum computing company, Silicon Quantum Computing Pty Limited (SQC), has been working to create and commercialise a quantum computer based on a suite of intellectual property developed at CQC2T and its own proprietary intellectual property.

“While we are still at least a decade away from a large-scale quantum computer, the work of CQC2T remains at the forefront of innovation in this space. Concrete results such as these reaffirm our strong position internationally,” she concludes.

MagnaChip Semiconductor Corporation (“MagnaChip” or the “Company”) (NYSE: MX), a designer and manufacturer of analog and mixed-signal semiconductor products, announced today it now offers foundry customers its third generation 0.18 micron Bipolar-CMOS-DMOS (BCD) process technology. The technology is highly suitable for PMIC, DC-DC converters, battery charger ICs, protection ICs, motor driver ICs, LED driver ICs and audio amplifiers. The third generation 0.18 micron BCD process technology offers improved specific on-resistance (Rsp) of power LDMOS (Laterally Diffused Metal Oxide Semiconductor) that operates up to 40V with simplified manufacturing steps.

Demand is increasing for high-performance and power-efficient Power ICs processed in BCD technology in order to reduce the number of components in power modules by having multiple functions in one chip. In BCD technologies, the Rsp characteristics of power LDMOS is a key performance parameter because BCD technology with lower Rsp LDMOS helps reduce chip size and power loss of power ICs. MagnaChip has been improving the Rsp of power LDMOS for last ten years. Now, by process and device architecture optimization, MagnaChip’s third generation 0.18 micron BCD process technology reduces the Rsp by approximately 30%, as compared to the previous generation.

BCD technology requirements vary for different applications and IC design schemes. To cover various requirements, MagnaChip adopted the modular process concept that can generate diverse combinations of 1.8V, 5V, and 12~40V transistors. In addition to the current device combinations, MagnaChip intends to release new devices in 2019, such as:  tailored LDMOS devices optimized for a specific range of operational voltages and LDMOS devices with low Vgs (bias between gate to source) that are suitable for power ICs with strict operational voltage limits and other operating at high frequencies.

The third generation BCD process technology offers various optional devices to enhance design integration and flexibility. The optional devices include a high performance bipolar transistor, Zener diode, high resistance poly resistor with no additional photo layer, tantalum nitride resistor with low temperature coefficient, metal-insulator-metal capacitor, metal-oxide-metal capacitor, electrical fuse, and multi-time programmable memory.

To support power ICs for more stringent reliability requirements, as in automotive applications, this third generation BCD process technology was qualified based on the automotive grade qualification specification of AEC-Q100 with Grade1 temperature conditions between -40 to 125 °C.

YJ Kim, Chief Executive Officer of MagnaChip, commented, “Our third generation 0.18 micron BCD process technology with low specific on-resistance is highly suitable for many power IC applications because it helps  reduce  chip size and improve power efficiency. And we will continue to improve the performance of our BCD technology, as it will help our customers increase the competitiveness of their products.”