Tag Archives: letter-wafer-tech

KLA-Tencor Corporation (NASDAQ: KLAC) today introduced five patterning control systems that help chipmakers achieve the strict process tolerances required for multi-patterning technologies and EUV lithography at the sub-7nm logic and leading-edge memory design nodes. Within the IC fab, the ATL™ (Accurate Tunable Laser) overlay metrology system and the SpectraFilm™ F1 film metrology system characterize processes and monitor excursions during fabrication of finFET, DRAM, 3D NAND and other complex devices. The Teron™ 640e reticle inspection product line and the LMS IPRO7 reticle registration metrology system facilitate development and qualification of EUV and advanced optical reticles at mask shops. The 5D Analyzer® X1 advanced data analysis system is the foundation of an open architecture approach that supports fab-customized analyses and real-time process control applications. These five new systems extend KLA-Tencor’s diverse portfolio of metrology, inspection and data analysis systems that enable identification and correction of process variations at the source.

“At the 7nm and 5nm design nodes, it is becoming increasingly difficult for chipmakers to find specific sources of on-product overlay error, critical dimension non-uniformity and hotspots,” said Ahmad Khan executive vice president of the Global Products Group at KLA-Tencor. “Our customers are looking beyond scanner corrections to understand how variations from all reticle and wafer process steps affect patterning. Through open access to fab-wide metrology and inspection data, IC engineers can quickly pinpoint and manage process issues directly where they occur. Our systems, such as the five introduced today, deliver our strongest technology to our customers’ experts, enabling them to drive down the patterning error contributions of every wafer, reticle and process step.”

The five new systems that support patterning control for sub-7nm design node devices include:

  • The ATL overlay metrology system utilizes unique tunable laser technology with 1nm resolution to automatically maintain highly accurate and robust overlay error measurements in the presence of process variations, supporting fast technology ramps and accurate wafer disposition during production.
  • The SpectraFilm F1 film metrology system employs new optical technologies that determine single- and multi-layer film thicknesses and uniformity with high precision to monitor deposition processes in production, and deliver bandgap data that predict device electrical performance earlier than end-of-line test.
  • The Teron 640e reticle inspection product line incorporates optical, detector and algorithm enhancements that detect critical pattern and particle defects at high throughput, advancing the development and qualification of EUV and optical patterned reticles in leading-edge mask shops.
  • The LMS IPRO7 reticle registration metrology system leverages a new operating mode to accurately measure on-device reticle pattern placement error with fast cycle time, enabling comprehensive reticle qualification for e-beam mask writer corrections and reduction of reticle-related contributions to device overlay errors in the IC fab.
  • The 5D Analyzer X1 data analysis system offers an extendible, open architecture that accepts data from a wide range of metrology and process tools to enable advanced analysis, characterization and real-time control of fab-wide process variations.

ATL, SpectraFilm F1, Teron 640e, LMS IPRO7 and 5D Analyzer X1 are part of KLA-Tencor’s unique 5D Patterning Control Solution™, which also includes systems for patterned wafer geometry measurements, in-situ process measurements, critical dimension and device profile metrology, lithography and patterning simulation, and discovery of critical hotspots. Several ATL, SpectraFilm F1 and 5D Analyzer X1 systems are in use at leading-edge IC manufacturers worldwide, supporting a range of patterning control applications. Through upgrades and new tool shipments, the Teron 640e and LMS IPRO7 expand KLA-Tencor’s strong installed base of reticle inspection and metrology systems in advanced mask shops. To maintain the high performance and productivity demanded by IC manufacturing, ATL, SpectraFilm F1, Teron 640e, LMS IPRO7 and 5D Analyzer X1 are backed by KLA-Tencor’s global comprehensive service network. More information on the five new systems can be found on the advanced patterning control web page.

Rudolph Technologies, Inc. (NYSE: RTEC) announces new Truebump™ Technology on the Dragonfly™ Inspection System. Truebump Technology provides fast, accurate and repeatable three-dimensional (3D) metrology for all advanced packaging bumping applications, from copper (Cu) pillar, to microbumps, and even large C4 bumps. With the Dragonfly system, the advanced packaging industry now has premier high-volume 2D inspection and 3D bump metrology on a single platform. The first Dragonfly system with Truebump Technology has shipped to a major IC manufacturer in the United States.

“Truebump Technology combines multiple 3D metrology techniques to provide faster, more accurate, and more repeatable measurements of the 3D features that are critical in advanced packaging technologies,” said Matt Wilson, senior director of inspection product management, Rudolph Technologies. “As 2D and 3D dimensions decrease, the tolerances for manufacturing become tighter, and device stacking continues to drive an increase in functionality. Because these 3D connections are so vital for reliability, the bump height measurements need to be absolutely accurate.”

Wilson continued, “A single wafer may contain 50 million bumps, each with multiple data points, creating massive amounts of data. The Dragonfly system’s integrated connection with Discover®analytics software gives users tools to visualize data, correct coplanarity variations, and improve yields.“

Truebump Technology is three times faster and 25 percent more repeatable than Rudolph’s previous generation tool. The Dragonfly system’s high volume throughput combined with industry leading accuracy and repeatability enable further adoption of stacked devices in advanced packaging applications that fuel today’s drive for thinner and lighter products that deliver more capability in a smaller form factor.

Researchers examining the flow of electricity through semiconductors have uncovered another reason these materials seem to lose their ability to carry a charge as they become more densely “doped.” Their results, which may help engineers design faster semiconductors in the future, are published online in the journal ACS Nano.

Semiconductors are found in just about every piece of modern electronics, from computers to televisions to your cell phone. They fall somewhere between metals, which conduct electricity very well, and insulators like glass that don’t conduct electricity at all. This moderate conduction property is what allows semiconductors to perform as switches and transistors in electronics.

The most common material for semiconductors is silicon, which is mined from the earth and then refined and purified. But pure silicon doesn’t conduct electricity, so the material is purposely and precisely adulterated by the addition of other substances known as dopants. Boron and phosphorus ions are common dopants added to silicon-based semiconductors that allow them to conduct electricity.

But the amount of dopant added to a semiconductor matters – too little dopant and the semiconductor won’t be able to conduct electricity. Too much dopant and the semiconductor becomes more like a non-conductive insulator.

“There’s a sweet spot when it comes to doping where the right amount allows for the efficient conduction of electricity, but after a certain point, adding more dopants slows down the flow,” says Preston Snee, associate professor of chemistry at the University of Illinois at Chicago and corresponding author on the paper.

“For a long time scientists thought that the reason efficient conduction of electricity dropped off with the addition of more dopants was because these dopants caused the flowing electrons to be deflected away, but we found that there’s also another way too many dopants impede the flow of electricity.”

Snee, UIC chemistry student Asra Hassan, and their colleagues wanted to get a closer look at what happens when electricity flows through a semiconductor.

Using the Advanced Photon Source Argonne National Laboratory, they were able to capture X-ray images of what happens at the atomic level inside a semiconductor. They used tiny chips of cadmium sulfide for their semiconductor “base” and doped them with copper ions. Instead of wiring the tiny chips for electricity, they generated a flow of electrons through the semiconductors by shooting them with a powerful blue laser beam. At the same time, they took very high energy X-ray photos of the semiconductors at millionths of a microsecond apart – which showed what was happening at the atomic level in real time as electrons flowed through the doped semiconductors.

They found that when electrons were flowing through, the copper ions transiently formed bonds with the cadmium sulfate semiconductor base, which is detrimental to conduction.

“This has never been seen before,” said Hassan. “Electrons are still bouncing off dopants, which we knew already, but we now know of this other process that contributes to impeding flow of electricity in over-doped semiconductors.”

The bonding of the dopant ions to the semiconductor base material “causes the current to get stuck at the dopants, which we don’t want in our electronics, especially if we want them to be fast and efficient,” she said. “However, now that we know this is happening inside the material, we can design smarter systems that minimize this effect, which we call ‘charge carrier modulation of dopant bonding’.”

To perpetuate the pace of innovation and progress in microelectronics technology over the past half-century, it will take an enormous village rife with innovators. This week, about 100 of those innovators throughout the broader technology ecosystem, including participants from the military, commercial, and academic sectors, gathered at DARPA headquarters at the kickoff meeting for the Agency’s new CHIPS program, known in long form as the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies program.

Many future microelectronics systems could be assembled with a library of plug-and-play chiplets that combine their respective modular functions with unprecedented versatility.

Many future microelectronics systems could be assembled with a library of plug-and-play chiplets that combine their respective modular functions with unprecedented versatility.

“Now we are moving beyond pretty pictures and mere words, and we are rolling up our sleeves to do the hard work it will take to change the way we think about, design, and build our microelectronic systems,” said Dan Green, the CHIPS program manager. The crux of the program is to develop a new technological framework in which different functionalities and blocks of intellectual property—among them data storage, computation, signal processing, and managing the form and flow of data—can be segregated into small chiplets, which then can be mixed, matched, and combined onto an interposer, somewhat like joining the pieces of a jigsaw puzzle. Conceivably an entire conventional circuit board with a variety of different but full-sized chips could be shrunk down onto a much smaller interposer hosting a huddle of yet far smaller chiplets.

Central to the design and intention of the program is the creation of a new community of researchers and technologists that mix-and-match mindsets, skillsets, technological strengths, and business interests. That is why the dozen selected prime contractors for the program include large defense companies (Lockheed Martin, Northrop Grumman, and Boeing), large microelectronics companies (Intel, Micron, and Cadence Design Systems), other semiconductor design players (Synopsys, Intrinsix Corp., and Jariet Technologies), and university teams (University of Michigan, Georgia Institute of Technology, and North Carolina State University). What’s more, many of these prime contractors will be working with additional partners who will extend the village of innovators working on the CHIPS program.

“If the CHIPS program is successful, we will gain access to a wider variety of specialized blocks that we will be able to integrate into our systems more easily and with lower costs,” said Green. “This should be a win for both the commercial and defense sectors.”

Among the specific technologies that could emerge from this newly formed research community are compact replacements for entire circuit boards, ultrawideband radio frequency (RF) systems, which require tight integration of fast data converters with powerful processing functions, and, by combining chiplets that provide different accelerator and processor functions, fast-learning systems for teasing out interesting and actionable data from much larger volumes of mundane data. “By bringing the best design capabilities, reconfigurable circuit fabrics, and accelerators from the commercial domain, we should be able to create defense systems just by adding smaller specialized chiplets,” said Bill Chappell, director of DARPA’s Microsystems Technology Office.

“The CHIPS program is part of DARPA’s much larger effort, the Electronics Resurgence Initiative, in which we are striving to build an electronics community that mixes the best of the commercial and defense capabilities for national defense,” Chappell said. “The ERI, which will involve roughly $200 million annual investments for the next four years, will nurture research in materials, device designs, and circuit and system architecture. The next round of investments are expected this September as part of the broader initiative.”

A new device being developed by Washington State University physicist Yi Gu could one day turn the heat generated by a wide array of electronics into a usable fuel source.

The device is a multicomponent, multilayered composite material called a van der Waals Schottky diode. It converts heat into electricity up to three times more efficiently than silicon — a semiconductor material widely used in the electronics industry. While still in an early stage of development, the new diode could eventually provide an extra source of power for everything from smartphones to automobiles.

“The ability of our diode to convert heat into electricity is very large compared to other bulk materials currently used in electronics,” said Gu, an associate professor in WSU’s Department of Physics and Astronomy. “In the future, one layer could be attached to something hot like a car exhaust or a computer motor and another to a surface at room temperature. The diode would then use the heat differential between the two surfaces to create an electric current that could be stored in a battery and used when needed.”

Gu recently published a paper on the Schottky diode in The Journal of Physical Chemistry Letters.

A new kind of diode

In the world of electronics, Schottky diodes are used to guide electricity in a specific direction, similar to how a valve in a water main directs the flow of liquid going through it. They are made by attaching a conductor metal like aluminum to a semiconductor material like silicon.

Instead of combining a common metal like aluminum or copper with a conventional semiconductor material like silicon, Gu’s diode is made from a multilayer of microscopic, crystalline Indium Selenide. He and a team of graduate students used a simple heating process to modify one layer of the Indium Selenide to act as a metal and another layer to act as a semiconductor. The researchers then used a new kind of confocal microscope developed by Klar Scientific, a start-up company founded in part by WSU physicist Matthew McCluskey, to study their materials’ electronic properties.

Unlike its conventional counterparts, Gu’s diode has no impurities or defects at the interface where the metal and semiconductor materials are joined together. The smooth connection between the metal and semiconductor enables electricity to travel through the multilayered device with almost 100 percent efficiency.

“When you attach a metal to a semiconductor material like silicon to form a Schottky diode, there are always some defects that form at the interface,” said McCluskey, a co-author of the study. “These imperfections trap electrons, impeding the flow of electricity. Gu’s diode is unique in that its surface does not appear to have any of these defects. This lowers resistance to the flow of electricity, making the device much more energy efficient.”

Next steps

Gu and his collaborators are currently investigating new methods to increase the efficiency of their Indium Selenide crystals. They are also exploring ways to synthesize larger quantities of the material so that it can be developed into useful devices.

“While still in the preliminary stages, our work represents a big leap forward in the field of thermoelectrics,” Gu said. “It could play an important role in realizing a more energy-efficient society in the future.”

Over the last two years, Waterloo based Siborg Systems Inc. teamed up with Sensor Creations Inc. from Camarillo, California in development of a practical tool for simulation of the process flow and optical sensor performance.

The companies collaborated in both the semiconductor process and device simulation for optical sensor structures. They have large sizes and require many fabrication steps such as epitaxial growth, implantation, deposition, etching, annealing and oxidation. Due to the large size, use of conventional simulation tools lead to high CPU time. In contrast, MicroTec was able to run a typical process simulation within a few minutes on a regular PC.

Doping profile for 3-junction optical sensor simulated with MicroTec. For 100,000 required CPU time was about 2 minutes on regular PC. (PRNewsfoto/Siborg Systems Inc.)

Doping profile for 3-junction optical sensor simulated with MicroTec. For 100,000 required CPU time was about 2 minutes on regular PC. (PRNewsfoto/Siborg Systems Inc.)

MicroTec provides steady-state two-dimensional semiconductor device simulation that is not sufficient for capacitance extraction. A new method was developed allowing to calculate capacitance of a semiconductor structure by solving equation for the total current conservation. The method is equally applicable to 1D, 2D and 3D structures but limited to low frequencies and low-leakage conditions. The most straightforward method is solving the equation of the total current conservation, mutual capacitances may be calculated simply by the formula C=Idt/dV.

This formula could be improved by using a relation involving resistances as well as capacitances. In order to do that, one more data point is required. Although this expression is more accurate than the first one, it is still not equivalent to the actual compact model of the semiconductor structure because, strictly speaking, it is a set of interconnected transmission lines and therefore any simplification of the equivalent circuit results in a loss of accuracy. The current based method is not very accurate and requires simulation with a properly selected ramp speed. If it is too fast, voltage drop due to Ohm’s law distorts the capacitance, and if it is too slow, displacement current becomes too small and is swamped by the numerical noise. Practically this method has a limited application due to high sensitivity to the ramp time.

In contrast to the current method, the charge method provides charges affiliated with the contacts rather than the currents, thus eliminating the problem of result interpretation using equivalent R-C circuit. To calculate the charges we solve the same equation but instead of calculating currents, we use the response to the excitation applied to a contact as a weight function when integrating the charge in the structure. The charges are easily calculated by a convolution of the “affiliation” function with the carrier density. This method appeared very stable and accurate and was successfully used for capacitance calculation in optical sensors.

The picture below shows the capacitance calculated by the charge based method at various ramp speeds. Note that all 4 curves virtually coincide. The method applicability is questionable when significant minority charge is injected as in the case of forward biased junctions. The proposed method has a wider range of applicability but the extent of its accuracy still needs to be studied.

“We used Two-dimensional Semiconductor Process and Device Simulation Software MicroTec from Siborg intensively for the last couple of years. We found it very useful in our practical optical sensor prototype development. It significantly outperforms other available commercial tools by the speed, ease-of-use and robustness. Last, but not least, the license cost is significantly lower as well,” says Stefan Lauxtermann from Sensor Creations.

MicroTec is a TCAD tool that has been used by major semiconductor manufacturers such as Hitachi, Texas Instruments, Matasushita, etc. As an educational tool, MicroTec and three-dimensional SibLin are simple and easy to learn.

Two-dimensional materials are a sort of a rookie phenom in the scientific community. They are atomically thin and can exhibit radically different electronic and light-based properties than their thicker, more conventional forms, so researchers are flocking to this fledgling field to find ways to tap these exotic traits.

Applications for 2-D materials range from microchip components to superthin and flexible solar panels and display screens, among a growing list of possible uses. But because their fundamental structure is inherently tiny, they can be tricky to manufacture and measure, and to match with other materials. So while 2-D materials R&D is on the rise, there are still many unknowns about how to isolate, enhance, and manipulate their most desirable qualities.

Now, a science team at the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) has precisely measured some previously obscured properties of moly sulfide, a 2-D semiconducting material also known as molybdenum disulfide or MoS2. The team also revealed a powerful tuning mechanism and an interrelationship between its electronic and optical, or light-related, properties.

To best incorporate such monolayer materials into electronic devices, engineers want to know the “band gap,” which is the minimum energy level it takes to jolt electrons away from the atoms they are coupled to, so that they flow freely through the material as electric current flows through a copper wire. Supplying sufficient energy to the electrons by absorbing light, for example, converts the material into an electrically conducting state.

As reported in the Aug. 25 issue of Physical Review Letters, researchers measured the band gap for a monolayer of moly sulfide, which has proved difficult to accurately predict theoretically, and found it to be about 30 percent higher than expected based on previous experiments. They also quantified how the band gap changes with electron density – a phenomenon known as “band gap renormalization.”

“The most critical significance of this work was in finding the band gap,” said Kaiyuan Yao, a graduate student researcher at Berkeley Lab and the University of California, Berkeley, who served as the lead author of the research paper.

“That provides very important guidance to all of the optoelectronic device engineers. They need to know what the band gap is” in orderly to properly connect the 2-D material with other materials and components in a device, Yao said.

Obtaining the direct band gap measurement is challenged by the so-called “exciton effect” in 2-D materials that is produced by a strong pairing between electrons and electron “holes” ¬- vacant positions around an atom where an electron can exist. The strength of this effect can mask measurements of the band gap.

Nicholas Borys, a project scientist at Berkeley Lab’s Molecular Foundry who also participated in the study, said the study also resolves how to tune optical and electronic properties in a 2-D material.

“The real power of our technique, and an important milestone for the physics community, is to discern between these optical and electronic properties,” Borys said.

The team used several tools at the Molecular Foundry, a facility that is open to the scientific community and specializes in the creation and exploration of nanoscale materials.

The Molecular Foundry technique that researchers adapted for use in studying monolayer moly sulfide, known as photoluminescence excitation (PLE) spectroscopy, promises to bring new applications for the material within reach, such as ultrasensitive biosensors and tinier transistors, and also shows promise for similarly pinpointing and manipulating properties in other 2-D materials, researchers said.

The research team measured both the exciton and band gap signals, and then detangled these separate signals. Scientists observed how light was absorbed by electrons in the moly sulfide sample as they adjusted the density of electrons crammed into the sample by changing the electrical voltage on a layer of charged silicon that sat below the moly sulfide monolayer.

Researchers noticed a slight “bump” in their measurements that they realized was a direct measurement of the band gap, and through a slew of other experiments used their discovery to study how the band gap was readily tunable by simply adjusting the density of electrons in the material.

“The large degree of tunability really opens people’s eyes,” said P. James Schuck, who was director of the Imaging and Manipulation of Nanostructures facility at the Molecular Foundry during this study.

“And because we could see both the band gap’s edge and the excitons simultaneously, we could understand each independently and also understand the relationship between them,” said Schuck, now at Columbia University. “It turns out all of these properties are dependent on one another.”

Moly sulfide, Schuck also noted, is “extremely sensitive to its local environment,” which makes it a prime candidate for use in a range of sensors. Because it is highly sensitive to both optical and electronic effects, it could translate incoming light into electronic signals and vice versa.

Schuck said the team hopes to use a suite of techniques at the Molecular Foundry to create other types of monolayer materials and samples of stacked 2-D layers, and to obtain definitive band gap measurements for these, too. “It turns out no one yet knows the band gaps for some of these other materials,” he said.

The team also has expertise in the use of a nanoscale probe to map the electronic behavior across a given sample.

Borys added, “We certainly hope this work seeds further studies on other 2-D semiconductor systems.”

The Molecular Foundry is a DOE Office of Science User Facility that provides free access to state-of-the-art equipment and multidisciplinary expertise in nanoscale science to visiting scientists.

Researchers from the Kavli Energy NanoSciences Institute at UC Berkeley and Berkeley Lab, and from Arizona State University also participated in this study, which was supported by the National Science Foundation.

MRSI Systems, a manufacturer of fully automated, ultra-precision, high speed die bonding and epoxy dispensing systems, is launching a new High Speed Die Bonder, MRSI-HVM3, to support photonics customers’ high volume manufacturing requirements. The MRSI-HVM3 is in full production and MRSI Systems is shipping to customers worldwide.

Scaling imperatives

Today, high volume manufacturing of photonic, sensor, and semiconductor devices demands a die bonding system that can deliver industry leading speed without sacrificing high precision and superior flexibility. The new MRSI-HVM3, a high speed, flexible, 3 micron die bonder, has been built to address this challenge. This new system leverages a well-defined set of MRSI’s core competencies, built up over 30 years, in the areas of system design, software development, machine vision, motion control, industrial automation, and process solutions.

Customer outcomes

As Dr. Yi Qian, Vice President of Product Management, states, “The new MRSI-HVM3 incorporates the latest hardware and software innovations. Equipped with ultrafast-ramp eutectic stations, it deploys multiple levels of parallel processing utilizing dual gantries, dual heads, dual bonding stages, and “on-the-fly” tool changes. Used across all products, MRSI’s platform software makes it easy for users to change process settings on their own for new parts, new processes, and new products. These features provide our customers with best-in-class throughput for capacity expansion; high accuracy for high-density packaging; and unmatched flexibility for multi-chip multi-process production in one machine. Ultimately the system will generate great ROIs for customers. The MRSI-HVM3 high speed die bonder supports many applications including chip-on-carrier (CoC), chip-on-submount (CoS), and chip-on-baseplate or board (CoB).”

“MRSI Systems has been serving optoelectronic and microelectronic customers for the past 33 years and understands their requirement to scale efficiently in today’s fast paced marketplace. MRSI is pleased to meet these needs with the launch of our new high speed die bonder for high volume manufacturing of photonics packaging,” said Mr. Michael Chalsen, President, MRSI Systems.

Private demonstrations at CIOE

MRSI Systems is exhibiting at CIOE with their Chinese Representative CYCAD Century Science and Technology (Booth #1C66) in Shenzhen, September 6-9, 2017. There will be private demonstrations of the MRSI-HVM3 performing CoC eutectic and epoxy bonding. Please reach out to your MRSI contact to ensure you have an opportunity to see the capabilities of this new product.

MRSI Systems is a manufacturer of fully automated, high-precision, high-speed die bonding and epoxy dispensing systems.

Chipmakers want every part of the wafer to produce, or yield, good die. Advances in process technologies over the years have just about made this a reality, even as feature dimensions continue to shrink and devices grow ever more complex. Now, the last frontier is improving yields at the edge of the wafer – the outer 10 mm or so – where chemical, physical, and even thermal discontinuities are simply much harder to control. Complicating matters, current strategies used to manage these edge issues involve tradeoffs between yield and manufacturing costs that result in less than ideal fab economics. At Lam, our technologists have been working on solutions to this challenge, and today, we released the new Corvus™ edge control technology for our Kiyo® conductor etch products to address these very issues and enhance edge yield.

Edge Challenges

Taking a closer look at the wafer’s edge, where up to ~10% of the die may be located, there are several issues at play that can impact yield. In all plasma etch reactors, the abrupt end of the wafer surface creates inherent electrical discontinuities at the edge region, forming voltage gradients that bend the plasma sheath. This, in turn, changes the direction of the plasma’s components (ions and neutrals), which impacts etch results and causes unwanted variability. In the case of 3D NAND devices, for example, this change in the plasma conditions at the wafer’s edge can cause tilted etch profiles or prevent features from being completely etched. In addition to affecting tilt angle, these edge effects can result in non-uniform critical dimensions (CDs) or changes in local overlay metrics.

LAMResearch1

Another challenge is that process drift creates CD uniformity and selectivity problems over time. As a way to manage this, chipmakers often add more chamber wet cleans to restore the equipment to a standard condition. However, this approach significantly reduces productivity because the chamber is not available for processing wafers during this maintenance. In addition, as process margins get tighter, more frequent wet cleans are required, which increases operational costs.

Corvus Solution

Lam’s new Corvus technology provides a novel capability to smooth out extreme edge discontinuities and enhance edge performance. It offers the ability to tune the plasma sheath at the edge to produce a constant, user-defined etch rate and ion angle. For example, etch rate can be tuned to be faster or slower at the edge relative to the rate over the rest of the wafer. With 3D NAND applications, Corvus technology has demonstrated the ability to minimize plasma sheath drift, preventing detrimental feature tilting at the wafer’s edge. Tuning to within 1.5 mm of the edge, the new technology can correct for inherent process variation in the edge region as well as for incoming film variations to optimize die yield. Furthermore, with Corvus, every wafer sees the same edge conditions for optimal yield, eliminating previously seen systematic wafer-to-wafer yield variability.

Corvus technology not only improves across-wafer uniformity, it also greatly reduces wafer-to-wafer and chamber-to-chamber variability and eliminates the historical tradeoffs among yield, operational flexibility, and cost. Customers have reported die yield improvements of 0.5-2% per wafer, which can be a significant advantage – especially when you consider how many thousands of wafers chipmakers process every day. Additionally, Corvus has demonstrated the ability to provide higher and more consistent yield over a longer period. It also greatly enhances productivity and lowers overall fab operating costs for high-volume manufacturing by requiring fewer chamber wet cleans. The new technology is being used for advanced patterning, mask open, and other challenging conductor etch applications where reducing variation in CD, profile, or selectivity and improving productivity helps enable continued scaling.

The new capability provided by Corvus complements Lam’s Hydra® technology, which enables fine tuning of within-wafer uniformity and actively compensates for incoming variation. Together, these advanced process control technologies are reducing variability across the entire wafer surface, improving yield, and enabling the production of next-generation logic and memory devices.

Welch Foundation, the Army Research Office and the National Science Foundation supported the research.

The next generation of feature-filled and energy-efficient electronics will require computer chips just a few atoms thick. For all its positive attributes, trusty silicon can’t take us to these ultrathin extremes.

Now, electrical engineers at Stanford have identified two semiconductors – hafnium diselenide and zirconium diselenide – that share or even exceed some of silicon’s desirable traits, starting with the fact that all three materials can “rust.”

“It’s a bit like rust, but a very desirable rust,” said Eric Pop, an associate professor of electrical engineering, who co-authored with post-doctoral scholar Michal Mleczko a paper that appears in the journal Science Advances.

The new materials can also be shrunk to functional circuits just three atoms thick and they require less energy than silicon circuits. Although still experimental, the researchers said the materials could be a step toward the kinds of thinner, more energy-efficient chips demanded by devices of the future.

Silicon’s Strengths

Silicon has several qualities that have led it to become the bedrock of electronics, Pop explained. One is that it is blessed with a very good “native” insulator, silicon dioxide or, in plain English, silicon rust. Exposing silicon to oxygen during manufacturing gives chip-makers an easy way to isolate their circuitry. Other semiconductors do not “rust” into good insulators when exposed to oxygen, so they must be layered with additional insulators, a step that introduces engineering challenges. Both of the diselenides the Stanford group tested formed this elusive, yet high-quality insulating rust layer when exposed to oxygen.

Not only do both ultrathin semiconductors rust, they do so in a way that is even more desirable than silicon. They form what are called “high-K” insulators, which enable lower power operation than is possible with silicon and its silicon oxide insulator.

As the Stanford researchers started shrinking the diselenides to atomic thinness, they realized that these ultrathin semiconductors share another of silicon’s secret advantages: the energy needed to switch transistors on – a critical step in computing, called the band gap – is in a just-right range. Too low and the circuits leak and become unreliable. Too high and the chip takes too much energy to operate and becomes inefficient. Both materials were in the same optimal range as silicon.

All this and the diselenides can also be fashioned into circuits just three atoms thick, or about two-thirds of a nanometer, something silicon cannot do.

“Engineers have been unable to make silicon transistors thinner than about five nanometers, before the material properties begin to change in undesirable ways,” Pop said.

The combination of thinner circuits and desirable high-K insulation means that these ultrathin semiconductors could be made into transistors 10 times smaller than anything possible with silicon today.

“Silicon won’t go away. But for consumers this could mean much longer battery life and much more complex functionality if these semiconductors can be integrated with silicon,” Pop said.

More to do

There is much work ahead. First, Mleczko and Pop must refine the electrical contacts between transistors on their ultrathin diselenide circuits. “These connections have always proved a challenge for any new semiconductor, and the difficulty becomes greater as we shrink circuits to the atomic scale,” Mleczko said.

They are also working to better control the oxidized insulators to ensure they remain as thin and stable as possible. Last, but not least, only when these things are in order will they begin to integrate with other materials and then to scale up to working wafers, complex circuits and, eventually, complete systems.

“There’s more research to do, but a new path to thinner, smaller circuits – and more energy-efficient electronics – is within reach,” Pop said.

Additional Stanford contributors to this research include: Chaofan Zhang, Hye Ryoung Lee, Hsueh-Hui Kuo, Blanka Magyari-Köpe, Robert G. Moore, Zhi-Xun Shen, Ian R. Fisher, and Professor Yoshio Nishi.

The work was supported by the Air Force Office of Scientific Research (AFOSR), the National Science Foundation, Stanford Initiative for Novel Materials and Processes (INMP), the Department of Energy (DOE) Office of Basic Energy Sciences, Division of Material Sciences, and an NSERC PGS-D fellowship.