Tag Archives: letter-wafer-tech

Brewer Science Inc. today announced from SEMICON West the extension of its partnership with Arkema to develop second-generation directed self-assembly (DSA) materials using high-x (chi) block copolymers. These new materials target advanced-node wafer patterning processes, because they enable even smaller feature sizes than first-generation DSA materials. As such, they provide a cost-effective solution to achieving device nodes down to 5nm and beyond, thereby enabling the continuation of Moore’s law.

“There have been very high expectations that DSA would solve all patterning issues,” said Darron Jurajda, Business Unit Manager, Brewer Science Inc. “Like all worthwhile technologies, there are many challenges to be solved before going into production. Leveraging our earlier DSA collaboration with Arkema offers the best path for implementing the next generation of materials. Together, we look forward to unlocking DSA’s full potential in accordance with industry timelines for manufacturing.”

High-chi block copolymers will further extend DSA’s advantages, achieving feature sizes that meet the requirements for 5nm and beyond. Extending their partnership allows these companies to build on their knowledge base, giving them a head start on developing high-chi materials.

As feature sizes shrink more aggressively with each node, it has become cost prohibitive to create them using existing patterning processes, such as EUV, self-aligned double patterning and self-aligned quad patterning. This presents a challenge for foundries and integrated device manufacturers preparing to ramp to 7nm and 5nm processes. DSA provides an alternative solution to achieving fine feature patterning; can be explored for minimal investment; and is cost efficient in final production. Development of high-chi materials also expands the opportunity for implementing DSA in other applications, including photonics, membrane applications and other areas of microelectronics.

The original collaboration between the two companies combined Brewer Science’s know-how in patterning and process integration with Arkema’s leading-edge expertise in block copolymer development to develop polystyrene-polymethyl methacrylate DSA materials, which are now production-ready to manufacture sub-22nm features.

At its annual Imec Technology Forum USA in San Francisco, imec today presented an electrically functional solution for the 5nm back-end-of-line (BEOL). The solution is a full dual-damascene module in combination with multi-patterning and multi-blocking. Scaling boosters and aggressive design rules pave the way to even smaller dimensions.

As R&D progresses towards the 5nm technology node, the tiny Cu wiring schemes in the chips’ BEOL are becoming more complex and compact. Shrinking the dimensions also reduces the wires cross-sectional area, driving up the resistance-capacitance product (RC) of the interconnect systems and thus increasing signal delay. To overcome the RC delay challenge and enable further improvements in interconnect performance, imec explores new materials, process modules and design solutions for future chip generations.

Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

One viable option is to extend the Cu-based dual-damascene technology – the current workhorse process flow for interconnects – into the next technology nodes. Imec has demonstrated that the 5nm BEOL can be realized with a full dual-damascene module using multi-patterning solutions. With this flow, trenches are created with critical dimensions of 12nm at 16nm.  Metal-cuts (or blocks) perpendicular to the trenches are added in order to create electrically functional lines and then the trenches are filled with metal. Area scaling is further pushed through the introduction of fully self-aligned vias. Moreover, aggressive design rules are explored to better control the variability of the metal tip-to-tips (T2Ts).

Beyond 5nm, imec is exploring alternative metals that can potentially replace Cu as a conductor. Among the candidates identified, low-resistive Ruthenium (Ru) demonstrated great promise. The imec team has realized Ru nanowires in scaled dimensions, with 58nm2 cross-sectional area, exhibiting a low resistivity, robust wafer-level reliability, and oxidation resistance – eliminating the need for a diffusion barrier.

“The emergence of RC delay issues started several technology nodes ago, and has become increasingly more challenging at each node. Through innovations in materials and process schemes, new BEOL architectures and system/technology co-optimization, we can overcome this challenge as far as the 5nm node,” said Zsolt Tokei, imec’s director of the nano-interconnect program. “Imec and its partners have shown attainable options for high density area scaled logic blocks for future nodes, which will drive the supplier community for future needs.”

For the longer term, imec is investigating different options including but not limited to alternative metals, insertion of self-assembled monolayers or alternative signaling techniques such as low-energy spin-wave propagation in magnetic waveguides, exploiting the electron’s spin to transport the signal. For example, the researchers have experimentally shown that spin waves can travel over several micrometers, the distance required by short and medium interconnects in equivalent spintronic circuits.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC.

Twelve years of continuous operation. That amounts to over 18.9 billion rotations. In mid-January 2017, a Busch LLC COBRA BC dry screw vacuum pump passed this milestone in a semiconductor foundry in Germany.

The COBRA BC in question has been in continuous operation at the GlobalFoundries production site in Dresden, Germany, since 2005 and is the longest-operating COBRA BC at the site, which is known as Fab 1. Fab 1 in Dresden was the world’s first fab to manufacture microchips with copper wiring in industrial quantities – a technology that is now the basis for semiconductor production throughout the world.

A total of 203 COBRA BC 0100 dry screw vacuum pumps are installed at the Dresden site, which produces 300mm wafers for the semiconductor industry. 31 of these COBRA BCs have been in continuous operation for over 10 years, and 15 of the COBRA BCs have passed the milestone of 100,000 operating hours (over 11 years of operation). Generally, continuous operation over five or six years is the industry expectation in load-lock applications.

COBRA BC vacuum pumps are predominantly used in the load-lock applications of epitaxy and physical vapor deposition (PVD) processes, as well as in other contamination-free processes for wafer handling and metrics to assure the quality of the lithography process.

The COBRA BC 0100 is a dry screw vacuum pump within the proven COBRA BC series portfolio that is a compact load-lock solution with additional process capabilities for the most demanding solar, flat panel and semiconductor applications. It has excellent powder handling capabilities as a result of its unique screw pump design.

The COBRA BC series is also available in a COBRA BC Premium Efficiency class with a reduced energy footprint that results in lower electrical energy use of up to 40%. The Premium Efficiency class is based on the proven technology platform of the COBRA BC.

Busch Vacuum Pumps and Systems maintains a service team in Dresden, which consists of nine service technicians and one team leader in a 24/7 shift system, ensuring very high system availability of the nearly 900 installed Busch vacuum pumps. Furthermore, the service team maintains the waste gas abatement systems.

GlobalFoundries is among the top semiconductor companies in the world and manufactures at its Dresden fab 40nm to 22nm nodes. The Dresden fab is Europe’s largest fab for the production of microchips.

Two European research institutes today announced their new collaboration to develop innovative, next-generation microelectronics technologies to spur innovation in their countries and strengthen European strategic and economic sovereignty.

Leti, a research institute of CEA Tech in Grenoble, France, and the Berlin-based Fraunhofer Group for Microelectronics, Europe’s largest R&D provider of smart systems, will initially focus on extending CMOS and More-than-Moore technologies to enable next-generation components for applications in the Internet of Things, augmented reality, automotive, health, aeronautics and other sectors, as well as systems to support French and German industries.

The agreement was signed today by Leti CEO Marie Semaria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner during Leti Innovation Days, which are marking Leti’s 50th anniversary.

“The ability to, one, develop key enabling technologies that overcome the formidable technical challenges that our leading technology companies will face, and, two, transfer them quickly to industry, is an essential focus for research institutes and industrials in France and Germany,” Semaria said. “Building on our previous, successful collaborations, Leti and the Fraunhofer Group for Microelectronics will bring our complementary strengths to the task of keeping France and Germany’s microelectronics industries in the forefront – and offer our innovations across Europe.”

“Micro-/nanoelectronics and smart systems are key enabling technologies for the economic success of Europe, especially in France and Germany. Thus, Europe can no longer afford to scatter its research competences. For the benefit of industry, joining forces will become more and more important, not only for industry but also for RTOs,” Lakner explained. “The new cooperation agreement will be the starting point for a strategic research cooperation of the two countries in order to jointly support the upcoming EC initiative, Important Project of Common European Interest (IPCEI), on micro- and nanoelectronics.”

Specific R&D projects that the collaboration will focus on include:

o    Silicon-based technologies for next-generation CMOS processes and products, including design, simulation, unit process and material development as well as production techniques

o    Extended More than Moore technologies for sensing and communication applications

o    Advanced-packaging technologies.

The second phase of the collaboration may be expanded with additional academic partners and other countries, as needed.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced it is demonstrating optimized pre-processing solutions for the implementation of plasma dicing for advanced semiconductor packaging applications. EVG’s latest products and process development services support this emerging semiconductor back-end fabrication process by protecting bumps and other topography with highly uniform resist layer and lithographic patterning of narrow dicing streets. By combining EVG’s systems with third-party dry plasma dicing systems, customers can obtain a complete solution that will enable highly parallel, high-throughput, debris-free die singulation without risking bump reliability or impacting structured surfaces. EVG’s offerings address the critical pre-processing requirements for mid-end-of-line (MEOL) and back-end-of-line (BEOL) processing of MEMS, power devices, RFID components, image sensors, logic and memory.

Thinner and smaller semiconductor chips are required to support the latest generation of mobile and wearable devices as well as to facilitate the Internet of Things (IoT). Plasma dicing offers numerous advantages for die singulation, such as reducing dicing street widths, providing flexible chip layouts as well as eliminating sidewall damage, chipping and wafer breakage. However, plasma dicing also brings new pre-process requirements, including the need for protecting top-side or bottom-side structures prior to singulation, conformal coating of severe topography features, thick resists for deep etching, and lithography to open up the dicing lanes.

EVG’s high-quality, low cost-of-ownership resist processing and lithography systems address all of the pre-processing steps needed for advanced plasma dicing, including resist coating and development, as well as mask alignment lithography:

  • EVG’s proprietary OmniSpray technology enables uniform coating of high-topography surfaces and bumps across the wafer—where traditional spin-coating techniques are limited—with sufficient thickness to fully protect bumps during plasma processing while providing the base for lithographic patterning of dicing streets.
  • EVG’s mask aligners provide optimal patterning quality with spray coating resists, including excellent depth of focus, high uniformity over topography, high throughput, and high resolution in deep cavities and trenches (down to 10µm even for large proximity gaps wider than 100µm), making them ideally suited to expose and open up the dicing lines.
  • The pre-processing line is completed with EVG’s high-throughput development systems.
  • All systems can be provided in semi-automated and fully automated configurations, and are fully compatible with film-frame handling, making them ideally suited for die singulation in advanced packaging.

“The semiconductor industry is increasingly driving device performance through vertical stacking on thinner substrates. This trend is leading to greater demand not only for new wafer dicing technologies, but also for the supporting pre-processing equipment such as our coat, develop and mask alignment systems,” stated Markus Wimplinger, corporate technology development and IP director at EV Group. “We are pleased to offer demonstrations of our complete line of R&D and volume-production pre-processing systems for plasma dicing at our demo labs in Austria, the U.S. and Japan, where customers can witness the yield and cost-of-ownership benefits of this powerful end-to-end wafer dicing solution for their custom advanced packaging needs.”

EVG will also showcase its latest suite of lithography and resist processing solutions for advanced packaging applications at SEMICON West, to be held July 11-13 at the Moscone Convention Center in San Francisco, Calif. Attendees interested in learning more can visit EVG at Booth #7211 in the West Hall.

Synopsys, Inc. (Nasdaq: SNPS) today announced the enablement of the Synopsys Design Platform and DesignWare Embedded Memory IP on GLOBALFOUNDRIES 7nm Leading-Performance (7LP) FinFET process technology. Synopsys and GF collaboration on the new process addressed several new challenges specific to the 7LP process. This process is expected to deliver 40 percent more processing power and twice the area scaling compared to GF’s 14nm FinFET process. Designers of premium mobile processors, cloud servers and networking infrastructure can take advantage of these benefits by confidently deploying the silicon-proven Synopsys Design Platform and Embedded Memory IP.

“GF’s leading-performance 7nm platform is exceeding initial performance targets and is now ready for customer designs,” said Alain Mutricy, senior vice president of product management at GF. “GF and Synopsys have collaborated to provide designers with tools and methodology that fully leverage the power and highest absolute performance of our 7LP technology, and will allow customers to create innovative products across a range of high-performance applications.”

GF and Synopsys worked together to ensure support of the comprehensive suite of Synopsys Design Platform digital implementation solutions for GF 7LP, including Design Compiler Graphical synthesis, IC Compiler II place-and-route, IC Validator physical verification, PrimeTime static timing analysis and StarRC extraction. To enable designers to achieve the full benefit of the GF 7LP process, the Synopsys tools employ advanced techniques including color track generation, pin color alignment checking and legalization, mixing of single-height and double-height physical boundary cells, power grid alignment to track and color-track aware routing.

The two companies are also collaborating on the development of Synopsys DesignWare Memory Compilers to deliver leading performance, power, area and yield for GF’s 7nm process technology. This joint effort consists of optimizing the GF 7LP process design rules and line patterns to achieve the best results. Early versions of the memory compilers will be on the GF 7LP process qualification vehicle.

“Synopsys and GF have always worked closely to address our customers’ needs, including collaborations on FDSOI and 14nm FinFET processes,” said Michael Jackson, corporate vice president of marketing and business development in the Design Group at Synopsys. “With today’s announcement, we are ready to enable designs on the 7LP process. We will continue to collaborate and ensure that our customers can get superior quality of results and faster time to results by using the Synopsys Design Platform and DesignWare Embedded Memory IP.”

Imec, a research and innovation hub in nano-electronics and digital technology, announced today that it has developed 200V and 650V normally-off/enhancement mode (e-mode) on 200mm/8-inch GaN-on-Silicon wafers, achieving a very low dynamic Ron dispersion (below 20 percent) and state-of-the-art performance and reproducibility. Stress tests have also shown a good device reliability. Imec’s technology is ready for prototyping, customized low-volume production as well as for technology transfer.

GaN technology offers faster switching power devices with higher breakdown voltage and lower on-resistance than silicon (Si), making it an ideal material for advanced power electronic components. Imec’s GaN-on-Si device technology is Au-free and compatible with the wafer handling and contamination requirements for processing in a Si fab. A key component of the GaN device structure is the buffer layer, which is required to accommodate the large difference in lattice parameters and thermal expansion coefficient between the AlGaN/GaN materials system and the Si substrate. Imec achieved a breakthrough development in the buffer design (patent pending), allowing to grow buffers qualified for 650 Volt on large diameter 200mm wafers. This, in combination with the choice of the Si substrate thickness and doping increased the GaN substrate yield on 200mm to competitive levels, enabling low-cost production of GaN power devices. Also, the cleaning and dielectric deposition conditions have been optimized, and the field plate design (a common technique for achieving performance  improvement) has been extensively studied. As a result, the devices exhibit dynamic Ron dispersion below 20% up till 650 Volt over the full temperature range from 25°C to 150°C. This means that there is almost no change in the transistor on-state after switching from the off-state, a challenge typical for GaN technology.

“Having pioneered the development of GaN-on-Si power device technology on large diameter substrates (200mm/8-inch), imec now offers companies access to its normally-off/e-mode GaN power device technology through prototyping, low-volume manufacturing as well as via a full technology transfer” stated Stefaan Decoutere, program director for GaN technology at imec. “Next to enhancement mode power device switches, imec also provides lateral Schottky diodes for power switching applications. Based on imec’s proprietary device architecture, the diode combines low turn-on voltage with low leakage current, up to 650V – a combination that is very challenging to achieve.”

si wafer

Silicon based CMOS (Complementary metal-oxide semiconductors) technology has truly shaped our world. It enables most of the electronics that we rely on today including computers, smartphones and digital cameras. However, to continue the path of progress in the electronics industry new technology must be developed and a key feature of this is the ability to integrate CMOS with other semiconductors. Now, Graphene Flagship researchers from ICFO (The Institute of Photonic Sciences in Barcelona) have shown that it is possible to integrate graphene into a CMOS integrated circuit.

This is graphene integrated onto CMOS pixels. Credit: Fabien Vialla

This is graphene integrated onto CMOS pixels. Credit: Fabien Vialla

In their paper published in the journal Nature Photonics they combine this graphene-CMOS device with quantum dots to create an array of photodetectors, producing a high resolution image sensor. When used as a digital camera this device is able to sense UV, visible and infrared light at the same time. This is just one example of how this device might be used, others include in microelectronics, sensor arrays and low-power photonics.

“The development of this monolithic CMOS-based image sensor represents a milestone for low-cost, high-resolution broadband and hyperspectral imaging systems” ICREA Professor at ICFO, Frank Koppens, highlights. He assures that “in general, graphene-CMOS technology will enable a vast amount of applications, that range from safety, security, low cost pocket and smartphone cameras, fire control systems, passive night vision and night surveillance cameras, automotive sensor systems, medical imaging applications, food and pharmaceutical inspection to environmental monitoring, to name a few”.

These results were enabled by the collaboration between Graphene Flagship Partner Graphenea (a Spanish graphene supplier) and ICFO, within the optoelectronics workpackage of the Graphene Flagship.

By creating a hybrid graphene and quantum dot system on a CMOS wafer using a layering and patterning approach, the Flagship team solved a complex problem with a simple solution. First the graphene is deposited, then patterned to define the pixel shape and finally a layer of PbS colloidal quantum dots is added. The photoresponse of this system is based on a photogating effect, which starts as the quantum dot layer absorbs light and transfers it as photo-generated holes or electrons to the graphene, where they circulate due to a bias voltage applied between two pixel contacts. The photo signal is then sensed by the change in conductivity of the graphene, with graphene’s high charge mobility allowing for the high sensitivity of the device.

As Stijn Goossens comments, “No complex material processing or growth processes were required to achieve this graphene-quantum dot CMOS image sensor. It proved easy and cheap to fabricate at room temperature and under ambient conditions, which signifies a considerable decrease in production costs. Even more, because of its properties, it can be easily integrated on flexible substrates as well as CMOS-type integrated circuits.”

The commercial applications of this research and the potential for imaging and sensing technology are now being explored in ICFO’s Launchpad incubator.

Professor Andrea Ferrari, Science and Technology Officer and Chair of the Management Panel of the Graphene Flagship added: “The integration of graphene with CMOS technology is a cornerstone for the future implementation of graphene in consumer electronics. This work is a key first step, clearly demonstrating the feasibility of this approach. The Flagship has put a significant investment in the system level integration of graphene, and this will increase as we move along the technology and innovation roadmap”.

Graphene and related two dimensional (2D) materials have raised massive interest and investment during the last years. However, the amount of 2D-materials-based commercial devices available in the market is still very low.

This image shows resistive random access memory made of graphene electrodes and hexagonal boron nitride dielectric. Credit: American Institute of Physics 2017.

This image shows resistive random access memory made of graphene electrodes and hexagonal boron nitride dielectric. Credit: American Institute of Physics 2017.

The research group led by Dr. Mario Lanza, a Young 1000 Talent Professor born in Barcelona (Spain) and based in Soochow University (China), is leading a global effort to investigate the properties of layered dielectrics. In their recent investigation, published in the journal 2D Materials, Prof. Lanza and co-workers synthesized a resistive random access memory (RRAM) using graphene/hexagonal-boron-nitride/graphene (G/h-BN/G) van der Waals structures. Furthermore, they developed a compact model to accurately describe its functioning. The model is based on the nonlinear Landauer approach for mesoscopic conductors, in this case atomic-sized filaments formed within the 2D materials system. Besides providing excellent overall fitting results (which have been corroborated in log-log, log-linear and linear-linear plots), the model is able to explain the dispersion of the data obtained from cycle-to-cycle in terms of the particular features of the filamentary paths, mainly their confinement potential barrier height.

The development of theoretical models to describe the functioning of electronic devices is one essential step enabling device/systems simulation, which is essential before device mass production. The device selected in this case, the RRAM device, is the most promising technology for future high-density information storage.

The 63rd annual IEEE International Electron Devices Meeting (IEDM), to be held at the Hilton San Francisco Union Square hotel December 2-6, 2017, has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development.

The paper submission deadline this year is Wednesday, August 2, 2017. For the second year in a row the IEDM submission deadline is about 1½ months later than what had been the norm, reducing the time between paper submissions and publication of the cutting-edge research results for which the conference is known. Authors are asked to submit four-page camera-ready abstracts (instead of the traditional three pages), which will be published as-is in the proceedings.

Only a very limited number of late-news papers will be accepted. Authors are asked to submit late-news abstracts announcing only the most recent and noteworthy developments. The late-news submission deadline is September 11, 2017.

“Based on the success of the later paper-submission deadline last year, we have decided to make it an IEDM tradition,” said Dr. Barbara DeSalvo, Chief Scientist at Leti. “This helps ensure a rich and unique technical program.”

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics gather to participate in a technical program consisting of more than 220 presentations, along with special luncheon presentations and a variety of panels, special sessions, Short Courses, IEEE/EDS award presentations and other events highlighting leading work in more areas of the field than any other conference.

This year special emphasis is placed on the following topics:
Advanced memory technologies
More-than-Moore device concepts
Neuromorphic computing/machine learning
Optoelectronics, photonics, displays and imaging systems
Package-device level interactions
Sensors and MEMS devices for biological/medical applications
Spin for memory and logic
Steep subthreshold devices
Technologies for 5nm and beyond

Overall, papers in the following areas of technology are encouraged:

  • Circuit and Device Interaction
  • Characterization, Reliability and Yield
  • Compound Semiconductor and High-Speed Devices
  • Memory Technology
  • Modeling and Simulation
  • Nano Device Technology
  • Optoelectronics, Displays and Imagers
  • Power Devices
  • Process and Manufacturing Technology
  • Sensors, MEMS and BioMEMS