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EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled the IQ Aligner NT–its latest and most advanced automated mask alignment system for high-volume advanced packaging applications. Featuring high-intensity and high-uniformity exposure optics, new wafer handling hardware, full 200-mm and 300-mm wafer coverage that enables global multi-point alignment, and optimized tool software, the new IQ Aligner NT provides a 2X increase in throughput and 2X improvement in alignment accuracy over EVG’s previous-generation IQ Aligner. The system surpasses the most demanding requirements for wafer bump and other back-end lithography applications while providing up to 30 percent lower cost of ownership compared to competing systems.

The IQ Aligner NT from EV Group is the industry's most advanced automated mask alignment system for advanced packaging applications. It provides a 2X increase in throughput and 2X improvement in alignment accuracy over the previous-generation system, as well as up to 30 percent lower cost of ownership compared to competing systems.

The IQ Aligner NT from EV Group is the industry’s most advanced automated mask alignment system for advanced packaging applications. It provides a 2X increase in throughput and 2X improvement in alignment accuracy over the previous-generation system, as well as up to 30 percent lower cost of ownership compared to competing systems.

The IQ Aligner NT is ideally suited for a variety of advanced packaging types, including Wafer-level Chip Scale Packaging (WLCSP), Fan-out Wafer Level Packaging (FOWLP), 3D-IC/Through-silicon Via (TSV), 2.5D Interposers, and Flip Chip.

New lithography capabilities needed

Semiconductor advanced packaging is continually evolving to enable new types of devices with increasing functionality at a lower cost per function. As a result, new developments in lithography are now required to address the unique needs of the advanced packaging market. These needs include:
Extremely tight alignment accuracy
Managing wafer warpage and addressing dimensional mismatch of wafer and mask layout to achieve optimized overlay

Sufficient exposure of the thicker resists and dielectric layers found in back-end processing
Higher resolution to address shrinking bumps and interconnects due to device scaling
At the same time, all of these needs must be met in a highly cost-effective and high-productivity lithography tool platform.

“Leveraging more than three decades of experience in lithography, EVG has pushed the envelope of mask alignment technology to new boundaries with our new IQ Aligner NT,” stated Paul Lindner, executive technology director at EV Group. “This latest addition to our suite of lithography solutions provides unprecedented levels of throughput, accuracy and cost-of-ownership performance, which in turn has opened up a variety of new market opportunities for EVG. We look forward to working closely with customers to meet their critical advanced packaging lithography needs.”

The IQ Aligner NT incorporates a variety of improvements to achieve industry-leading mask alignment performance for advanced packaging lithography:

High-power optics provides a 3X increase in illumination intensity compared to EVG’s previous-generation IQ Aligner, making it ideal for exposing thick resists and other films associated with processing bumps, pillars and other high-topography features:

  • Full clearfield mask movement over 300-mm substrates, which offers the highest process compatibility and flexibility in dark field mask alignment and pattern positioning
  • Dual substrate size concept eliminates the need for any retooling effort, providing a quick and easy on-the-fly bridge tool for two different wafer sizes
  • Fully automated as well as semi-automated/manual wafer loading operation is supported for maximum flexibility
  • Latest EVG CIMFramework system software based on the latest fab software standards and protocols
  • Unsurpassed accuracy and productivity performance

Combining optical and mechanical engineering with optimized tool software, the IQ Aligner NT provides a two-fold increase in throughput (>200 wph for first print, >160 wph for top side alignment) as well as a two-fold improvement in alignment accuracy (250nm 3-sigma). As a result of the tighter alignment specification, customers can also realize improved yields for high-end and high-bandwidth packaging products.

Imec, the research and innovation hub in nano-electronics and digital technologies, today announced that their 200mm gallium nitride-on-silicon (GaN-on-Si) e-mode power devices with a pGaN gate architecture showed no degradation after heavy ion and neutron irradiation. The irradiation tests were performed in collaboration with Thales Alenia Space, a leader in innovative space systems. The results demonstrate that imec’s 200mm GaN-on-Si platform delivers state-of-the-art GaN-based power devices for earth as well as for space applications.

GaN-on-silicon transistors operate at higher voltages, frequencies and temperatures than their silicon counterparts. This makes them the ideal candidates for power conversion devices as they show less power losses in electricity conversion. First-generation GaN-based power devices are used today and will play a key role in the power conversion of future electronic devices such as battery chargers, smartphones, computers, servers, automotive, lighting systems and photovoltaics.

Imec has been  developing the next-generation of GaN-based power devices with improved performance and reliability. Imec’s latest 200mm GaN-on-Si platform shows good  wafer-to-wafer reproducibility and low dynamic Rdson. The platform is currently available for dedicated development or technology transfer to imec’s current and future partners.

imec Ron

Imec’s latest generation of  200mm GaN-on-Si e-mode pGaN devices were irradiated with heavy ions (Xenon) and neutrons. Pre and post irradiation tests revealed that there was no permanent degradation of transistor characteristics: no shifts in threshold voltage nor gate rupture. The excellent radiation hardness of imec’s devices is important, as it enables applications in space, where fluxes of heavy ions and neutrons can damage electronic circuits in satellites and space stations.

Thales Alenia Space Belgium has surveyed, since many years, the evolution in the field of wide band gap devices. These family of components is promising for a significant increase in performances. But, robustness to space radiation is mandatory for electronic devices in our equipment’s. The result obtained with Imec’s GaN-on-Si devices is an important step in the way to space based power conversion applications.

“These results are important to start using this promising technology for space applications. Also, it demonstrates that our 200mm GaN-on-Si platform has reached a high level of technology readiness and can be adopted by industry,” stated Rudi Cartuyvels, Executive Vice President at imec. “At imec, we use 200mm silicon substrates for GaN epitaxy and this technology can be used on 200mm CMOS-compatible infrastructure. Thanks to innovations in transistor architecture and substrate technology, we’ve succeeded in making GaN devices on larger wafer diameters than used today, which brings lower cost perspectives for the second generation of GaN-on-Si power devices. Imec is also looking beyond today’s technology, exploring novel substrates, higher level of integrations and novel devices.”

These results were achieved in the framework of the European Space Agency (ESA) project “ESA AO/1-7688/13/NL/RA”, GaN devices for space based DC-DC power conversion applications.

Andrew Barnes ESA Technical Officer overseeing the project stated: “GaN is a critical technology for future space missions with a wide range of potential applications, including smaller size, higher efficiency DC-DC power conversion subsystems. These results, obtained from the first phase of an ESA GSTP project, are important and show that the p-GaN devices developed by imec offer excellent radiation robustness for operation in space. In the second phase of the project it is planned to industrialize this technology in readiness for a future space qualification program”. The European Space Agency (ESA) is Europe’s gateway to space. Its mission is to shape the development of Europe’s space capability and ensure that investment in space continues to deliver benefits to the citizens of Europe and the world.

Cadence Design Systems, Inc. (NASDAQ:  CDNS) today announced the Cadence Litho Physical Analyzer (LPA) Production Lithography Unified Solution (PLUS) developed in partnership with ASML, which seamlessly provides foundry-enabled lithography simulation capabilities during chip design implementation and signoff. Cadence LPA PLUS enables engineers to detect lithography hotspots during design implementation and physical signoff and automatically fix them in Cadence design platforms. As a result, designers can improve design reliability and yield, while also accelerating time to market and yield ramp-up of their products.

Cadence LPA PLUS enables engineers to predict and optimize the manufacturability and printability of their designs using a production simulation model and optical proximity correction (OPC) technique from ASML prior to tapeout. This ensures the efficient delivery of high-quality designs that function as intended. In addition, this technology is integrated with the Cadence Virtuoso® environment and Innovus™ Implementation System, providing a simple way to detect and fix printability hotspots during implementation, thereby further optimizing design manufacturability and yield.

Cadence and ASML developed the LPA PLUS to address the most complex design for manufacturing (DFM) requirements for advanced nodes that industry ecosystem partners demand. Furthermore, the Cadence LPA PLUS solution, validated by imec for advanced node designs, is readily accessible from the designer’s desktop, giving the designer greater control over manufacturability optimization while reducing foundry iterations.

“At advanced nodes, bridging the gap between design and manufacturing is imperative,” said Christophe Fouquet, executive vice president of applications at ASML. “We recognized that the Cadence design solution provided the optimal platform to bring manufacturing awareness to designers. The powerful combination of ASML Brion computational lithography technology and Cadence LPA brings together best-in-class technologies that fill that gap.”

“With Cadence LPA PLUS, engineering teams can simulate the manufacturability of their design at any time during implementation and signoff so they can accelerate time to market,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “By working closely with ASML and imec, we’re enabling customers to take control of their design intent, reliability and yield.”

At the SPIE Advanced Lithography conference in San Jose, Calif. (USA), imec and its partners will present a patterning solution for a 42nm-pitch M1 layer and a 32nm-pitch M2 layer in logic design compatible with the foundry N5 requirements. The approach includes two scenarios for EUVL insertion that, when combined with an array of scaling boosters, serve as a basis of the industry requirements for power, performance, area and cost. Including proposals for design rules, masks, photoresists, etching, and metrology and an extensive process variation assessment, imec’s R&D has established the first comprehensive solution for EUVL enablement in high-volume manufacturing.

As an alternative to the cost-prohibitive and complex self-aligned quadruple patterning (SAQP) + immersion triple block patterning for the 32nm metal layer (M2), imec has developed two approaches that include exposure on ASML’s NXE:3300B EUV-scanner. The primary solution involves completing the SAQP with a single EUV blocking step, which offers a 20 percent wafer cost reduction over the full immersion approach. The alternate approach relies on EUV for a single patterning step, replacing both the SAQP and triple blocking steps.  This adds an additional cost reduction, but has more implementation challenges than the SAQP+EUV block solution. As pitch-only scaling becomes a burden in technology node transition, imec’s solutions have been complemented by co-optimizing the technology and the design libraries resulting in significantly lower area while lessening the burden in pitch-only scaling. This allows a full node definition with fixed wafer cost increase with more area reduction.

As part of the solution, imec and ASML created a 2D OPC full-chip model, which was then used to design and fabricate the EUVL block mask. Also for the etch process, solutions have been found that meet the requirements.  As for the mask pellicles, imec reports on work for 250W exposure membranes, investigating a promising group of materials based on carbon nanotubes (CNT).

Lastly, the SAQP and block structures have been characterized in detailed morphological studies, assessing pattern fidelity and variability. At a 32nm pitch, even minor process variations in EUVL may have significant impact on device performance. Such variations are due to overlay and critical dimension uniformity issues, in addition to EUVL-specific effects such as shadowing, M3D, flare and stochastic effects. Imec simulated and measured these effect on the wafers, demonstrating the suitability of the proposed solutions and identifying approaches to fine-tune processing computationally, e.g. further refining the OPC.

Gigaphoton Inc., a manufacturer of light sources used in lithography, has announced that in the field of Laser-Produced Plasma (LPP) light sources for EUV scanners, which the company is currently engaged in developing, it has successfully demonstrated that debris mitigation using magnetic fields, the company’s new proprietary technology, is effective in extending the lifetime of collector mirrors in pilot light sources designed to operate in semiconductor mass production lines, which have been a result of Japan’s National Institute for New Energy and Industrial Technology Development (NEDO) grant program.

EUV light source equipment concentrates light generated by high-intensity EUV plasma, and requires collector mirrors to then transmit this light to lithography equipment. However, when operating at high output rates the mirrors soon become contaminated with the tin being targeted by the mirror’s light, which leads to exceedingly short lifespans of collector mirrors. This challenge has been a major barrier for their practical application.

In its experiments, Gigaphoton has verified that its patented technology, which uses magnetic fields to mitigate debris, extends the lifetime of collector mirrors (with a reflectance decrease of less than 0.5% per billion pulses). These experiments involved the magnetic-field debris mitigation technology installed onto an EUV lithography pilot light source equivalent to one typically used in a mass production plant, and then operated at 100 W. The data suggests that the lifespan of collector mirrors, which was previously only a few weeks under continuous operation, can be successfully extended.

Hakaru Mizoguchi, Vice President & CTO of Gigaphoton says, “This demonstration of the effectiveness of our magnetic-field debris mitigation technology for pilot light sources designed to operate in state-of-the-art semiconductor mass production lines, shows how incredibly close we are to overcoming major technological bottlenecks and introducing the technology into the EUV light source market. We remain committed in our efforts to support overall development in the semiconductor industry and contribute to the realization of an IoT based society through the development of EUV light sources.”

1): a light source designed by Gigaphoton for use in mass production plants that use EUV lithography. Also called a “high output demonstration unit”

More information on this issue will be announced at the upcoming international symposium on advanced lithography, “SPIE Advanced Lithography 2017,” to be held from February 26 to March 2 in San Jose, California.

KLA-Tencor Corporation (NASDAQ: KLAC) today introduced four innovative metrology systems that enable development and high-volume manufacturing of sub-10nm integrated circuit (IC) devices: the Archer 600 overlay metrology system, the WaferSight PWG2 patterned wafer geometry measurement system, the SpectraShape 10K optical critical dimension (CD) metrology system and the SensArray HighTemp 4mm in-situ temperature measurement system. These four new systems expand the capability of KLA-Tencor’s unique 5D Patterning Control Solution to support advanced patterning techniques, such as self-aligned quadruple patterning (SAQP) and extreme ultraviolet (EUV) lithography.

“Leading-edge device manufacturers are facing extremely tight patterning specifications,” said Oreste Donzella, chief marketing officer at KLA-Tencor. “To understand patterning errors, chipmakers need to quantify process variations, isolate their sources and fix the underlying issues. The new metrology systems announced today generate critical data that engineers can use to specify detailed scanner corrections in the lithography module and process improvements in etch, films and other modules. Our new overlay, patterned wafer geometry, optical critical dimension and in-situ temperature measurement systems serve key roles in driving 193i multi-patterning performance and baselining early EUV lithography results.”

The Archer 600 extends imaging-based overlay metrology technology with new optics and novel measurement targets, helping chipmakers achieve sub-3nm overlay error for advanced logic and memory devices. Innovative ProAIM™ targets deliver better resilience to process variations and improved correlation between target and device overlay errors, producing more accurate overlay measurements. The Archer 600’s new optical technologies, including a higher brightness light source and polarization module, enable tighter overlay error feedback and control across a range of process layers—from thin resists to opaque hard mask materials. With enhanced productivity, the Archer 600 supports increased sampling of overlay error for improved scanner corrections or identification of inline excursions. Multiple Archer 600 systems are already measuring the most advanced devices at foundry, logic and memory manufacturers worldwide.

The WaferSight PWG2 produces comprehensive wafer stress and shape uniformity data, enabling process tool monitoring and matching for film deposition, anneal, etch and other process modules. With significant productivity improvements, the WaferSight PWG2 promotes increased wafer sampling in production, helping chipmakers identify and fix process-induced wafer stress variations that can cause patterning and yield issues. The WaferSight PWG2’s wafer shape data can also be fed forward to the lithography scanner to address overlay errors due to wafer stress, a particular concern for 3D NAND devices, which utilize thick film stacks that can distort wafers. With industry-unique vertical wafer hold, the WaferSight PWG2 measures front and back wafer surfaces simultaneously, generating wafer flatness and topography metrics that can improve prediction and control of scanner focus. Several WaferSight PWG2 systems are installed at advanced IC manufacturers, where they are used in development for lithography control, and in high volume manufacturing to optimize and monitor a wide range of fab processes.

The SpectraShape 10K optical-based metrology system measures the CDs and three-dimensional shapes of complex IC device structures following etch, chemical mechanical planarization (CMP) and other process steps. To comprehensively characterize device structures, the SpectraShape 10K employs a diverse array of optical technologies, including new polarization capability and multiple incidence angles for the ellipsometer, and a new high brightness light source with TruNI™ illumination for the reflectometer. These technologies enable accurate measurement of the numerous critical parameters associated with FinFET and 3D NAND devices—such as CD, height, SiGe shape and channel hole bow profile. With higher throughput than its predecessor, the SpectraShape 10K facilitates the increased sampling required for tighter process control and the growth in number of process layers due to multi-patterning techniques. The SpectraShape 10K has been strongly adopted by foundries for FinFET and multi-patterning integration, with additional systems supporting advanced 3D NAND fabrication at all the leading memory manufacturers.

Through in-situ measurements, the SensArray HighTemp 4mm wireless wafer provides temporal and spatial temperature information for advanced films processes. With a thinner wafer profile than its predecessor, the SensArray HighTemp 4mm is compatible with a wider range of process tool types, including track, strip and physical vapor deposition (PVD) systems. With a temperature range of 20 – 400°C, the SensArray HighTemp 4mm enables process characterization and tool qualification by mapping thermal variations that can affect process windows and patterning performance. Multiple SensArray HighTemp 4mm wafers are in use at microprocessor, DRAM and 3D NAND manufacturers for tuning and routine process monitoring of films applications.

The Archer 600, WaferSight PWG2, SpectraShape 10K and SensArray HighTemp 4mm are integrated with KLA-Tencor’s 5D Analyzer® advanced data analysis system, which supports real-time process control and provides tools for engineering monitoring and analysis. To maintain the high performance and productivity demanded by IC manufacturing, the Archer 600, WaferSight PWG2, SpectraShape 10K and SensArray HighTemp 4mm are backed by KLA-Tencor’s global comprehensive service network. More information on the four new systems can be found on the 5D Patterning Control Solution web page.

ClassOne Technology (www.classone.com), manufacturer of cost-efficient wet processing equipment for ≤200mm substrates, announced a new company-wide initiative to reduce costs of operation (CoO) in copper plating processes.

“From the beginning, our mission has been to bring more advanced and lower priced plating capabilities to all the emerging markets who work with smaller wafers,” said ClassOne Technology President, Kevin Witt. “Our Solstice systems are already the industry’s most affordable tools for ≤200mm plating. Now we want to enable economies on the cost of ownership side, as well — perhaps reducing those expenses by as much as 25 to 30%. And that’s our goal in this initiative.”

The company explained that it sees potential for shrinking Cu plating CoO by reducing chemical consumption, extending the life of consumables and equipment parts, increasing and optimizing throughput, and enhancing chamber performance, among other areas. Company representatives stated that they are working toward innovative ways to increase efficiencies, minimize waste, streamline operation and optimize performance in each of the copper plating processes.

“Copper plating is an extremely hot area of interest right now in a great many emerging markets,” said Witt. “That’s why ClassOne focuses serious attention on it. We want to continue to be the go-to guys for absolutely everything having to do with copper plating on smaller wafers.”

“And that’s why you’ll be seeing more new copper-related announcements coming from ClassOne in the coming weeks and months,” he added.

ClassOne Technology offers a selection of new wet processing tools specifically designed for users of 75mm to 200mm wafers. These include three different models of Solstice electroplating systems for production and development as well as the Trident families of Spin-Rinse-Dryers and Spray Solvent Tools. All are priced at less than half of what similarly configured systems from the larger manufacturers would cost — which is why the ClassOne lines are often described as delivering “Advanced Wet Processing for the Rest of Us.”

University of Pennsylvania researchers are now among the first to produce a single, three-atom-thick layer of a unique two-dimensional material called tungsten ditelluride. Their findings have been published in 2-D Materials.

Unlike other two-dimensional materials, scientists believe tungsten ditelluride has what are called topological electronic states. This means that it can have many different properties not just one.

When one thinks about two-dimensional materials, graphene is probably the first that comes to mind.

The tightly packed, atomically thin sheet of carbon first produced in 2004 has inspired countless avenues in research that could revolutionize everything from technology to drinking water.

One of the most important properties of graphene is that it’s what’s called a zero bandgap semiconductor in that it can behave as both a metal and a semiconductor.

But there are tons of other properties that 2-D materials can have. Some can insulate, others can emit light and still others can be spintronic, meaning they have magnetic properties.

“Graphene is just graphene,” said A.T. Charlie Johnson, a physics professor in Penn’s School of Arts & Sciences. “It just does what graphene does. If you want to have functioning systems that are based on 2-D materials, then you want 2-D materials that have all of the different physical properties that we know about.”

The ability of 2-D materials to have topological electronic states is a phenomenon that was pioneered by Charles Kane, the Christopher H. Browne Distinguished Professor of Physics at Penn.

In this new research, Johnson, physics professor James Kikkawa and graduate students Carl Naylor and William Parkin were able to produce and measure the properties of a single layer of tungsten ditelluride.

“Because tungsten ditelluride is three atoms thick, the atoms can be arranged in different ways,” Johnson said. “These three atoms can take on slightly different configurations with respect to each other. One configuration is predicted to give these topological properties.”

Marija Drndi?, the Fay R. and Eugene L. Langberg Professor of Physics; Andrew Rappe, the Blanchard Professor of Chemistry and a professor of materials science and engineering in the School of Engineering and Applied Science, and Robert Carpick, the John Henry Towne Professor and chair of the Department of Mechanical Engineering and Applied Mechanics, also contributed to the research.

“It’s very much a Penn product,” Johnson said. “We’re collaborating with multiple other faculty members who investigate the material in their own ways, and we brought it all together to put a paper out there. Everybody comes along for the ride.”

The researchers were able to grow this material using a process called chemical vapor deposition. Using a hot-tube furnace, they heated a chip containing tungsten to the right temperature and then introduced a vapor containing tellurium.

“Through good fortune and finding exactly the right conditions, these elements will chemically react and combine to form a monolayer, or three-atom-thick regions of this material,” Johnson said.

Although this material degrades extremely rapidly in air, Naylor, the paper’s first author, figured out ways to protect the material so that it could be studied before it was destroyed.

One thing the researchers found is that the material grows in little rectangular crystallites, rather than the triangles that other materials grow in.

“This reflects the rectangular symmetry in the material,” Johnson said. “They have a different structure so they tend to grow in different shapes.”

Although the research is still in its beginning stages and the researchers haven’t yet been able to produce a continuous film, they hope to conduct experiments to show that it has the topological electronic properties that are predicted.

One property of these topological systems is that any current traveling through the material would only be carried on the edges, and no current would travel through the center of the material. If researchers were able to produce single-layer-thick materials with this property, they may be able to route an electrical signal to go off into different locations.

The ability of this material to have multiple properties could also have implications in quantum computing, which taps into the power of atoms and subatomic phenomena to perform calculations significantly faster than current computers. These 2-D materials might allow for an intrinsically error-tolerant form of quantum computing called topologically protected quantum computing, which requires both semiconducting and superconducting materials.

“With these 2-D materials, you want to realize as many physical properties as possible,” Johnson said. “Topological electronic states are interesting and they’re new and so a lot of people have been trying to realize them in a 2-D material. We created the material where these are predicted to occur, so in that sense we’ve moved towards this very big goal in the field.”

A new study, affiliated with Ulsan National Institute of Science and Technology (UNIST), South Korea, has introduced a novel method for fabrication of world’s thinnest oxide semiconductor that is just one atom thick. This may open up new possibilities for thin, transparent, and flexible electronic devices, such as ultra-small sensors.

This new ultra-thin oxide semiconductors was created by a team of scientists, led by Professor Zonghoon Lee of Materials Science and Engineering at UNIST. In the study, Professor Lee has succeeded in demonstrating the formation of two-dimensional zinc oxide (ZnO) semiconductor with one atom thickness.

The above graphic displays the growth of ZnO on graphene layer, consists of interconnected hexagons of carbon atoms. Zinc atom shown as red spheres, oxygen atom as green spheres. Credit: UNIST

The above graphic displays the growth of ZnO on graphene layer, consists of interconnected hexagons of carbon atoms. Zinc atom shown as red spheres, oxygen atom as green spheres. Credit: UNIST

This material is formed by directly growing a single-atom-thick ZnO layer on graphene, using atomic layer deposition. It is also the thinnest heteroepitaxial layer of semiconducting oxide on monolayer graphene.

“Flexible, high-performance devices are indispensable for conventional wearable electronics, which have been attracting attention recently,” says Professor Lee. “With this new material, we can achieve truly high-performance flexible devices.”

Semiconductor technology continually moves toward smaller feature sizes and greater operational efficiency and the existing silicon semiconductors seem to also follow this trend. However, as the fabrication process becomes finer, the performance becomes much critical issue and there has been much research on next-generation semiconductors, which can replace silicon.

Graphene has superior conductivity properties, but it cannot be directly used as an alternative to silicon in semiconductor electronics because it has no band gap. A bandgap gives a material the ability to start and stop the flow of electrons that carry electricity. In graphene, however, electrons move randomly at a constant speed no matter their energy and they cannot be stopped.

To solve this, the research team decided to demonstrate atom-by-atom growth of zinc and oxygen at the preferential zigzag edge of a ZnO monolayer on graphene through in situ observation. Then, they experimentally determine that the thinnest ZnO monolayer has a wide band gap (up to 4.0 eV), due to quantum confinement and graphene-like ‘hyper-honeycomb’ structure, and high optical transparency.

The currently-existing oxide semiconductors have a relatively large bandgap in the range of 2.9-3.5 eV. The greater the band gap energy, the lower the leakage current and excess noise.

“This is the first time to actually observe the in situ formation of hexagonal structure of ZnO,” says Hyo-Ki Hong of Materials Science and Engineering, first author of the paper. “Through this process, we could understand the process and principle of 2D ZnO semiconductor productiom.”

“The heteroepitaxial stack of the thinnest 2D oxide semiconductors on graphene has potential for future optoelectronic device applications associated with high optical transparency and flexibility,” says Professor Lee. “This study can lead to a new class of 2D heterostructures including semiconducting oxides formed by highly controlled epitaxial growth through a deposition route.”

NXP Semiconductors N.V. (NASDAQ:NXPI) today announced that Marcel Pelgrom is the recipient of the 2017 Gustav Robert Kirchhoff Award from the IEEE. The long-time NXP researcher and inventor was recognized for “seminal contributions to systematic analysis of random offsets in semiconductor devices and their impact on circuits,” where his theories on random component variation led to the Pelgrom Law, widely acknowledged as a critical enabler of design efficiency in analog chip design.

The Kirchhoff Award, given at the 2017 edition of the International Solid-State Circuits Conference (ISSCC), is sponsored by the IEEE Circuits & Systems Society. Notably, this is the first time in the award’s history that the honoree comes from the commercial electronics industry, with previous recipients coming from academia and research.

“Marcel’s work literally transformed generations of chip designs and is a linchpin in the advancement of a wide range of circuitry that forms the foundation of devices that touch our lives every day,” said Lars Reger, CTO, Automotive at NXP. “His significant contributions helped NXP establish a leadership position in high-performance, mixed-signal circuits and we continue to make use of his insights in virtually every technology we use, both analog and digital. More significantly, it inspired and enabled thousands of engineers throughout the world, and sparked a broader movement in understanding statistical phenomena across the semiconductor industry. I deeply admire his work.”

Pelgrom is most known for his formulation of the random variation (mismatch) behavior between two otherwise identical components. His work is the starting point for proper analysis of matching, essential for accurate analog circuits. The Pelgrom Law or “Pelgrom Model” has been accepted by the global device and design community as an elegant description for mismatch. His 1989 prediction still holds after more than 12 technology generations. The general formulation of the model has allowed applications to other devices, like bipolar devices, resistors and capacitors.

Pelgrom’s contribution has had a dramatic impact on the design efficiency of analog designers, allowing engineers to optimize designs for lowest power and highest yield. Pelgrom’s mismatch model has become an essential performance metric for technology optimization, serving as the key element of communication between the technologists and device physicists on one hand and the design community on the other.

“I am incredibly honored to be recognized by the IEEE and included in such prestigious company of past Kirchhoff Award winners. The namesake of the award is a true pioneer and personal inspiration to me, so it is especially meaningful,” said Pelgrom. “I am also extremely grateful for the opportunities Philips and NXP have given me over the years to pursue my research and provide a practical means to see it implemented to benefit actual chip designers and product developers. The freedom and resources to research and be surrounded with such gifted fellow engineers has been an essential factor in our ability to advance our findings. I am happy to see my colleagues continuing and expanding this research field to keep our company at the forefront of high performance circuits.”

After earning degrees from the Arnhem Polytechnical School (BEE with honors) and the University of Twente (MEE with honors and a Ph.D), Pelgrom began his a career in 1979 at Philips Research, which later became part of NXP. In addition to his groundbreaking research, during that time he wrote three books on AD conversion and taught this topic to generations of R&D engineers at NXP. He retired from NXP in 2013 and is still active as an advisor, consultant and trainer. He regularly teaches classes at TU Delft, University of Twente and Stanford University and serves as honorary professor at the KU Leuven.