Tag Archives: letter-wafer-tech

Traditional computer memory, known as DRAM, uses electric fields to store information. In DRAM, the presence or absence of an electric charge is indicated either by number 1 or number 0. Unfortunately, this type of information storage is transient and information is lost when the computer is turned off. Newer types of memory, MRAM and FRAM, use long-lasting ferromagnetism and ferroelectricity to store information. However, no technology thus far combines the two.

To address this challenge, a group of scientists led by Prof. Masaki Azuma from the Laboratory for Materials and Structures at Tokyo Institute of Technology, along with associate Prof. Hajime Hojo at Kyushu University previously at Tokyo Tech, Prof. Ko Mibu at Nagoya Institute of Technology and five other researchers demonstrated the multiferroic nature of a thin film of BiFe1?xCoxO3 (BFCO). Multiferroic materials exhibit both ferromagnetism and ferroelectricity. These are expected to be used as multiple-state memory devices. Furthermore, if the two orders are strongly coupled and the magnetization can be reversed by applying an external electric field, the material should work as a form of low power consumption magnetic memory.

Previous scientists had speculated that ferroelectric BFO thin film, a close relative of BFCO, might be ferromagnetic as well, but they were thwarted by the presence of magnetic impurity. Prof. M. Azuma’s team successfully synthesized pure, thin films of BFCO by using pulsed laser deposition to perform epitaxial growth on a SrTiO3 (STO) substrate. They then conducted a series of tests to show that BFCO is both ferroelectric and ferromagnetic at room temperature. They manipulated the direction of ferroelectric polarization by applying an electric field, and showed that the low-temperature cychloidal spin structure, essentially the same as that of BiFeO3, changes to a collinear one with ferromagnetism at room temperature.

In the future, the scientists hope to realize electrical control of ferromagnetism, which could be applied in low power consumption, non-volatile memory devices.

When most living creatures get hurt, they can self-heal and recover from the injury. But, when damage occurs to inanimate objects, they don’t have that same ability and typically either lose functionality or have their useful lifecycle reduced. Researchers at the Beckman Institute for Advanced Science and Technology are working to change that.

For more than 15 years, Jeff Moore, a professor of chemistry, Nancy Sottos, a professor of materials science and engineering, and Scott White, a professor of aerospace engineering, have been collaborating in the Autonomous Materials Systems Group. Their work focuses on creating synthetic materials that can react to their environment, recover from damage, and even self-destruct once their usefulness has come to an end.

The trio of Beckman researchers are pioneers in what is now a dynamic and growing field. Their work on self-healing polymers was first presented in the journal Nature more than a decade-and-a-half ago. Prior to that, there had been just a few papers published on the subject of autonomous polymers. In the years since, research in the field has exploded, with hundreds of papers published.

Now, in a sweeping perspective article published this month in the journal Nature, the researchers, along with Beckman Postdoctoral Fellows Jason Patrick and Maxwell Robb, review the state-of-the-art autonomous polymers and lay out future directions for the field.

“What we’ve tried to capture for the first time is a vision of polymers as multifunctional entities that can manage their well-being,” Moore said.

The article is an overview of how their work has evolved from the development of self-healing polymers to a concentration on “life cycle control of polymers” — what he called “the healthy aging of materials.” He described the autonomous function of materials this way: “Live long, be fit, die fast, and leave no mess behind. … We want the materials to live as long as they can in a healthy state and, when the time comes, be able to trigger the inevitable from a functional state to recoverable materials resources.”

In the paper, the researchers identified five landscape-altering developments: self-protection, self-reporting, self-healing, regeneration, and controlled degradation.

Much of their work revolves around microcapsules, which are small, fluid-filled spheres that can be integrated into various material systems. The capsules contain a healing agent that is released automatically when exposed to a specific environmental change, such as physical damage or excessive temperature.

“You have capsules that remain stable in the material until the environment causes a stress that causes them to rupture,” explained Sottos. “A lot of different external stimuli can open up the capsules. You can have a thermal trigger, a mechanical trigger, and we’ve worked a lot on chemical triggers. They open up, release their contents, and the science is in what comes out and reacts.”

By developing new chemistries and ways to integrate microcapsules over the years, the researchers have created polymers that can do everything from re-filling minor damage in paints and coatings (self-protecting), changing color when undergoing stress (self-reporting), and re-bonding cracks or restoring electrical conductivity (self-healing).

The AMS Group also developed a way to efficiently fabricate vascular networks within polymers. These networks, which can include multiple channels that run throughout a material, are able to deliver healing agents multiple times, change thermal or magnetic properties, and facilitate other useful chemical interactions in a material.

A major development in their self-healing work focuses on repairing large-scale damage through the process of regeneration.

“Ballistic impacts, drilling holes in sheets of plastic, and these sorts of things, where a significant mass is lost … traditional self-healing has no way of dealing with that problem at all,” White said. “The materials that would be used to heal that hole would simply fall out, bleed out under gravity.”

So White and his collaborators came up with a two-channel healing system. When damage occurs on a large scale, a gel-like substance fills the space and builds upon itself, keeping the healing agents in place until they harden.

Their most recent work is concerned with how to deal with material systems when they have reached the end of their useful life. This work involves making materials that can self-destruct when a specific environmental signal is given (triggered transience). The researchers believe that triggers such as high temperature, water, ultraviolet light, and many others may one day be used to make obsolete devices degrade quickly so that they can be reused or recycled, thus reducing electronic waste and boosting sustainability.

Autonomous polymers are beginning to make their way into the commercial sector. Commercialization efforts have produced materials such as wear-resistant mobile device cases and automotive paints that can self-repair minor scratches. And more self-healing products are slowly coming to market including a microcapsule-based powder coating produced by the Champaign-based start-up company Autonomic Materials Inc.

While the practical application of many of these techniques still face challenges, Moore, Sottos, White, and their colleagues continue to work toward the creation of smart materials that can function independently, self-heal, and disintegrate once they are no longer useful, offering the eventual promise of safer, more efficient, and longer-lasting products that require fewer resources and produce less waste.

At this week’s IEEE IEDM conference, imec, the research and innovation hub in nano-electronics and digital technologies showed for the first time a silicon (Si)-passivated germanium (Ge) nMOS gate stack with dramatically reduced interface defect density (DIT) reaching the same level as a Si gate stack and with high mobility and reduced positive bias temperature instability (PBTI). These promising results pave the way to Ge-based finFETs and gate all-around devices, as promising options for 5nm and beyond logic devices.

Today’s results were achieved by band engineering using an interface dipole at high-k/SiO2 interface, and a H2 high-pressure anneal (HPA) finalizing the process flow. The interface dipole was formed on SiO2 layer by depositing a Lanthanum (La)SiO layer by atomic layer deposition (ALD), which is a 3D-compatible process. While a high DIT has been the leading concern for Si-passivated Ge nFET, it was dramatically reduced, for the first time, from 2×1012 cm-2eV-1 down to 5×1010 cm-2eV-1 around midgap using a combination of the LaSiO insertion and a H2 HPA. Consequently, electron mobility was increased (approximately 50 percent at peak) while PBTI reliability was improved thanks to the interface dipole-induced band engineering.

At IEEE IEDM, imec also presents a model for heterostructure interface resistivity (Rhi) analysis for highly doped semiconductors. Using this novel model, imec predicted that high-doping Si:P in a TiSix/Si:P/n-Ge contact stack helps to overcome the high contact resistance problem in Ge nMOS. With development of an advanced low-temperature Si:P epitaxy technique, imec demonstrated a TiSix/Si:P/n-Ge contact stack with record-low contact resistivity for n-Ge.

“Dedicated to push the boundaries of Moore’s Law, Ge-based devices are a key focus area or our research,” stated An Steegen, Executive Vice President Semiconductor Technology and Systems. “These breakthrough achievements underscore our dedication to understanding the fundamental roadblocks that need to be overcome in order for Ge-based devices to become a viable solution for 5nm and beyond.”

This work was performed in collaboration with ASM, Poongsan and Nanyang Technological University. Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony and TSMC.

Scientists often discover interesting things without completely understanding how they work. That has been the case with an experimental memory technology in which temperature and voltage work together to create the conditions for data storage. But precisely how was unknown.

But when a Stanford team found a way to untangle the chip’s energy and heat requirements, their tentative findings revealed a pleasant surprise: The process may be more energy efficient than was previously supposed. That’s good news for next-generation mobile devices whose batteries would last longer if they were powering lower energy chips.

The group that made this discovery, led by Stanford electrical engineer H.-S. Philip Wong, is presenting the paper when the IEEE International Electron Devices Meeting (IEDM) brings leading researchers to San Francisco Dec. 5.

The new technology the team investigated is called resistive random-access memory, or RRAM for short. RRAM is based on a new type of semiconductor material that forms digital zeros and ones by resisting or permitting the flow of electrons. RRAM has the potential to do things that aren’t possible with silicon: for instance, being layered on top of computer transistors in new three-dimensional, high-rise chips that would be faster and more energy efficient than current electronics, which is ideal for smartphones and other mobile devices where energy efficiency is a vital feature.

But while engineers can observe that RRAM does store data, they don’t know exactly how these new materials work. “We need much more precise information about the fundamental behavior of RRAM before we can hope to produce reliable devices,” Wong said.

Jolting memory

So to help engineers understand some of the unknowns, Wong’s team built a tool to measure the basic forces that make RRAM chips work.

Graduate student Zizhen Jiang of the Stanford team explained the basics: RRAM materials are insulators, which normally do not allow electricity to flow, she said. But under certain circumstances, insulators can be induced to let electrons flow. Past research had shown how: Jolting RRAM materials with an electric field causes a pathway to form that permitted electron flows. This pathway is called a filament. To break the filament, researchers apply another jolt and the material becomes an insulator again. So each jolt switched the RRAM from zero to one or back, which is what makes the material useful for data storage.

But electricity is not the only force at play in RRAM switching. Pumping electrons into any material raises its temperature. That’s the principle behind electric stoves. In the case of RRAM, it was the elevated temperature caused by introducing voltage that induced filaments to form or break. The question was what voltage-induced temperature was needed to cause the switching. No one knew.

Before the new Stanford study researchers thought short bursts of voltage, sufficient to generate temperatures of about 1,160 degrees Fahrenheit – hot enough to melt aluminum – was the switching point. But those were estimates because there was no way to measure the heat generated by an electric jolt.

“In order to begin to answer our questions, we had to decouple the effects of voltage and temperature on filament formation,” said Ziwen Wang, another graduate student on the team.

Dissecting the heat needs

Essentially, the Stanford researchers had to heat the RRAM material without using an electric field. So they put an RRAM chip on a micro thermal stage (MTS) device – a sophisticated hot plate capable of generating a wide range of temperatures inside the material. Of course the objective was not merely to heat the material, but also to measure how filaments formed. Here they took advantage of the fact that RRAM materials are insulators in their natural state. That makes them digital zeros. As soon as a filament formed electrons would flow. The digital zero would become a digital one, which the researchers could detect.

Using this experimental model, the team put RRAM chips on the burner and cranked up the heat, starting at about 80 F – roughly the temperature of a warm room – all the way up to 1,520 F, hot enough to melt a silver coin. Heating the RRAM to various temperatures in between these extremes, the researchers measured precisely if and how RRAM switched from its native zero to a digital one.

To their pleasant surprise, the researchers observed that filaments could form more efficiently at ambient temperatures between 80 F and 260 F, which is hotter than boiling water – contrary to prior expectation that hotter was better.

If confirmed by subsequent research, this would be good news because in a working chip the switching temperature would be created by the voltage and duration of the electric jolt. Efficient switching at lower temperatures would require less electricity and make RRAM more energy efficient and extend battery life when used as the memory in mobile devices.

Much work remains to be done to make RRAM memory practical but this research provides the test bed to vary conditions systematically instead of relying on hit-and-miss hunches.

“Now we can use voltage and temperature as design inputs in a predictive manner and that is going to enable us to design a better memory device,” Wang said.

Henry Chen, a Stanford alumnus who earned his PhD in Wang’s lab, gave this research a big assist and was a co-author on the paper. Chen, now with the Chinese memory chip-manufacturing firm GigaDevices Semiconductor Inc., helped develop the concepts and instruments that enabled the researchers to make the measurements being reported at IEDM.

Leti, an institute of CEA Tech, presented two papers at IEDM 2016 today that demonstrate its ability to provide industry with all the elements required for building a competitive 5nm node with nanowire architectures.

Nanowire architectures are seen as the best candidates for that node, and Leti is addressing some of its biggest challenges, such as of performance and parasitic capacitances. Its results suggest that strain can be introduced into stacked nanowire and that parasitic capacitances can be reduced thanks to inner spacer integration.

The paper, “Vertically Stacked-Nanowires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain”, is the first demonstration of functional devices with SiGe source and drain to induce strain in the channel to boost performance, and inner spacer to reduce parasitic capacitances. Both building blocks are required for the 5-nm node. This MOSFET architecture extends the scaling limits of CMOS technology, and is also seen as a possible extension to FinFET.

Leti, at IEDM 2008, was among the world’s first organizations to report stacked nanowire and nanosheet results.

The second paper, “NSP: Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs”, presents a predictive and physical compact model for nanowire and nanosheet gate-all-around MOSFETs.

“This is the first compact model, or SPICE model, that can simulate stacked nanowire and nanosheet devices with various geometries,” said Olivier Faynot, Leti’s microelectronics section manager and a co-author of both papers. “It also enables the simulation of vertical nanowire, which is one of the key achievements of this model.”

The paper presents a physically based SPICE model for stacked nanowires that can enable circuit designers to accurately project their existing circuits into the 5-nm node, and investigate novel designs.

University of Texas at Dallas physicists have published new findings examining the electrical properties of materials that could be harnessed for next-generation transistors and electronics.

Dr. Fan Zhang, assistant professor of physics, and senior physics student Armin Khamoshi recently published their research on transition metal dichalcogenides, or TMDs, in the journal Nature Communications. Zhang is a co-corresponding author, and Khamoshi is a co-lead author of the paper, which also includes collaborating scientists at Hong Kong University of Science and Technology.

In recent years, scientists and engineers have become interested in TMDs in part because they are superior in many ways to graphene, a one-atom thick, two-dimensional sheet of carbon atoms arranged in a lattice. Since it was first isolated in 2004, graphene has been investigated for its potential to replace conventional semiconductors in transistors, shrinking them even further in size. Graphene is an exceptional conductor, a material in which electrons move easily, with high mobility.

“It was thought that graphene could be used in transistors, but in transistors, you need to be able to switch the electric current on and off,” Zhang said. “With graphene, however, the current cannot be easily switched off.”

Beyond Graphene

In their search for alternatives, scientists and engineers have turned to TMDs, which also can be made into thin, two-dimensional sheets, or monolayers, just a few molecules thick.

“TMDs have something graphene does not have — an energy gap that allows the flow of electrons to be controlled, for the current to be switched on and off,” Khamoshi said. “This gap makes TMDs ideal for use in transistors. TMDs are also very good absorbers of circularly polarized light, so they could be used in detectors. For these reasons, these materials have become a very popular topic of research.”

One of the challenges is to optimize and increase electron mobility in TMD materials, a key factor if they are to be developed for use in transistors, Khamoshi said.

In their most recent project, Zhang and Khamoshi provided the theoretical work to guide the Hong Kong group on the layer-by-layer construction of a TMD device and on the use of magnetic fields to study how electrons travel through the device. Each monolayer of TMD is three molecules thick, and the layers were sandwiched between two sheets of boron nitride molecules.

The behavior of electrons controls the behavior of these materials,” Zhang said. “We want to make use of highly mobile electrons, but it is very challenging. Our collaborators in Hong Kong made significant progress in that direction by devising a way to significantly increase electron mobility.”

The team discovered that how electrons behave in the TMDs depends on whether an even or odd number of TMD layers were used.

“This layer-dependent behavior is a very surprising finding,” Zhang said. “It doesn’t matter how many layers you have, but rather, whether there are an odd or even number of layers.”

Electron Physics

Because the TMD materials operate on the scale of individual atoms and electrons, the researchers incorporated quantum physics into their theories and observations. Unlike classical physics, which describes the behavior of large-scale objects that we can see and touch, quantum physics governs the realm of very small particles, including electrons.

On the size scale of everyday electrical devices, electrons flowing through wires behave like a stream of particles. In the quantum world, however, electrons behave like waves, and the electrical transverse conductance of the two-dimensional material in the presence of a magnetic field is no longer like a stream — it changes in discrete steps, Zhang said. The phenomenon is called quantum Hall conductance.

“Quantum Hall conductance might change one step by one step, or two steps by two steps, and so on,” he said. “We found that if we used an even number of TMD layers in our device, there was a 12-step quantum conductance. If we applied a strong enough magnetic field to it, it would change by six steps at a time.”

Using an odd number of layers combined with a low magnetic field also resulted in a 6-step quantum Hall conductance in the TMDs, but under stronger magnetic fields, it became a 3-step by 3-step phenomenon.

“The type of quantum Hall conductance we predicted and observed in our TMD devices has never been found in any other material,” Zhang said. “These results not only decipher the intrinsic properties of TMD materials, but also demonstrate that we achieved high electron mobility in the devices. This gives us hope that we can one day use TMDs for transistors.”

They’re flexible, cheap to produce and simple to make – which is why perovskites are the hottest new material in solar cell design. And now, engineers at Australia’s University of New South Wales in Sydney have smashed the trendy new compound’s world efficiency record.

Dr. Anita Ho-Baillie, a Senior Research Fellow at the Australian Centre for Advanced Photovoltaics at UNSW, with the new perovskite cell. Credit: Rob Largent/UNSW

Dr. Anita Ho-Baillie, a Senior Research Fellow at the Australian Centre for Advanced Photovoltaics at UNSW, with the new perovskite cell. Credit: Rob Largent/UNSW

Speaking at the Asia-Pacific Solar Research Conference in Canberra on Friday 2 December, Anita Ho-Baillie, a Senior Research Fellow at the Australian Centre for Advanced Photovoltaics (ACAP), announced that her team at UNSW has achieved the highest efficiency rating with the largest perovskite solar cells to date.

The 12.1% efficiency rating was for a 16 cm2 perovskite solar cell, the largest single perovskite photovoltaic cell certified with the highest energy conversion efficiency, and was independently confirmed by the international testing centre Newport Corp, in Bozeman, Montana. The new cell is at least 10 times bigger than the current certified high-efficiency perovskite solar cells on record.

Her team has also achieved an 18% efficiency rating on a 1.2 cm2 single perovskite cell, and an 11.5% for a 16 cm2 four-cell perovskite mini-module, both independently certified by Newport.

“This is a very hot area of research, with many teams competing to advance photovoltaic design,” said Ho-Baillie. “Perovskites came out of nowhere in 2009, with an efficiency rating of 3.8%, and have since grown in leaps and bounds. These results place UNSW amongst the best groups in the world producing state-of-the-art high-performance perovskite solar cells. And I think we can get to 24% within a year or so.”

Perovskite is a structured compound, where a hybrid organic-inorganic lead or tin halide-based material acts as the light-harvesting active layer. They are the fastest-advancing solar technology to date, and are attractive because the compound is cheap to produce and simple to manufacture, and can even be sprayed onto surfaces.

“The versatility of solution deposition of perovskite makes it possible to spray-coat, print or paint on solar cells,” said Ho-Baillie. “The diversity of chemical compositions also allows cells be transparent, or made of different colours. Imagine being able to cover every surface of buildings, devices and cars with solar cells.”

Most of the world’s commercial solar cells are made from a refined, highly purified silicon crystal and, like the most efficient commercial silicon cells (known as PERC cells and invented at UNSW), need to be baked above 800°C in multiple high-temperature steps. Perovskites, on the other hand, are made at low temperatures and 200 times thinner than silicon cells.

But although perovskites hold much promise for cost-effective solar energy, they are currently prone to fluctuating temperatures and moisture, making them last only a few months without protection. Along with every other team in the world, Ho-Baillie’s is trying to extend its durability. Thanks to what engineers learned from more than 40 years of work with layered silicon, they’re are confident they can extend this.

Nevertheless, there are many existing applications where even disposable low-cost, high-efficiency solar cells could be attractive, such as use in disaster response, device charging and lighting in electricity-poor regions of the world. Perovskite solar cells also have the highest power to weight ratio amongst viable photovoltaic technologies.

“We will capitalise on the advantages of perovskites and continue to tackle issues important for commercialisation, like scaling to larger areas and improving cell durability,” said Martin Green, Director of the ACAP and Ho-Baillie’s mentor. The project’s goal is to lift perovskite solar cell efficiency to 26%.

The research is part of a collaboration backed by $3.6 million in funding through the Australian Renewable Energy Agency’s (ARENA) ‘solar excellence’ initiative. ARENA’s CEO Ivor Frischknecht said the achievement demonstrated the importance of supporting early stage renewable energy technologies: “In the future, this world-leading R&D could deliver efficiency wins for households and businesses through rooftop solar as well as for big solar projects like those being advanced through ARENA’s investment in large-scale solar.”

To make a perovskite solar cells, engineers grow crystals into a structure known as ‘perovskite’, named after Lev Perovski, the Russian mineralogist who discovered it. They first dissolve a selection of compounds in a liquid to make the ‘ink’, then deposit this on a specialised glass which can conduct electricity. When the ink dries, it leaves behind a thin film that crystallises on top of the glass when mild heat is applied, resulting in a thin layer of perovskite crystals.

The tricky part is growing a thin film of perovskite crystals so the resulting solar cell absorbs a maximum amount of light. Worldwide, engineers are working to create smooth and regular layers of perovskite with large crystal grain sizes in order to increase photovoltaic yields.

Ho-Baillie, who obtained her PhD at UNSW in 2004, is a former chief engineer for Solar Sailor, an Australian company which integrates solar cells into purpose-designed commercial marine ferries which currently ply waterways in Sydney, Shanghai and Hong Kong.

Following a decade of intensive research into graphene and two-dimensional materials a new semiconductor material shows potential for the future of super-fast electronics.

The new semiconductor named Indium Selenide (InSe) is only a few atoms thick, similarly to graphene. The research was reported in Nature Nanotechnology this week by researchers of The University of Manchester and their colleagues at The University of Nottingham.

Graphene is just one atom thick and has unrivalled electronic properties, which has led to widely-publicised suggestions about its use in future electronic circuits.

For all its superlative properties graphene has no energy gap. It behaves more like a metal rather than a normal semiconductor, frustrating its potential for transistor-type applications.

The new research shows that InSe crystals can be made only a few atoms thick, nearly as thin as graphene. InSe was shown to have electronic quality higher than that of silicon which is ubiquitously used in modern electronics.

Importantly, unlike graphene but similar to silicon, ultra-thin InSe has a large energy gap allowing transistors to be easily switched on and off, allowing for super-fast next-generation electronic devices.

Combining graphene with other new materials, which individually have excellent characteristics complementary to the extraordinary properties of graphene, has resulted in exciting scientific developments and could produce applications as yet beyond our imagination.

Sir Andre Geim, one of the authors of this study and a recipient of the Nobel Prize in Physics for research on graphene, believes that the new findings could have a significant impact on development of future electronics.

“Ultra-thin InSe seems to offer the golden middle between silicon and graphene. Similar to graphene, InSe offers a naturally thin body, allowing scaling to the true nanometre dimensions. Similar to silicon, InSe is a very good semiconductor.”

The Manchester researchers had to overcome one major problem to create high-quality InSe devices. Being so thin, InSe is rapidly damaged by oxygen and moisture present in the atmosphere. To avoid such damage, the devices were prepared in an argon atmosphere using new technologies developed at the National Graphene Institute.

This allowed high-quality atomically-thin films of InSe for the first time. The electron mobility at room temperature was measured at 2,000 cm2/Vs, significantly higher than silicon. This value increases several times at lower temperatures.

Current experiments produced the material several micrometres in size, comparable to the cross-section of a human hair. The researchers believe that by following the methods now widely used to produce large-area graphene sheets, InSe could also soon be produced at a commercial level.

Co-author of the paper Professor Vladimir Falko, Director of the National Graphene Institute said: “The technology that the NGI has developed for separating atomic layers of materials into high-quality two-dimensional crystals offers great opportunities to create new material systems for optoelectronics applications. We are constantly looking for new layered materials to try.”

Ultra-thin InSe is one of a growing family of two-dimensional crystals that have a variety of useful properties depending on their structure, thickness and chemical composition.

Currently, research in graphene and related two-dimensional materials is the fastest growing field of materials science that bridges science and engineering.

Controlling the flow of heat through semiconductor materials is an important challenge in developing smaller and faster computer chips, high-performance solar panels, and better lasers and biomedical devices.

For the first time, an international team of scientists led by a researcher at the University of California, Riverside has modified the energy spectrum of acoustic phonons– elemental excitations, also referred to as quasi-particles, that spread heat through crystalline materials like a wave–by confining them to nanometer-scale semiconductor structures. The results have important implications in the thermal management of electronic devices.

Led by Alexander Balandin, Distinguished Professor of Electrical and Computing Engineering and UC Presidential Chair Professor in UCR’s Bourns College of Engineering, the research is described in a paper published Thursday, Nov. 10, in the journal Nature Communications. The paper is titled “Direct observation of confined acoustic phonon polarization branches in free-standing nanowires.”

The team used semiconductor nanowires from Gallium Arsenide (GaAs), synthesized by researchers in Finland, and an imaging technique called Brillouin-Mandelstam light scattering spectroscopy (BMS) to study the movement of phonons through the crystalline nanostructures. By changing the size and the shape of the GaAs nanostructures, the researchers were able to alter the energy spectrum, or dispersion, of acoustic phonons. The BMS instrument used for this study was built at UCR’s Phonon Optimized Engineered Materials (POEM) Center, which is directed by Balandin.

Controlling phonon dispersion is crucial for improving heat removal from nanoscale electronic devices, which has become the major roadblock in allowing engineers to continue to reduce their size. It can also be used to improve the efficiency of thermoelectric energy generation, Balandin said. In that case, decreasing thermal conductivity by phonons is beneficial for thermoelectric devices that generate energy by applying a temperature gradient to semiconductors.

“For years, the only envisioned method of changing the thermal conductivity of nanostructures was via acoustic phonon scattering with nanostructure boundaries and interfaces. We demonstrated experimentally that by spatially confining acoustic phonons in nanowires one can change their velocity, and the way they interact with electrons, magnons, and how they carry heat. Our work creates new opportunities for tuning thermal and electronic properties of semiconductor materials,” Balandin said.

Astronics Corporation (NASDAQ:ATRO), through its wholly-owned subsidiary Astronics Test Systems, introduced its new breakthrough System-Level Test (SLT) platform that is expected to revolutionize the testing of high volume integrated semiconductor devices.  The new ATS 5034 System-Level Test (SLT) Platform improves production efficiency and greatly reduces the cost of test by processing up to 396 devices simultaneously.

This new platform is ideal for testing the latest semiconductor devices for mobile, automotive, wearable and industrial applications.  The ATS 5034 SLT Platform can be tailored to meet precise production test requirements.  Customers will benefit from the dramatically reduced footprint of the ATS 5034 SLT Platform and the ability to test up to 5,000 units per hour (UPH).

“For the past 20 years, we’ve provided system-level and burn-in testers that have tested more than 9 billion semiconductor devices globally,” explained Jon Sinskie, Executive Vice President of Astronics Test Systems.  “The ATS 5034 SLT Platform is our newest tester, which for the first time offers an affordable method for semiconductor manufacturers to improve yields by implementing a 100% SLT test insertion in production.”

Affordable 100% SLT through a Massively Parallel Platform

The new ATS 5034 SLT Platform tests integrated semiconductors in “mission mode” to verify performance of the semiconductor at the operating level.  Traditionally a difficult, expensive test insertion, the new ATS 5034 makes it simple for manufacturers to now transition to 100% SLT affordably.  An engineer can design a test sequence for a single site, and the ATS 5034 SLT Platform easily scales that sequence to hundreds of sites.

“With the increasing complexity of today’s semiconductor devices and pressures to cost effectively hit aggressive time to market schedules, customers are looking for new ways to find defects that are missed during traditional ATE functional testing,” explained Anil Bhalla, Senior Marketing Manager for Astronics Test Systems.  “We’ve built a platform that enables customers to find these defects with SLT in a way that previously was not cost effective.”

Customizable and adaptable, this versatile modular platform satisfies a variety of manufacturing test functions including system characterization, validation, and qualification, system-level test and RMA/failure debug.

Key features include:

  • Testing of integrated semiconductor devices, such as microprocessors, microcontrollers, and embedded systems
  • Test up to 396 devices simultaneously, at a rate of up to 5,000 UPH
  • Support for popular package types: system on chip (SoC), module, and heterogeneous system in package (SiP)
  • Turnkey automation with JEDEC trays input and outputs, including lot cascading
  • Astronics’ ActivATE™ software, an easy-to-use test executive
  • Extremely accurate thermal stress testing capability (+/- 1° C)
  • Small factory footprint

Astronics can further customize this platform for various low, medium or high volume system-level test scenarios.  This platform also includes support from the Astronics program management organization, which oversees installation and maintenance at any global location.  Units are in production and shipping in the first quarter of 2017.