Tag Archives: letter-wafer-tech

The Semiconductor Industry Association (SIA), in consultation with Semiconductor Research Corporation (SRC), today presented its University Research Award to professors from the University of Chicago and the University of Michigan in recognition of their outstanding contributions to semiconductor research.

Dr. Paul Nealey, professor of molecular engineering at the University of Chicago, received the honor for excellence in technology research, while Dr. David T. Blaauw, professor of electrical engineering and computer science at the University of Michigan, was recognized for excellence in design research.

“Research brings to life the tremendous innovations that underpin the U.S. semiconductor industry, the broader tech sector, and our economy,” said John Neuffer, president and CEO of the Semiconductor Industry Association, which represents U.S. leadership in semiconductor manufacturing, design, and research.

“Professors Nealey and Blaauw have led research efforts that have advanced semiconductor technology and strengthened America’s global technology leadership. It is an honor to recognize Dr. Nealey and Dr. Blaauw for their landmark accomplishments.”

“SRC’s mission is to drive focused industry research to both advance state-of-the-art technology and continue to create a pipeline of qualified professionals who will serve as next-generation leaders for the industry,” said Ken Hansen, SRC President and CEO. “Dr. Nealey and Dr. Blaauw exemplify that spirit of innovation, and we’re pleased to honor them for their achievements.”

Dr. Nealey is a pioneer of directed self-assembly, which is becoming very important in microelectronics processing to create patterns for integrated circuits. He is one of the world’s leading experts on patterning organic materials. This entails creating physical patterns of structure and composition in organic materials at the nanometer length scale, where the patterns affect the function of the materials. Dr. Nealey holds 14 patents and is the author of more than 180 publications.

Dr. Blaauw worked for Motorola, Inc. from 1993-2001, where he was the manager of the High Performance Design Technology group. Since August 2001, he has been on the faculty at the University of Michigan where he is currently a full professor. His work has focused on VLSI design with particular emphasis on adaptive and low-power design. Dr. Blaauw received his B.S. from Duke University in 1986 and his Ph.D. from the University of Illinois, Urbana, in 1991.

The University Research Award was established in 1995 to recognize lifetime research contributions to the U.S. semiconductor industry by university faculty.

Cascade Microtech, a FormFactor company (NASDAQ:FORM), and a supplier of solutions that enable precision measurements of discrete devices and integrated circuits (ICs) at the wafer level, today announced the launch of the Estrada-EM system – the industry’s first integrated measurement solution (IMS) to offer high-performance electromigration (EM) wafer-level reliability (WLR) testing of copper lines and vias in an oxygen-depleted environment. The Estrada-EM system delivers important WLR benefits to a test industry which has traditionally been limited to package-level reliability (PLR) test methods alone for EM. By overcoming several long-standing technical hurdles, this new product enables semiconductor reliability test programs to produce faster test results and assure high data integrity.

Electromigration is widely recognized to be a critical reliability issue for state of the art semiconductor technologies, and expected to become an even greater challenge at the 10 nm node and beyond. Proper evaluation of EM reliability necessitates the testing of many samples, under many conditions. By eliminating the packaging steps required for PLR, which delay the start of every test, the Estrada-EM WLR solution provides the same electromigration reliability answers days, or even weeks, sooner. In addition to eliminating the packaging delays, the system further boosts test program throughput with an extended-range thermal system for test acceleration, high-parallel test capacity, and unique features for unattended test which include automated in-situ probe alignment and autonomous dynamic thermal test profiles. The result is quicker technology evaluation cycles and faster fab process qualifications, for reduced time to market and increased profitability.

Today’s environment of shrinking reliability margins and increasingly sophisticated IC design rules demands not only fast results, but also highly accurate test data. WLR testing with the Estrada-EM IMS entirely avoids the risk of latent water and ESD damage which can occur in the test structures during the wafer sawing, structure bonding, and package handling which occurs for PLR. To further enhance data integrity, the system’s source measurement units (SMUs) incorporate unique performance capabilities such as programmable compliance to ensure the legitimacy of breakdown mechanisms and continuous monitoring to capture maximum data detail. This meticulous care leads to the industry’s most well-informed interconnect reliability models and technology decisions.

These benefits are extended to the full reliability test market by Cascade Microtech’s revolutionary PureZone oxygen-purging chamber system, which carefully wraps the wafer in an inert gas environment to prevent oxidation of copper pads and structures. This innovation enables, for the first time, direct testing of all wafers with copper interconnect technologies, including those without pad capping or passivation and even partially-processed wafers.

“Today’s technology race puts pressure on reliability labs for quicker answers, and the complexity of new nodes means a variety of materials and structures need to be evaluated in a compressed timeframe,” said Mike Slessor, President and CEO, FormFactor, Inc. “We’re happy to be able to help our customers accelerate design and qualification cycles by using EM WLR to complement EM PLR as they respond to emerging reliability challenges.”

GLOBALFOUNDRIES today introduced a scalable, embedded magnetoresistive non-volatile memory technology (eMRAM) on its 22FDX platform, providing system designers with access to 1,000x faster write speeds and 1,000x more endurance than today’s non-volatile memory (NVM) offerings. 22FDX eMRAM also features the ability to retain data through 260°C solder reflow, industrial temperature operation, while maintaining an industry-leading eMRAM bitcell size.

GLOBALFOUNDRIES’ eMRAM will be offered initially on its 22FDX platform, which leverages the industry’s first 22nm fully-depleted silicon-on-insulator (FD-SOI) technology. This versatile eMRAM technology is designed for both code storage (flash) and working memory (SRAM) to enable ultra-efficient memory sub-systems that can be power cycled without any energy or performance penalty. The power efficiency of FDX and eMRAM, coupled with the available RF connectivity IP, makes 22FDX an ideal platform for battery-powered IoT products and automotive MCUs.

“Customers are looking for a high-performance non-volatile memory solution that expands their product capabilities,” said Gregg Bartlett, senior vice president CMOS Platforms Business Unit, GLOBALFOUNDRIES. “Our introduction of 22FDX eMRAM enables system designers with new capabilities, allowing them to build greater functionality into their MCUs and SoCs, while enhancing performance and power efficiency.”

The emergence of autonomous vehicles is rapidly driving the need for increased on-chip memory capacities required for real-time vision processing, high-precision, continuous 3D mapping data and next-generation automotive MCUs that update over-the-air. GLOBALFOUNDRIES’ eMRAM uniquely addresses these advanced driving assistance system (ADAS) requirements by combining greater memory density than SRAM, with the fast write, very high endurance, and non-volatility that only magnetoresistive memory can provide.

“Emerging non-volatile memories are moving from the lab to the fab,” said Thomas Coughlin, President of Coughlin Associates. “GLOBALFOUNDRIES’ 22FDX eMRAM will offer a major advancement in SoC capabilities, by leveraging the key performance attributes of embedded MRAM. Designers of battery powered IoT devices, automotive MCUs and SoCs and SSD storage controllers will certainly want to take advantage of this versatile embedded NVM technology.”

The introduction of GLOBALFOUNDRIES’ 22FDX eMRAM is a result of the company’s multi-year partnership with MRAM pioneer, Everspin Technologies. The partnership has already delivered the world’s highest density ST-MRAM in August, 2016  – Everspin’s 256Mb DDR3 perpendicular magnetic tunnel junction (pMTJ) product, which is now successfully sampling and is being readied for mass production at GLOBALFOUNDRIES.

GLOBALFOUNDRIES’ 22FDX eMRAM is currently in development and is expected to be available for customer prototyping in 2017, with volume production in 2018. GLOBALFOUNDRIES’ eMRAM technology is scalable beyond 22nm and is expected to be available on both FinFET and future FDX platforms.

Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, presented its highest honors Sept. 12 to professors from University of California, Berkeley and University of Minnesota at SRC’s annual TECHCON conference in Austin, Texas.

Dr. Tsu-Jae King Liu, TSMC Distinguished Professor in Microelectronics in the Department of Electrical Engineering and Computer Sciences(EECS) at UC Berkeley, received this year’s SRC Aristotle Award for outstanding teaching and a deep commitment to the educational experience of his students. With SRC support, Liu’s team at UC Berkeley has made numerous research contributions to the industry in areas including nanometer-scale semiconductor devices and technology, novel non-volatile memory devices and technology and M/NEMS technology for ultra-low-power integrated circuits.

Additionally, Dr. Chris Kim, a Professor in the Department of Electrical and Computer Engineering at Minnesota, was awarded the SRC Technical Excellence Award for his respective SRC-supported research and contributions to the industry in VLSI circuit design.

Selected by SRC member companies and SRC staff, the award-winning faculty and research teams are being recognized for their exemplary impact on semiconductor productivity through cultivation of technology and talent.

“Advanced research has been instrumental in propelling the semiconductor industry forward, and we are recognizing these valuable researchers and their teams for the critical work they have performed in helping the industry achieve technological triumphs,” said Ken Hansen, SRC CEO and President.

UC Berkeley and Minnesota research helps drive technology innovation

Dr. Liu, a member of the Kavli Energy NanoSciences Institute and Associate Dean of the College of Engineering at UC Berkeley, earned B.S., M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. Prior to joining UC Berkeley, she worked as a researcher at the Xerox Palo Alto Research Center. Dr. Liu’s current research activities include nanometer-scale logic and memory devices for energy-efficient electronics, and she currently leads research on millivolt nanomechanical switches under the NSF Center for Energy Efficient Electronics Science.

“I am very fortunate to have been able to work with many outstanding students during my career at UC Berkeley, and am humbled to receive this prominent recognition for our joint achievements,” said Dr. Liu. “SRC’s support has made it possible for us to make impactful contributions to society, for which I am very grateful.”

Dr. Kim, a recipient of the National Science Foundation’s CAREER award, received his B.S and M.S. degrees from Seoul National University and a Ph.D. from Purdue University. Prior to joining the University of Minnesota, he worked at Intel Corporation that also recognized him with an Intel Ph.D. Fellowship. His current research focuses on digital, mixed-signal and memory circuit design in advanced-CMOS and beyond-CMOS technologies.

“This award recognizes our group’s invention of a new class of compact on-chip sensors called “silicon odometers” that can accurately and efficiently measure circuit aging effects,” said Dr. Kim. “Over the span of several SRC projects, our team has experimentally demonstrated more than a dozen different odometer designs in technologies ranging from 130 to 32 nanometers.”

TECHCON showcases academia’s brightest

TECHCON brings together the brightest minds in microelectronics research to exchange news about the progress of research ranging from materials to architectures created by SRC’s network of more than 100 of the top engineering universities. Students and industry leaders discuss basic research that is intended to accelerate advancements for both private and public entities.

The presentation of the Aristotle and Technical Excellence awards reflects the purpose of TECHCON, which is to enable future generations of chip technology. The Aristotle Award is given to SRC-funded university faculty that have profoundly and continuously impacted their students’ professional performances in a way that provides long-term benefit to the SRC member companies. The Technical Excellence Awards recognize researchers who have made key contributions to technologies that significantly enhance the productivity of the semiconductor industry.

More than 12,000 students have been prepared by SRC programs, professors and mentors for entry into the semiconductor business. These students provide a path for technology transfer and a source of relevantly educated technical talent for the industry.

An overview of liquid-to-liquid cooling systems and their operating principles

BY MARKO NIEMANN, Regional Sales Director, Laird Engineered Thermal Systems, Cologne, Germany

Cooling and temperature control systems are used throughout semiconductor fabrication facilities. In fabrication facilities both large and small, hundreds to thousands of cooling systems are installed and operate continuously. The processes employed are usually setup as copy-exact, which means the process systems are developed and transferred from the OEM of the process tool. These crtitical production tools used in a semiconductor fabrication facilities are required to be reliable and easy to service to deliver minimum downtime. The same is required of the cooling systems that support them. Usually the cooling systems employed have a water- cooled evaporator instead of an air-cooled evaporator. A liquid-liquid unit is quieter than a liquid to air unit because a fan is not required. Even more important, the heat can be rejected by available general facility cooling water and the heat is not rejected into the air temperature conditioned environment. These cooling systems can be placed near the tool, hidden in a false floor or on the lower level in a sub-floor. Cooling systems are built to meet SEMI S2 or F47 standards. OEM customers vary in their demand according to their unique requirements, but compliance is mandatory and sometimes OEM customers ask to get certifications for SEMI S2 or F47, which includes for example seismic “protections.” In these fabrication facilities a variety of liquid cooling systems are used including: compressor and thermoelectric based recirculating chillers.

Cooling systems

Liquid cooling systems are required to:

  • Protect the tool process against chemical reaction by avoiding an unknown Wetted-Parts-Material-Mix
  • Achieve a stable temperature, independent from facility water temperatures that can change
  • Achieve a temperature below or above the facility water temperature
  • Solve different temperature or fluid requirements at one tool with a multi-loop liquid cooling system

In semiconductor fabrication facilities, the required temperature control range varies from -80°C to +150°C. For the majority of applications, only one stable temperature set point is required. In the final chip test environment however, temperatures are required to vary in order to stress the chip. Here different temperature set points need to be reached with a single thermal management system. Due to the high-precision processes, tool manufacturers demand a very stable temperature environment. Typical of these requirements are +/-0.1K stability (e.g. for etching) to ±0.001K (e.g. for lithography) while cooling capacities can be up to several kilowatts.

In semiconductor fabrication facilities, custom multi- stage compressor based chillers are used to support cooling for very low temperature requirements. Most standard chillers utilized need some form of modification to meet semiconductor process facility requirements and may even require a water-cooled condenser. Some of the installation base also uses thermoelectric (19” rack) cooling systems, i.e. for etch applications, instead of compressor-based systems.

The cooling capacity demands and the range over which the system operates varies from a couple of hundred Watts (thermoelectric chiller and compressor based systems) to hundreds of Kilowatts (liquid-to-liquid cooling systems). The majority of the installed base uses liquid-to-liquid cooling systems that operate close to ambient and are based on a fluid-to-fluid heat-exchange principle.

The cooling systems utilize facility water to prevent heat dissipation of the cooling unit from warming the cleanroom and destabilizing the process tool’s thermal management system. These liquid-to-liquid systems keep the air quality level high by avoiding dust up introduced from the airflow of an air-to-air thermal management system. This consideration is independent of the location of the thermal management system. Due to the cyclic nature of the market, product requirements change and time to market is crucial. The cooling system solution developed is usually a custom product with a unique approach and design specific to the OEM.

Technical requirements

Cooling systems are often placed in the sub-fab, which means they are located one or two floors below the tool they are connected to. For cooling systems that use water as coolant, the height between the tool and the cooling system cannot exceed 10 meters, otherwise the height difference can cause the water to boil as the pressure is lower than the vapor pressure of water.
If the cooling system is placed at a lower level, the coolant circuit can function as a closed loop to the atmosphere. In this case, the cooling unit needs to incorporate a closed pressurized reservoir (7 PSI pressure cap) to minimize over flow conditions. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap (FIGURE 1).

FIGURE 1. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap.

FIGURE 1. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap.

A standpipe reservoir introduces additional fluid to the liquid circuit as required, whereas a flow-through reservoir continuously exchange fluid. It is important to know that the pump simply needs to overcome the height and pressure difference one-time during start-up in a closed loop system, as the supply and return lines will equilibrate given that they have the same length and diameter.

Material compatibility

In the semiconductor process environment, copper and brass are materials with limited compatibility due to their susceptibility to galvanic corrosion. Wetted parts, which come in direct contact with the medium (liquid), are typically made of stainless steel. These parts range from the complete plumbing circuit of the cooling unit to the process loop. Stainless steel is usually used in the process loop due its resistance to galvanic corrosion or because a special fluid is used that is not compatible with PVC, copper, and brass etc. When stainless steel is required, the heat exchanger, valves and the pumps will require special consideration. Occasionally, stainless steel may require additional passivation or a limited subset of stainless steel materials may be used.

If copper or brass is used to accomodate cost considerations, the material needs to be insulated to minimize the thermal impact on the system from outside thermal sources. Special particle free insulation may be required in this instance.

Special fluids used in the semiconductor environment include: di-electric fluids (Galden, 3M Novec), which are non-conductive. Special hoses and sealings need to be used for these fluids and special attention to handling is also required. These coolants run in a closed loop as the fluid vapor pressure is relatively low compared to water.

The use of de-ionized water is common. Copper or brass can be run up to 3 MOhm-cm resistivity if the set point temperature does not exceed 30°C for extended periods of time. However to ensure long lifetimes and for higher resistivity demands, the cooling system should be equipped with a nickel brazed or complete passivated stainless steel evaporator/heat-exchanger. The pumps should be stainless steel and all component parts in contact with the fluid should be made of passivated stainless steel to prevent corrosion. This is referred to as high-purity plumbing. In addition, a DI cartridge can be equipped with an indicator light or regulated through the cooling system and the DI level will be constantly measured and monitored keeping to a preset resistivity. The DI cartridge filters the ions out of the fluid and needs to be replaced to ensure its effectiveness.

Valves

If the unit is placed below the fabrication floor, an anti- siphoning package can be used to avoid backflow of the fluid and prevent overflowing the unit in event the pump stops. The anti-siphoning package consists of a one-way check valve in the supply line and normally open solenoid valves triggered by the unit in the return line. The solenoid valve would close in case the pump stops and the one-way check valve allows for the flow in only one direction. Instead of a one-way check valve, another solenoid valve can be used, though this depends on the flow rate and size (FIGURE 2).

FIGURE 2. Instead of a one-way check valve, another solenoid valve can be used.

FIGURE 2. Instead of a one-way check valve, another solenoid valve can be used.

For a process facility, constant monitoring and control of the facility process water is required and modulating solenoid valves from Siemens or Bellimo need to be used. The valve diameter and actuating motor have to be sized correctly to achieve stable temperatures and trigger the correct switching cycles. Assuring this means the inclusion of a long- lasting actuator and facility water flowing through an acceptable pressure drop from the facility water supply and return. Sometimes three-way mixing valves are used. This allows for continuous flow into the facility water loop and adds cooling for the heat exchanger of the thermal management system when required. The constant flow back to the facility water loop avoids a water hammer in cases where it would close and reopen when cooling is required. Flow requirements can go be as high as hundreds of liters per minute.

Space consideration

Cleanroom costs can be up to $60,000 /m2, therefore the chiller footprint is important and can have a costly impact. Semiconductor cooling systems should be stackable (stacked high) and preferable narrow to maximize space and minimize their impact on costs. Therefore the design of a cooling system’s footprint needs to be closely examined. The system should also be located where it is easy to access from two sides. Routine maintenance on cooling systems is required to exchange components such as pumps, motors, valves and fans to maximize system uptime.

SEMI requirements

For a completed tool, OEMs require a SEMI S2 certification and sometimes a Semi F-47 certification in areas with high earthquake probability. As the SEMI S2 certification requires a high amount of documentation, subsystems like a cooling unit will finally be integrated into the tool. Most of the time it is sufficient to meet the intent of SEMI S2 and the OEM will do a full certification of the final tool with all sincorporated subsystems in their NRTL laboratory. Below are some items to consider when designing a cooling unit to meet SEMI S2 and F-47 standards.

SEMI S2:

  • Drip tray must be large enough to hold 110% of the volume of the largest container in the cooling product
  • EMO button and/or EMO connection
  • Seismic brackets, seismic tie downs for standalone units
  • A specific power connection setup depending on the power consumption

F-47:

  • Continue to run during a power drop for a given time and fixed reduction of power

These requirements vary from customer to customer, but to some extent the certification is known to the manufacturer of the system.

If the unit is not placed below the fabrication facility flooring, the cooling system will instead be placed in the cleanroom or a grey room. Again, requirements here can vary drastically from customer to customer. If the cooling system, sub-assembly or any component is required to be in the cleanroom, then the entire assembly including each component must be as clean as possible. This requires the entire manufacturing process to have a high level of attention to cleanliness. Debris, dust, burrs or chips occurring at every process step need to be examined and removed ideally after every fabrication step. The industry is quite sensitive to this.

After the final assembly, the cooling unit needs to go through a manual check with UV-light and wipe down for final cleaning with gloves. The unit is then double bagged and each bag needs to be labeled appropriately. There are suppliers who specialize in cleaning, to semicon- ductor standards, and this can be subcontracted. Since it contributes to the cost and lead-time, the level of detail used requires scrutiny.

Service

Selling a cooling unit into the semiconductor market requires long-term servicing agreements in the contract. If a product is qualified in one facility other facilities can take over the setup as a copy exact requirement and use the existing cooling solution. For this after-market service and support, full understanding of the end users demands is critical. Service and support needs to responsive. In the event a tool unexpectedly goes down, immediate support is required or the OEM can lose millions of dollars in revenue.

Once the tool is installed service needs to be done on-site on the same day of failure, as large cooling systems cannot be replaced easily or shipped back to manufacturer for repair. OEMs have moved away from purchasing redundant cooling systems as their processes are getting leaner and expenses are reviewed more closely. This puts the contractual emphasis on service and a global service infrastructure.

Ideally the manufacturer is aware of the service demands and support strategy of their customers. Systems today are designed to minimize the downtime and make use of hot swappable parts, such as pumps on rails or modular exchange of complete assemblies, including electrical control boxes.

Conclusion

A semiconductor fabrication facility’s unique environment makes designing and building a liquid based cooling system one of the most challenging environments. Careful consideration is required not only for component selection, but also on the overall liquid cooling system unit and its integration with a semiconductor tool. Challenges designers face include the type of heat transfer mechanism utilized on the control and heat dissipation sides, material compat- ibility, valve control, cleanliness, space optimization, semi compliance and serviceability. These are all areas in need of attention to detail to properly ensure an optimized total cost of ownership.

The global high-tech engineering and construction company M+W Group has presented current and future trends, as well as state of the art solutions, for an integrated approach to waste reduction in order to improve the sustainability of semiconductor fabs. The presentation was held at the High-Tech Facility International Forum 2016 in Taipei on 8th September in conjunction with the Semicon Taiwan trade show.

Having successfully contributed to the forum’s widely recognized meetings over the past two years M+W Group was also invited to this year’s expert meeting on high- tech facilities. There, M+W Group leading experts presented the company’s solutions for an Integrated Waste Reduction Program for Semiconductor Facilities. It was emphasized that minimization of waste produced in semiconductor wafer fabs and other high-tech facilities begins during the buildings’ design and must focus on both the construction as well as the operational phases.

Drawing on its globally recognized experience, M+W Group outlined how sustainability in a semiconductor wafer fab can best be evaluated, monitored and optimized through the application of a holistic Life Cycle Assessment (LCA) tool that provides systematic evaluation of all environmental aspects of a wafer fab during their construction, operational lifetime and decommissioning.
Herbert Blaschitz, CEO of M+W Group’s Global Business Unit Advanced Technology Facilities, said “There is an ever-increasing interest in the industry to implement fully sustainable semiconductor wafer fab solutions. We at M+W Group have broad and successful experience in this field and are proud to be at the forefront of this development.”

About the High-Tech Facility International Forum: As part of SEMICON Taiwan the High- Tech Facility International Forum 2016 focuses on cost-efficient waste reduction for sustainable facilities. The forum builds a platform for major players in the high tech facility community to discuss latest trends, challenges and outstanding solutions for the Taiwanese high-tech industry. Other members besides M+W Group include TSMC, UMC (wafer fab foundries for Integrated Circuits (IC)), Macronix, Inotera (IC memory manufacturers), AUO, Chimei Innolux (flat panel display manufacturers), ASE, SPIL (IC assembly), Epistar (LED Manufacturer) and Motech (PV module manufacturer).

Lam Research Corp. (Nasdaq: LRCX), an advanced manufacturer of semiconductor equipment, today announced that it is expanding its atomic layer etching (ALE) portfolio with the addition of ALE capability on its Flex dielectric etch systems. Enabled by Lam’s Advanced Mixed Mode Pulsing (AMMP) technology, the new ALE process has demonstrated the atomic-level control needed to address key challenges in scaling logic devices to 10nm and below. First in the industry to use plasma-enhanced ALE in production for dielectric films, the latest Flex system has been adopted as tool of record for high-volume manufacturing of logic devices.

“From transistor and contact creation to interconnect patterning, a new level of precision is needed by logic manufacturers to continue scaling beyond the 10nm technology node,” said Vahid Vahedi, group vice president, Etch Product Group. “For device-enabling applications like self-aligned contacts, where etch helps create critical structures, conventional technologies do not provide sufficient control for the stringent specifications now demanded. Our latest Flex product with dielectric ALE delivers atomic-scale control with proven productivity to meet customers’ key requirements.”

To continue logic device scaling, chipmakers are adopting new integration schemes such as those using self-aligned contacts (SACs) in order to address issues like RC delay. As a result, contact etch has become one of the most crucial processes, directly impacting both wafer yield and transistor performance. In order to define critical device structures with high fidelity, the etch process requires directional (anisotropic) capability with ultra-high selectivity, while also delivering the productivity needed for manufacturing.

For next-generation logic and foundry applications, Lam’s Flex dielectric etch systems offer the industry’s most advanced capacitively coupled plasma (CCP) reactor, featuring a unique, small-volume design to deliver repeatable results. The latest system uses proprietary AMMP technology to enable ALE of dielectric films such as silicon dioxide (SiO2). This capability results in a 2x improvement in selectivity over previous dielectric etch technologies while delivering atomic-level control.

Last March, the artificial intelligence (AI) program AlphaGo beat Korean Go champion LEE Se-Dol at the Asian board game.

“The game was quite tight, but AlphaGo used 1200 CPUs and 56,000 watts per hour, while Lee used only 20 watts. If a hardware that mimics the human brain structure is developed, we can operate artificial intelligence with less power,” points out Professor YU Woo Jong.

In the junctions (synapses) between neurons, signals are transmitted from one neuron to the next. TRAM is made by a stack of different layers: A semiconductor molybdenum disulfide (MoS2) layer with two electrodes (drain and source), an insulating hexagonal boron nitride (h-BN) layer and graphene layer. This two-terminal architecture simulates the two neurons that made up to the synaptic structure. When the difference in the voltage of the drain and the source is sufficiently high, electrons from the drain electrode tunnel through the insulating h-BN and reach the graphene layer. Memory is written when electrons are stored in the graphene layer, and it is erased by the introduction of positive charges in the graphene layer. CREDIT: IBS

In the junctions (synapses) between neurons, signals are transmitted from one neuron to the next. TRAM is made by a stack of different layers: A semiconductor molybdenum disulfide (MoS2) layer with two electrodes (drain and source), an insulating hexagonal boron nitride (h-BN) layer and graphene layer. This two-terminal architecture simulates the two neurons that made up to the synaptic structure. When the difference in the voltage of the drain and the source is sufficiently high, electrons from the drain electrode tunnel through the insulating h-BN and reach the graphene layer. Memory is written when electrons are stored in the graphene layer, and it is erased by the introduction of positive charges in the graphene layer. CREDIT: IBS

In collaboration with Sungkyunkwan University, researchers from the Center for Integrated Nanostructure Physics within the Institute for Basic Science (IBS), have devised a new memory device inspired by the neuron connections of the human brain. The research, published in Nature Communications, highlights the devise’s highly reliable performance, long retention time and endurance. Moreover, its stretchability and flexibility makes it a promising tool for the next-generation soft electronics attached to clothes or body.

The brain is able to learn and memorize thanks to a huge number of connections between neurons. The information you memorize is transmitted through synapses from one neuron to the next as an electro-chemical signal. Inspired by these connections, IBS scientists constructed a memory called two-terminal tunnelling random access memory (TRAM), where two electrodes, referred to as drain and source, resemble the two communicating neurons of the synapse. While mainstream mobile electronics, like digital cameras and mobile phones use the so-called three-terminal flash memory, the advantage of two-terminal memories like TRAM is that two-terminal memories do not need a thick and rigid oxide layer. “Flash memory is still more reliable and has better performance, but TRAM is more flexible and can be scalable,” explains Professor Yu.

TRAM is made up of a stack of one-atom-thick or a few atom-thick 2D crystal layers: One layer of the semiconductor molybdenum disulfide (MoS2) with two electrodes (drain and source), an insulating layer of hexagonal boron nitride (h-BN) and a graphene layer. In simple terms, memory is created (logical-0), read and erased (logical-1) by the flowing of charges through these layers. TRAM stores data by keeping electrons on its graphene layer. By applying different voltages between the electrodes, electrons flow from the drain to the graphene layer tunnelling through the insulating h-BN layer. The graphene layer becomes negatively charged and memory is written and stored and vice versa, when positive charges are introduced in the graphene layer, memory is erased.

IBS scientists carefully selected the thickness of the insulating h-BN layer as they found that a thickness of 7.5 nanometers allows the electrons to tunnel from the drain electrode to the graphene layer without leakages and without losing flexibility.

Flexibility and stretchability are indeed two key features of TRAM. When TRAM was fabricated on flexible plastic (PET) and stretachable silicone materials (PDMS), it could be strained up to 0.5% and 20%, respectively. In the future, TRAM can be useful to save data from flexible or wearable smartphones, eye cameras, smart surgical gloves, and body-attachable biomedical devices.

Last but not least, TRAM has better performance than other types of two-terminal memories known as phase-change random-access memory (PRAM) and resistive random-access memory (RRAM).

Microsemi Corporation (Nasdaq:  MSCC), a provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced it is renewing its current 50,000 euros scholarship program for University of Limerick engineering students living in County Clare, where the company has its European headquarters in Ennis, Ireland. In addition, the company announced its new “Microsemi Women in Engineering” scholarship and first award recipient.

Microsemi initially launched its 50,000 euros scholarship program with the University of Limerick in August 2012 as part of the company’s 20 year anniversary of operations in Ireland. Scholarships are awarded to a first-year engineering student from County Clare to the value of 3,000 euros per academic year, or 12,000 euros per student. The original 50,000 euros were awarded to a student for each of the four academic years (2012/2013, 2013/2014, 2014/2015 and 2015/2016), and now the company will grant the same scholarships to four new engineering students each December for four years beginning December 2016. Winners are selected objectively via the students’ scores on the Leaving Certificate, a national examination students complete at the end of secondary school.

“We are pleased to announce the continuation of our 50,000 euros scholarship program, as this introduces our company to some of the brightest talent in the region while supporting their academic achievements in engineering,” said Jim Aralis, chief technology officer and vice president of advanced development at Microsemi. “Leveraging our longstanding relationship with the University of Limerick, engineering students are exposed to internships, hands-on education and coursework which are extremely relevant to Microsemi’s business, products and technologies. Our scholarship program is both an investment in the future of our company and the success of our Clare community’s most deserving youth.”

In conjunction with the new 50,000 euros scholarship program, the company also announced its new “Microsemi Women in Engineering” scholarship, a one-time 2,000 euros award which will be presented to Eimear O’Sullivan in late August 2016. O’Sullivan will graduate from the University of Limerick with a Bachelor of Engineering in Electronic and Computer Engineering degree, with a First Class Honours. Microsemi’s new award is given to the highest performing graduating female student registered in the Bachelor of Engineering in Electronic and Computer Engineering, Bachelor of Engineering in Design and Manufacture, or Bachelor of Engineering in Mechanical Engineering courses at the University of Limerick.

“Expanding our support for the specific achievements of our female students here in our community reflects Microsemi’s ongoing commitment to diversity and to securing top talent for our company,” said Siobhan Dolan Clancy, vice president and general manager of Microsemi’s Discrete Products Group. “We congratulate Eimear for achieving such an impressive level of engineering education.”

The University of Limerick and Microsemi have worked together for decades to ensure top-tier engineering resources are available to all students, offering real-world training and education to prepare them for in-demand technology careers. The four recipients of Microsemi’s initial scholarships have each completed an internship or summer employment with Microsemi in one of its three Ireland facilities, reflecting the strong support system the institutions have developed together.

“The University is delighted with this new commitment from Microsemi, which not only rewards excellence in engineering generally, but also further strengthens the university’s commitment to gender equality through its ‘Women in Engineering’ prize,” said Professor Edmond Magner, dean of the Faculty of Engineering at the University of Limerick.

In addition, Laurence Egan, the first recipient of the Microsemi Scholarship in 2012, has just been announced as a joint winner of the Gold Medal from the University of Limerick. The Gold Medal is awarded annually to an undergraduate student at the university graduating with the highest overall Quality Credit Average (QCA) result in his or her final year of study and signifies the highest level of academic achievement.

Microsemi established its presence in Ireland in 1992 through the acquisition of a facility in Ennis, Co. Clare and in 2012 the company named the Ennis facility as its European headquarters. Over the past several years, Microsemi has made a significant investment in its Ennis operations and now employs 270 people, making it one of the largest employers in the area. Microsemi’s annual spend in Ireland is in excess of $20 million annually and it continues to recruit engineers and other technical professionals.

Researchers at Queen’s University Belfast and ETH Zurich, Switzerland, have created a new theoretical framework which could help physicists and device engineers design better optoelectronics, leading to less heat generation and power consumption in electronic devices which source, detect, and control light.

Speaking about the research, which enables scientists and engineers to quantify how transparent a 2D material is to an electrostatic field, Dr. Elton Santos from the Atomistic Simulation Research Centre at Queen’s, said: “In our paper we have developed a theoretical framework that predicts and quantifies the degree of ‘transparency’ up to the limit of one-atom-thick, 2D materials, to an electrostatic field.

“Imagine we can change the transparency of a material just using an electric bias, e.g. get darker or brighter at will. What kind of implications would this have, for instance, in mobile phone technologies? This was the first question we asked ourselves. We realised that this would allow the microscopic control over the distribution of charged carriers in a bulk semiconductor (e.g. traditional Si microchips) in a nonlinear manner. This will help physicists and device engineers to design better quantum capacitors, an array of subatomic power storage components capable to keep high energy densities, for instance, in batteries, and vertical transistors, leading to next-generation optoelectronics with lower power consumption and dissipation of heat (cold devices), and better performance. In other words, smarter smart phones.”

Explaining how the theory could have important implications for future work in the area, Dr. Santos added: “Our current model simply considers an interface formed between a layer of 2D material and a bulk semiconductor. In principle, our approach can be readily extended to a stack of multiple 2D materials, or namely, van der Waals heterostructures recently fabricated. This will allow us to design and predict the behaviour of these cutting-edge devices in prior to actual fabrication, which will significantly facilitate developments for a variety of applications. We will have an in silico search for the right combination of different 2D crystals while reducing the need for expensive lab work and test trials.”