Tag Archives: letter-wafer-tech

By Pete Singer, Editor-in-Chief

The semiconductor industry is moving quickly to adopt a variety of new materials in an effort to increase chip performance. These new materials can create a host of safety concerns that must be addressed. Many of the new process chemicals have low vapor pressures, are highly reactive and present serious hazards to personnel and equipment. Many new CVD precursors and their associated reaction by-products are flammable, pyrophoric, toxic, corrosive or otherwise hazardous to personnel or destructive to equipment. “The problem’s always been there. It’s just becoming more acute as new processes emerge,” said Andrew Chambers, Senior Product Manager at Edwards Ltd., Clevedon, UK.

The Danger That Lurks Figure

Process byproducts are pumped through exhaust lines to a gas abatement system. Residual precursor materials or reaction byproducts often have a tendency to condense in pipe-work, including process exhausts. These exhaust pipes must be cleaned regularly, since condensed material will block the pipe, reduce its conductance and cause process problems.

Epitaxial silicon (“epi”) deposition processes, for example, are particularly notorious for the process decomposition products condensing in exhaust pipes or in the foreline of the pump. The hazard is greatest when the exhaust system is dismantled for cleaning. “The condensed material can react violently when it’s exposed to air and will burn vigorously or even explode. That presents a pretty serious hazard to the service engineers who are charged with taking the pipe apart and cleaning it,” Chambers said.

These problems can largely be avoided, however, by keeping the exhaust pipe or the pump foreline at a high temperature to avoid condensation of the material. If the surfaces in the exhaust system are warm enough, the processed products transit through the exhaust pipe and into the abatement system, where they can be combusted and dealt with in a safe fashion.

In many fabs, the heating is done with heating tape, but that’s not always the best (or safest) way to go. “In principle, that works up to a point but it’s quite difficult to apply that kind of technique when you’ve got accessories like a large ball valve in the line, where there are brackets attaching the exhaust pipe to the wall or there’s a system for injecting nitrogen dilution gas into the exhaust. The idea of heater tapes is convenient but not a very effective fix,” Chambers said. “Furthermore, removing heater tape to dismantle and clean the exhaust pipe can be inconvenient and time consuming” he added.

What’s really required is an approach that involves heating the pipe in a uniform fashion so that the pipe is universally at a high temperature to avoid the condensation. “You can’t afford to have cold spots in the pipe where there’s no heater or there’s no insulation because the moment you have a cold spot in the pipe, then material’s going to condense there and cause a local blockage,” he said.

Edwards offers a new Temperature Management System (SMART TMS) that ensures these compounds remain volatile until they enter the abatement device. SMART TMS is designed to heat both forelines and pump exhaust lines uniformly as far as the inlet of the abatement device. Molded high surface area heaters maximize contact with pipes and are designed to maintain them at a constant temperature between ambient and 180°C, recognizing that when choosing the temperature set point, knowledge of what process materials and byproducts are going to be in the exhaust pipe is invaluable.

Chambers said this approach is also superior to other heating methods using custom heater mats with integral insulation. “The difficulty you encounter with those kinds of systems is that the heater mat and jacket tend to be custom-designed to suit the particular installation. You spend a lot of time designing stuff, placing orders and waiting for it to be manufactured. Once it is manufactured and installed, there’s no flexibility. If you change the configuration of the exhaust pipe, you’ve got to go buy a whole set of new pipeline heating components,” he said.

With the Edwards SMART TMS approach, heater mats are provided separately from the insulation. “The heater mats are provided in standard lengths and as shaped components too, for elbows, valves, T-pieces and so on. You basically assemble the heater mats of sufficient length to heat your pipe from one end to the other. Then, since they’re made from low-particulate material, the insulation jackets can be cut to shape on assembly to fit the exhaust pipe. They’re all basically reusable,” Chambers said.

Success in thermal management goes well beyond mechanical considerations, however. “A lot of the skill and judgment in temperature management of exhaust pipes is knowing what factors you need to take care of to get decent temperature control throughout the system,” Chambers said.

When handling flammable gases, for example, nitrogen is often used to dilute them below their lower flammable limit to make them safe. “Typically, you pour a whole lot of nitrogen dilution gas into your exhaust pipe. The way in which you do that has a very significant impact on the temperature of the gas and the temperature of the exhaust pipe,” Chambers said. “If you’ve heated your exhaust pipe up to a temperature based on the process gases flowing through it and then you flow into it a couple of hundred liters per minute of cold nitrogen, then your heating system is no longer going to be fully effective. You start to run into the kind of condensation problem you were trying to avoid in the first place.”

The Edwards solution to that problem is to employ a system to heat up the nitrogen dilution gas. “Providing a nitrogen heater system as an accompaniment to a temperature management system for the exhaust pipe is sometimes a desirable thing to do,” Chambers added.

SMART TMS includes a sophisticated control system. “In our system, we have a controller which takes care of exhaust pipes on a zone by zone basis. The controller can control nine zones. All of those nine zones may be nine separate pipes. It may be one long pipe with nine zones in it over a long distance,” Chambers said.

The controller has useful operational features such as the ability to set and log different control temperatures and user-defined limits in each zone. If a temperature strays outside the user-defined band, an alert is transmitted from the controller to the process tool, the fab central monitoring system or other fault reporting system, depending on the nature of the fault. Furthermore, recognizing that some processes can cause very hazardous byproduct build-up in cold exhausts, SMART TMS includes a “fail-on” function to ensure that in the event of a component failure or loss of temperature indication a high pipeline temperature is maintained until servicing can be scheduled. In these cases the integrated health-check function provides an alert, while dual safety devices in each heater provide intrinsic safety and protection against thermal runaway.

“In the future, we can imagine the process which is running in the tool can be used to inform the set-up of the sub-fab equipment, the dry pumps or even the temperature management system,” Chambers said. “We’ve come a long way from relatively simple electrical heaters installed on an ad hoc basis to a sophisticated combination of process knowledge, a wide range of heater mats and shaped heaters, very efficient insulation materials and intelligent controllers with data acquisition capability.”

Leti, a CEA Tech institute, today announced it has developed a new on-chip communications system to improve high-performance computing (HPC) that is faster and more energy efficient than current solutions and is compatible with 3D architectures.​

Leti researchers, working in the frame of IRT Nanoelec, boosted computing power and slashed energy consumption by stacking chips on top of each other in a single enclosure, or by placing the chips side by side on a silicon interposer. The chips, which have progressed from demonstrator to fabrication-ready, exchange data via a new communications network that is part of the network on chip (NoC) called 3D-NoC.

3D-NoC technology has been demonstrated with a homogeneous 3D circuit that is comprised of regular tiles assembled using a 4x4x2 NoC. It also features robust and fault-tolerant asynchronous 3D links, and provides 326 MFlit/s @ 0.66 pJ/bit. It was fabricated in a CMOS 65nm technology using 1,980 TSVs in a Face2Back configuration.

This second generation 3D-NoC technology has been integrated in the INTACT circuit developed in the frame of IRT Nanoelec. The 3D circuit, currently in foundry, combines a series of chiplets fabricated at the FDSOI 28nm node and co-integrated on a 65nm CMOS interposer.  The active interposer embeds several lower-cost functions, such as communication through the NoC and system I/Os, power conversion, design for testability and integrated passive components.

Moreover, the chip requires 20 times less energy for data transmission than chips placed on an electronic circuit board. This new IP is compatible with standard remote direct-memory-access-type software used for data transmission and has likely industrial uses in virtual-server migration applications.

“The steady rise in the number of applications that require high-performance computing creates a demand for new hardware-plus-software communications solutions that improve both performance and energy consumption,” said Denis Dutoit, Leti strategic marketing manager. “This new technology brick makes it possible to transfer data between processors via a network-on-chip delivering more powerful, energy-efficient computing.”

Leti will host its annual workshop during Semicon West on “Sensing your Future with Leti” at 5 p.m., July 12, at the W Hotel.  Registration is here.

Leti scientists will be available at booth #2028 in the South Hall during Semicon West to discuss this announcement and other recent research developments and initiatives.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the EVG50 automated metrology system. Designed to support the increasingly stringent manufacturing requirements for advanced packaging, MEMS and photonics applications, the EVG50 performs high-resolution non-destructive multi-layer thickness and topography measurement, as well as void detection, in bonded wafer stacks and in photoresists used in optical lithography. The system measures layers down to two microns in thickness, can inspect up to one million points, and achieves throughputs of up to 55 300-mm wafers per hour. This combination of extremely high resolution and high throughput provides cost-efficient full-wafer inspection that enables device manufacturers to improve their wafer bonding and lithography processes, as well as achieve higher yields.

The EVG 50 Automated Metrology System from EV Group performs high-throughput, high-resolution measurements of critical wafer bonding and lithography process parameters.

The EVG 50 Automated Metrology System from EV Group performs high-throughput, high-resolution measurements of critical wafer bonding and lithography process parameters.

Dr. Thomas Glinsner, corporate technology director at EV Group, noted, “The semiconductor industry is witnessing a trend toward total control and monitoring of all production processes. Mid-end-of-line and back-end packaging processes face tighter process constraints at levels previously seen only in front-end-of-line wafer processing. This is creating an urgent need for highly accurate in-line metrology that can provide critical process data quickly and cost-effectively. The EVG50 is an important addition to our suite of metrology solutions that achieves these goals at speeds and resolutions that far surpass those of competitive systems.”

Building on a legacy of widely adopted metrology solutions

The standalone EVG50 system was developed based on the company’s existing in-line metrology module (IMM), which is available as an option in EVG’s line of 300-mm process equipment and has been widely implemented in high-volume manufacturing. The EVG50 complements the company’s versatile EVG40NT measurement system, which is the industry standard for bond overlay inspection, to meet increased customer demand for full-area layer thickness and topography measurement in critical applications. The EVG50’s high throughput and unparalleled accuracy and repeatability, even at ultra-high resolutions, enables cost-effective, 100-percent inspection of production wafers, resulting in improved process control.

The EVG50’s versatility allows it to measure coating thickness for lithography as well as wafer bow and warpage, and make void inspections for a bonded wafer stack on the same system, while its low-contact edge handling enables particle-free, full-area wafer inspection. Another key benefit of the EVG50 is its flexibility. Leveraging a multi-sensor measurement mount, the system can be customized for different thickness ranges and substrates to address a wide variety of customer requirements. Its self-calibration capability also allows for better system reproducibility and productive uptime.

Media, analysts and potential customers interested in learning more about EVG’s suite of metrology solutions, including the EVG50, are invited to visit the company’s booth #1017 in the South Hall of the Moscone Convention Center in San Francisco, Calif., at the SEMICON West show on July 12-14.

Applied Materials, Inc. today announced its next-generation e-beam inspection system is delivering the highest resolution and image quality at the fastest throughput to leading foundry, logic, DRAM and 3D NAND customers as they move to advanced nodes.

The Applied PROVision– system is the industry’s most advanced e-beam inspection tool, incorporating innovations based on more than 20 years of leading expertise in e-beam technology for review and metrology. It is the only e-beam hotspot inspection tool offering down to 1nm resolution, allowing customers to detect the most challenging “killer” defects that other technologies cannot find, and to monitor process marginality to rapidly resolve ramp issues and achieve higher yields.

“The PROVision system is the latest addition to our e-beam portfolio, and is a key part of Applied’s growth strategy,” said Bob Perlmutter, vice president and general manager of Applied’s Imaging and Process Control Group. “Our differentiated e-beam column technology is the best in the industry and when coupled with our customers’ new inspection methodologies, enables the PROVision system to go beyond R&D use and into production environments.”

The PROVision system is gaining momentum with already more than a dozen shipments, including repeat orders from a leading foundry and a major memory manufacturer. Additional systems are scheduled for shipment to existing and new customers in the second half of 2016.

“The PROVision system’s unique combination of high resolution and massive sampling has helped accelerate time to solution and time to market for our advanced nodes,” said Dr. Oh-Jang Kwon, SK hynix R&D EBI Group.

Offering 3x faster throughput over existing e-beam hotspot inspection tools, the PROVision system ensures accurate process characterization, prediction and detection of performance- and yield-limiting defects throughout the fab product life cycle. The PROVision system complements Applied’s e-beam metrology and review products as well as the optical patterned wafer inspection product line.

071116 Applied PROVision system

Imec, a nanoelectronics research center, today announced the opening of imec Florida, a new entity focusing on photonics and high-speed electronics IC design based in Osceola, Florida. Imec Florida kicked off with the signing of a collaboration agreement with the University of Central Florida (UCF), Osceola County and the International Consortium for Advanced Manufacturing Research (ICAMR), that is setting up fab facilities for the development and production of highly innovative III-V-on-silicon solutions for a broad range of applications including sensors, high-speed electronics and photonics.

Imec Florida will be established as a design center facilitating the collaboration between imec’s headquarters, based in Leuven, Belgium, and U.S.-based semiconductor and system companies, universities, and research institutes. Imec Florida’s initial focus will be the R&D of high speed electronics and photonics solutions, starting with an offering of IC design research for a broad set of semiconductor-based solutions such as THz and LIDAR sensors, imagers, and a broad range of sensors.  It will also provide IC design needs that will be driving the ICAMR manufacturing research. Through imec Florida, imec’s design, prototyping and low-volume production service – also named imec IC-link – will provide the US market low-cost access to advanced foundry services, helping entrepreneurs to (industry and academia) design innovative products and get them to market.

Funding for imec Florida will come from Osceola County, and the University of Central Florida. The new center will attract top talent through future strategic partnerships, with the aim to employ about 10 scientists and engineers by the end of the year and increase to 100 researchers in the next five years. Heading up the facility as General Manager will be imec’s Vice President Bert Gyselinckx who previously served as general manager at imec in Eindhoven, the Netherlands and helped to co-invent many technologies deployed by innovative semiconductor and consumer electronics companies.

“As the U.S. semiconductor market continues to strengthen with semiconductor manufacturing, equipment, materials and system innovation, we are extremely pleased to collaborate with partner organizations in Florida and see Osceola County in the Orlando region as an interesting location to drive the next phase of imec’s growth and innovation,” stated Luc Van den hove, president and CEO of imec. “Together with industrial and academic partners, we want to develop sustainable solutions and technology to accelerate innovation and stimulate economic growth within Osceola County and the State of Florida.”

“Imec’s international prestige gives us the opportunity to leverage its standing in a field that is growing exponentially in order to recruit more partners and funding for our work at the new Design Center and the Florida Advanced Manufacturing Research Center,” said Osceola County Commission Chairwoman Viviana Janer. “The relationships and people that imec brings to our operation are tangible ways that Osceola County’s 5-year, $15 million investment will be more than re-paid. It’s important to realize that the new Design Center is going to capture the attention of everyone in this field, thereby ensuring maximum utilization and value of the FAMRC.”

“The imec Design Center is the funnel that will fill ICAMR with high-value manufacturing opportunities and we will work closely with them to make sure our capabilities tightly align with their technology direction, said ICAMR CEO Chester Kennedy.  “This partnership is poised to shine the global high-tech spotlight on Central Florida.”

On July 11, 2016, imec will introduce imec Florida to the semiconductor industry at its annual Imec Technology Forum (ITF) USA, a half-day conference in San Francisco Calif., at the Marriott Marquis. ITF USA is part of imec’s prestigious worldwide ITF events, organized in conjunction with SEMICON West and supported by SEMI. With the theme ‘Towards the Ultimate System’, imec’s highly acclaimed speakers and industrial keynote speakers will look at the co-optimization of design and new technology, and how technology innovation can deliver the right building blocks to build these systems.

Gigaphoton Inc., a manufacturer of light sources used in lithography, has announced success in achieving 250W light output at 4.0% conversion efficiency with a Laser-Produced Plasma (LPP) light source prototype for EUV scanners, which the company is currently engaged in developing. At this output level, the light sources can be used in high-volume manufacturing of state-of-the-art semiconductors. The company also announced its success in achieving 119 hours of continuous operation at over 130W in testing.

This result was achieved via the culmination of a number of efforts that the company has continued to develop, including the sub 20 μm micro droplet supply technology, the combination of solid state pre-pulse and CO2 main pulse lasers, improvements in energy control technology, and magnetic field enabled debris mitigation technology.

Gigaphoton has also launched operation of a high-power EUV light source verifier designed for use in a semiconductor high-volume manufacturing environment, and is committed to continuing the development of EUV light sources with high operational rates and reliability in an aim to facilitate their implementation in the high-volume manufacturing of semiconductors.

Hakaru Mizoguchi, Vice President and CTO of Gigaphoton says, “Our success in achieving 250W output at 4.0% conversion efficiency serves to demonstrate how very close we are to perfecting an EUV light source that will achieve the high output rates, while delivering stable operation at low running costs, which the semiconductor manufacturers have long waited for. We are confident that Gigaphoton’s advanced technological capabilities and development efforts aimed at high-volume manufacturing will ultimately produce ground breaking results by accelerating the development of EUV scanners for mass production, expediting the implementation of EUV scanners as the next generation of technology in lithography, contributing to overall development of the semiconductor industry, and accelerating the realization of an IoT based society.

*This project utilizes results from the New Energy and Industrial Technology Development Organization (NEDO) grant program.

SUSS MicroTec, a supplier of equipment and process solutions for the semiconductor industry and related markets, announced the launch of the MA/BA Gen4 series today. The new generation of SUSS MicroTec’s semi-automated Mask and Bond Aligners extends its capabilities by major improvements in alignment accuracy, ergonomic design and further reduced cost of ownership. With the launch of the fourth generation, SUSS MicroTec introduces a new platform system. The two platform types are configured differently and consist of the MA/BA Gen4 for standard processes and the MA/BA Gen4 Pro series for advanced high-end processes. By moving to this new platform concept, SUSS MicroTec further optimizes the Mask Aligner product portfolio to better align with customer requirements.

Main application of SUSS MicroTec’s MA/BA Gen4 series is full-field lithography in Academia, MEMS, 3D Integration and the Compound Semiconductor market. It furthermore handles processes like bond alignment, fusion bonding and SMILE imprint. In addition to standard wafer processing the MA/BA Gen4 series reliably processes delicate substrates, such as fragile, warped or uneven surfaced wafers.

“Our new manual Mask Aligner series sets a high benchmark regarding cost efficiency, user friendliness and leading edge process results” said Dr. Per-Ove Hansson, CEO SUSS MicroTec. “With this new platform concept, we further align with different customer requirements – the MA/BA Gen4 for standard lithography processes or the leading edge MA/BA Gen4 Pro for small-series production and more demanding solutions, e.g. our Soft Conformal Imprint Lithography (SCIL) solution.”

Scientists at Hokkaido University have developed a device that employs both magnetic and electronic signals, which could provide twice the storage capacity of conventional memory devices, such as USB flash drives.

Using two forms of strontium cobalt oxide with different oxygen content, the device can be switched from an insulating/non-magnet state to a metallic/magnet state simultaneously by electrochemical oxidation/reduction reaction at room temperature in air. Credit: Hiromichi OHTA, Hokkaido University

Using two forms of strontium cobalt oxide with different oxygen content, the device can be switched from an insulating/non-magnet state to a metallic/magnet state simultaneously by electrochemical oxidation/reduction reaction at room temperature in air. Credit: Hiromichi OHTA, Hokkaido University

Conventional USB flash drives are electronic data storage devices. They store information by using millions of small gates that process information into “words” consisting of various combinations of the numbers 0 and 1.

A team of scientists at Hokkaido University’s Research Institute for Electronic Science investigated the possibility of using a magnetic signal along with the electronic signal to allow double the storage capacity in these “multiplex writing/reading” devices. In addition to the binary 0/1 method of storing information, this would add an A/B store for the information as well. To do this would require finding a material that can switch back and forth from a magnet to a non-magnet state.

Using two forms of strontium cobalt oxide with different oxygen content, the device can be switched from an insulating/non-magnet state to a metallic/magnet state simultaneously by electrochemical oxidation/reduction reaction at room temperature in air. The use of magnetic signal along with electronic signal Using two forms of strontium cobalt oxide with different oxygen content, the device can be switched from an insulating/non-magnet state to a metallic/magnet state simultaneously by electrochemical oxidation/reduction reaction at room temperature in air. [copyright: Hiromichi OHTA, Hokkaido University]

The team investigated two forms of strontium cobalt oxide (SrCoOx): one is an insulating non-magnet while the other is a metal magnet. By changing the oxygen content in this compound, the team could cause it to switch between the two forms. However, the two methods currently available to do this have big drawbacks. One method requires using a high temperature heat treatment. This would make it impossible to use in devices that work at room temperature, such as your mobile phone. The other method involves using a dangerous alkaline solution. This would require a device that is sealed so that the solution does not leak. This method is difficult to miniaturize and is thus not suitable for information storage devices.

The team developed a new method to use strontium cobalt oxide safely at room temperature in air. They applied a sodium tantalate thin film, which can be used at room temperature without leaking alkaline solution, over layers of strontium cobalt oxide. When a three-volt current was applied (or about one-seventh of the voltage required in currently available USB flash drives), the insulating form of SrCoO2.5 reversibly switched to its metal magnet form, SrCoO3, in three seconds. By comparison, current devices can store information in 0.01 seconds. Making the device smaller would shorten the time needed for the compound to switch between an insulator and a magnet, the researchers say. This would allow the storage of an even larger number of photos and videos in mobile phones, for example.

In collaboration with the National Institute of Information and Communications Technology (NICT), Associate Professor Hiroyuki Ito and Professor Kazuya Masu, et al., of the Tokyo Institute of Technology, developed a new algorithm and circuit technology allowing high-frequency piezoelectric resonators to be used for phase locked loops (PLL). It was confirmed that these operate with low noise and have an excellent Figure of Merit (FoM) compared to conventional PLLs.

This technology allows high-frequency piezoelectric resonators to be used in place of crystal oscillators which was a problem for realizing compact and low-cost radio modules. This greatly contributes to the creation of compact, low-cost, high-speed radio communication systems for the IoT age. High-frequency piezoelectric resonators are compact, can be integrated, have an excellent Q value, and oscillators that use these have excellent jitter performance. High-frequency piezoelectric resonators had greater issues with resonance frequency variance and temperature dependability compared to crystal resonators. However, these issues were resolved by the development of a PLL that uses a channel adjustment technique, which is a new algorithm.

A prototype was fabricated by a silicon CMOS process with a minimum line width of 65 nm, and a maximum frequency output of approximately 9 GHz was achieved with a phase fluctuation of only 180 femtoseconds. Power consumption was 12.7 mW. This performance is equivalent to a PLL Figure of Merit (FoM) of -244 dB, and it has the world’s top-class performance as a fractional-N PLL. This can contribute to the realization of compact, low-cost, high-speed radio communication systems.

The study results will be announced in local time June 17 in “The 2016 Symposium on VLSI Circuits” to be held in Hawaii from June 14.

FEI announced today the release of three new tools for process control and defect/failure analysis in advanced semiconductor manufacturing. Two of the tools are specifically targeted at the 7nm node, and all are designed to allow manufacturers to address critical production issues with industry-leading time-to-data, throughput and low cost-per-sample.

“Perhaps more than any other industry, time is money in advanced semiconductor manufacturing,” said Rob Krueger, vice president and general manager of FEI’s Semiconductor Business. “The time required to analyze a sample affects the cost-per-sample directly, but even more importantly, the time required to answer critical production questions can reduce losses and increase production of the entire process. These new tools are the first on the market to allow fast, automated analysis of critical structures that are 7nm and smaller, enabling manufacturers to develop and scale new processes faster, and get new products to market sooner and more profitably than their competitors.”

The Helios G4 DualBeam EXL is a flexible, full-wafer, in-lab or in-fab DualBeam (focused ion beam/scanning electron microscope – FIB/SEM) system. In addition to performing the full range of sectioning, imaging and analyzing functions typical of DualBeam applications in semiconductor manufacturing, it is the only commercially-available full-wafer system in the market today capable of preparing transmission electron microscope (TEM) samples as thin as 7nm. The new Phoenix FIB column and monochromated Elstar SEM column deliver more precise milling with less surface damage and higher resolution imaging. Automation greatly reduces the difficulty, while also improving the speed and reproducibility of the sample preparation process.

The Metrios DX TEM incorporates new high-speed X-ray compositional analysis in conjunction with fully-automated workflows to improve defect analysis throughput by up to 50 percent. An automated aberration corrector improves low-voltage operation to minimize beam damage in ultrathin samples without sacrificing imaging resolution. Automated connectivity to upstream preparation tools minimizes operator interaction with the sample and improves data integrity. The Metrios DX is the only commercially-available fully-automated TEM in the market with the resolution required for process control and root cause analysis at the 7nm node.

The ExSolve 2 WTP is a dedicated, automated full-wafer DualBeam TEM sample preparation system capable of creating thin samples for 10nm and 14nm processes. This second generation ExSolve offers a 40 percent improvement in sample thickness, 50 percent better placement accuracy relative to its predecessor, while delivering  25 percent reduction in capex relative semi-automated/manual techniques. Automated sample preparation with ExSolve is two to three times faster than manual or small DualBeam procedures. The new ExSolve also adds semi-automated defect analysis capability for certain surface defects.