Tag Archives: letter-wafer-tech

Researchers at the Energy Department’s National Renewable Energy Laboratory (NREL) discovered single-walled carbon nanotube semiconductors could be favorable for photovoltaic systems because they can potentially convert sunlight to electricity or fuels without losing much energy.

The research builds on the Nobel Prize-winning work of Rudolph Marcus, who developed a fundamental tenet of physical chemistry that explains the rate at which an electron can move from one chemical to another. The Marcus formulation, however, has rarely been used to study photoinduced electron transfer for emerging organic semiconductors such as single-walled carbon nanotubes (SWCNT) that can be used in organic PV devices.

In organic PV devices, after a photon is absorbed, charges (electrons and holes) generally need to be separated across an interface so that they can live long enough to be collected as electrical current. The electron transfer event that produces these separated charges comes with a potential energy loss as the molecules involved have to structurally reorganize their bonds. This loss is called reorganization energy, but NREL researchers found little energy was lost when pairing SWCNT semiconductors with fullerene molecules.

“What we find in our study is this particular system — nanotubes with fullerenes — have an exceptionally low reorganization energy and the nanotubes themselves probably have very, very low reorganization energy,” said Jeffrey Blackburn, a senior scientist at NREL and co-author of the paper “Tuning the driving force for exciton dissociation in single-walled carbon nanotube heterojunctions.”

The paper appears in the new issue of the journal Nature Chemistry. Its other co-authors are Rachelle Ihly, Kevin Mistry, Andrew Ferguson, Obadiah Reid, and Garry Rumbles from NREL, and Olga Boltalina, Tyler Clikeman, Bryon Larson, and Steven Strauss from Colorado State University.

Organic PV devices involve an interface between a donor and an acceptor. In this case, the SWCNT served as the donor, as it donated an electron to the acceptor (here, the fullerene). The NREL researchers strategically partnered with colleagues at Colorado State University to take advantage of expertise at each institution in producing donors and acceptors with well-defined and highly tunable energy levels: semiconducting SWCNT donors at NREL and fullerene acceptors at CSU. This partnership enabled NREL’s scientists to determine that the electron transfer event didn’t come with a large energy loss associated with reorganization, meaning solar energy can be harvested more efficiently. For this reason, SWCNT semiconductors could be favorable for PV applications.

Researchers at the Energy Department’s National Renewable Energy Laboratory (NREL) have uncovered a way to overcome a principal obstacle in using two-dimensional (2D) semiconductors in electronic and optoelectronic devices.

2D semiconductors such as molybdenum disulfide are only a few layers thick and are considered promising candidates for next-generation devices. Scientists first must overcome limitations imposed by a large and tunable Schottky barrier between the semiconductor and a metal contact. The barrier, at the metal/semiconductor junction, creates an obstacle for the flow of electrons or holes through the semiconductor.

The NREL team discovered that the height of the Schottky barrier can be adjusted-or even made to vanish-by using certain 2D metals as electrodes. Such adjustments are not possible with conventional three-dimensional metals because of a strong Fermi level pinning (FLP) effect occurring at the junction of metal and semiconductor, due to electronic states in the semiconductor band gap that are induced by the metal. Increasing the flow of electrons or holes through a semiconductor reduces power losses and improves the device performance.

The NREL theorists considered a family of 2D metals that could bind with the 2D semiconductors through van der Waals interaction. Because this interaction is relatively weak, the metal-induced gap states are suppressed and the FLP effect is negligible. This means that the Schottky barrier becomes highly tunable. By selecting an appropriate 2D metal/2D semiconductor pair, one can reduce the barrier to almost zero (such as H-NbS2/WSe2 for hole conduction).

They noted that using a 2D metal as an electrode would also prove useful for integrating into transparent and flexible electronics because the 2D metal is also transparent and flexible. They also noted that the junction of 2D metal and 2D semiconductor is atomically flat and can have fewer defects, which would reduce carrier scattering and recombination.

The work by Yuanyue Liu, Paul Stradins, and Su-Huai Wei, “Van der Waals metal-semiconductor junction: weak Fermi level pinning enables effective tuning of Schottky barrier,” appears in the new issue of Science Advances.

The trio of researchers predicts that hexagonal phase of niobium disulfide (NbS2) is the most promising for hole injection into a 2D semiconductor, and heavily nitrogen-doped graphene can enable efficient electron injection.

Spintronic majority gates could revolutionize circuit design. They will completely change the paradigm – both at device and circuit level – in how to approach scaling.

BY IULIANA RADU and AARON THEAN, imec, Leuven, Belgium

Spin logic devices are an emerging beyond-CMOS technology that may push beyond Moore’s law, enabling functional scaling beyond the 5nm technology node. These exotic devices lend themselves to majority logic operation, which differs in many ways from the classical NAND-based operation. Imec looks into spin torque majority gates and spin wave majority gates, two concepts that completely change the way we think of computing and scaling. As shown at the 2015 IEDM conference, circuit simulations with these majority gates outperform equivalent CMOS circuits in terms of area and power consumption. Meanwhile, experimental work has been started to learn about the materials, about the devices behavior and about the technology challenges that lie ahead.

Spintronic majority gates, an efficient way to build circuits

As we approach 5nm logic technology in 2020, CMOS device density scaling faces serious challenges due to escalating process costs and parasitics. This inevitably leads to questions of sustainability of traditional Moore’s law where cost and data processing supposedly scale favorably with increasing device density. This begs the question: are there specialized devices and computational paradigms out there that break away from these fundamental trappings of CMOS scaling? The search is on and novel beyond-CMOS devices are being intensively studied.

This varied class of devices may enhance and complement the functionality of CMOS circuits. Among the promising concepts are spintronic devices (FIGURE 1), which exploit the electron’s spin, a quantum attribute that relates to magnetism, rather than its charge to perform logic operations. Spin logic devices promise to be non-volatile and lend themselves to ultralow-energy operation. But one of their biggest trumps is the ability to build majority gates, ‘democratic’ devices that return true if more than 50% of their inputs are true. For example, if two inputs are in a true state and a third one is in a false state, the expected state at the output is true. With these majority gates, logic AND and OR operations can be emulated. Also, this concept of majority logic operation differs in many ways from the classical NAND-based logic, where an output is false only if all its inputs are true. It presents a concept shift that completely changes the way we synthesize circuits. But the advantages are huge: majority gates enable arithmetic circuits that are much more compact and energy-efficient than conventional NAND or XOR gate-based circuits. For example, while a one-bit adder in CMOS technology requires about 25 transistors, the equivalent wave computing circuit only requires 5 transducers and 4 waveguides to perform the same operation.

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Two ways of encoding information

Spintronic majority gates can come in several flavors, differing in the way the information is encoded and processed in the device, and in the way transduction from the charge domain to the spin (magnetism) domain is executed. At imec, two concepts are studied extensively: the spin torque majority gate (STMG) and the spin wave majority gate (SWMG).

In a STMG, the information is encoded in magnetic domain walls. Domain walls are interfaces that separate regions with different magnetization direction. The majority gate itself consists of a cross-shaped free layer that is common to 4 magnetic tunnel junctions (3 inputs, 1 output). The magnetization direction of the 3 ‘input’ free layers is switched using spin transfer torque, provided by a current through each of the magnetic tunnel junctions. Based on quantum interactions between electrons known as exchange, the domain walls propagate and interact, and the majority magnetization direction wins. The output state is measured via tunneling magnetoresistance.

In a SWMG, the computation principle is based on the interference of spin waves. The information can be encoded either in the amplitude or in the phase of the waves. Spin waves are low-energy collective excita- tions in magnetic materials. They can be generated by a so-called magneto-electric cell, which converts voltage into a spin wave. Key elements of this cell are a piezoelectric layer (that converts voltage into strain) and a magnetostrictive layer (in which the strain produces a change in magnetization or magne- tization anisotropy). In its turn, the change in magne- tization can generate a spin wave in a magnetic spin wave bus. The same cell is used to read the output state of the majority gate (FIGURE 2).

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Both concepts have been studied intensively, and approaches of how to handle the computation have been proposed. An experimental demonstration is however still missing. At imec, we have enlarged our basic understanding of both STMG and SWMG and used simulations to validate device functioning. We have compared the two types of majority gates against equivalent circuits in 10nm FinFET CMOS technology. And we present our first experimental results, and highlight the main challenges for both concepts.

Spin torque majority gate – compact and technology friendly

We used micromagnetic simulations to validate the functioning of the STMG and identify its operating conditions. For this majority gate, the switching of the magnetization state is current controlled. If the applied current or the pulse length are not enough, the output fails to switch. Even if the applied current pulses provide enough energy to switch, other failure modes can appear. For example, the domain walls that are being formed can become ‘stuck’ at the crossing of the device. This happens when the width of the cross exceeds a certain value, typically in the 15-20nm range. This makes these devices difficult to demonstrate experimentally as it requires patterning and etching to small size and tight pitch between the magnetic tunnel junctions. However, this initial impediment holds great promise for further device scaling. A major advantage of this majority gate is the use of technology friendly materials, compa- rable to the materials used in magnetic memories.

We have benchmarked the device against equivalent 10nm CMOS circuits by comparing key metrics of area, power and delay. On average, the STMG circuits have about 10x smaller area, and provide a means for further scaling. However, being current controlled, the STMG circuits have a longer delay, making them less efficient than equivalent CMOS circuits. Further advances in materials stacks are needed to improve their performance, comparable to those needed in general for magnetic memory.

At imec, we are currently building the first STMG devices on 300mm wafers. Particular attention is paid to the magnetic tunnel junction pillar etch development (FIGURE 3).

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Spin wave majority gate – compact, ultralow-power but challenging materials

We used micromagnetic simulations to model the spin wave propagation in SWMGs and to simulate the magnetic behavior of the magneto-electric cell that converts the applied voltage into a spin wave. This cell is a critical component for the device functionality. We mapped out the parameter space where the magneto-electric cell is expected to work optimally and used these parameter ranges as input for circuit synthesis. Building magneto- electric cells experimentally is very challenging as the materials to be used are not typically used in standard fabs and cleanrooms. For this reason, and to help choose the right materials, we have performed circuit synthesis and benchmarked them against CMOS. Based on materials parameters extracted from these simulations we have chosen a starting set of materials for our experiments.

One of the questions to be answered is how piezoelectrics behave at very high frequencies (gigahertz range) as needed for logic devices. Piezoelectric materials are being used in many applications, where they typically operate at low frequencies (up to hundreds of kHz). At imec, we started first experiments to grow piezoelectric materials in a thin film and to learn how these materials behave in the high frequency domain. And although more experiments are needed to improve the performance and map out the reliability behavior, our preliminary results are very encouraging. An important drawback of the spin wave technology is that the required materials (both the magnetostrictive and the piezoelectric materials) are very different from standard CMOS materials (FIGURE 4).

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The spin wave technology was also benchmarked against CMOS circuits. The spin wave circuits take on average 3.5 times less area and about 400 times lower power than their CMOS counterparts. However, the spin wave circuits are on average 12 times slower, mainly because of the large switching delay of the magneto-electric cell. SWMGs may therefore be used for ultralow-power applications, where latency is a secondary consideration (FIGURE 5).

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Building arithmetic circuits on top of CMOS

Spintronic majority gates could revolutionize circuit design. They will completely change the paradigm – both at device and circuit level – in how to approach scaling. In the future, more experimental work is planned to learn about the new materials required, to validate circuit assessment, and to finally demonstrate functional devices.

Once these technologies have become more mature, we can start thinking of multi-device architectures that combine CMOS-based and spin logic devices. An interesting approach is to stack, on top of CMOS technology, arithmetic circuits made of spintronic majority gates. The high-performance functions could be executed by the CMOS-based devices and the ultralow-power functions by the spin logic arithmetic circuits. So, rather than replacing Si CMOS based transistors in the future, this beyond-CMOS technology is intended to enhance and complement the functionality of CMOS-based devices.

Spintronics belongs to the beyond-CMOS segment, where we look into new materials and device architectures, and even into new computing paradigms and circuits. Beyond-CMOS research is part of imec’s multiple roadmap scenario that is built around 3 pillars: Si extension, beyond Si and beyond CMOS. Each of these segments has its own mission and approach to enabling scaling. And each of the new technologies will bring in enabling modules and devices that will serve the application diversity in the new era of electronics: the internet of things. And the results will support the quest of the semiconductor industry to find solutions that enable continual functional scaling of cost and energy per bit by departing from the familiar CMOS scaling.

Suggested additional reading

1. Spintronic majority gates, I. P. Radu et al., IEDM 2015 (https://www.researchgate.net/publication/286882975_ Spintronic_Majority_Gates)

2. Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS, O. Zografos et al., Proceedings of the 15th International IEEE Conference on Nanotechnology (NANO), 2015(http://infoscience.epfl.ch/ record/211004)

3. “With our multiple roadmap scenario, we anticipate the appli- cation diversity in the new Era of Electronics”, imec annual overview 2015, vision by Aaron Thean (click on the name of Aaron at http://magazine.imec.be/data/80/reader/reader. html?t=1452505511353#!preferred/1/package/80/pub/86/ page/8)

IULIANA RADU is a program manager and AARON THEAN is the Vice President of Process Technologies and the Director of the Logic Devices Research at imec, Leuven, Belgium.

This article originally appeared on EECatalog.com.

By Venetia Espinoza, BrightVolt

Are the power solutions the IoT needs arriving quickly enough?

The massive game-changing potential of the Internet of Things (IoT) connected devices has been limited by a lack of effective power solutions. The solid-state thin film battery market is forecasted to reach $1.3 bil­lion worldwide by 2021 as published by Custom Market Insights. Fueling this growth is the rise of IoT—wear­ables, medical devices and sensors. Traditional battery technologies simply cannot provide the new features and designs that these new applications demand.

However, arriving on the market are thin-film, flexible batteries which are ultra-thin, flexible, rollable, stretch­able and can withstand high temperatures.

Many applications are still emerging, and their require­ments are evolving fast. Because target specs are also very diverse, each with unique requirements for power, thinness, cost, safety, shelf life, reliability, and flex­ibility, a customized power source makes sense.

BrightVolt is one company tackling the demand for small powered solutions.

Figure 1: Traditional battery technologies are giving way to new designs, which can reduce design complexity. (Courtesy BrightVolt)

Low power/long battery life—As IoT infrastructure becomes ubiquitous, many use-cases require designing and building low power and small form factor batteries, both primary and rechargeable. BrightVolt’s Flexion™ batteries have 3.0V, multiple capacity options such as 10, 14, 20, 25mAh and varied tab con­figurations such as extended tab, terminal support, terminal support with ACF. They also have attachment options such as ultrasonic welding, soldering, conductive epoxy and conductive film and a shelf life of 3-5+ years.

Customized—Battery designs are available that are as thin as 0.37mm. For example, BrightVolt Flexion batteries were designed to operate continuously over a wide temperature range (-10 ºC to +60 ºC). They utilize a patented solid polymer electrolyte and contain no volatile liquids or gelling agents. Self-connecting battery terminals using anisotropic conductive film. BrightVolt can custom-build the size, shape, power, capacity, tab configurations and attachment options that are needed for these diverse requirements.

Scalable Manufacturing—BrightVolt has already shipped millions of units. Scalability is our key differentiator. We can take a solution from prototype to full production and anything in between. Our enduring quality, durability, and built-in intelligence is what makes us the best choice for custom product designs.

Safe—It is now possible to find batteries that are non-toxic, non-corrosive and environ­mentally friendly. It’s also important to choose an Inherently safe design that reduces the need for additional battery safety circuitry. Polymer matrix electrolyte provides outstanding thermal stability with no volatile liquids or gels.

Medical Miracles and Thin Batteries

Nanotechnology itself dates back to the 1980s, when U.S. engineer Eric Drexler coined it. Today, nanotechnology and tiny batteries are changing the medical device industry.

Applicable medical uses include the ability to use small form batteries to power the circuitry associated wit skin-based monitoring devices that can detect the glucose levels, for example. Trans­dermal drug delivery and patches could change how injectable drugs are delivered in a more effective time-released manner through a battery-powered patch.

Additionally, the combination of a nanosensor used in conjunction with a smartphone could be used to track auto­immune diseases and cancer. It could also be an effective screening tool for rejection in patients with organ transplants.

Sensors, Smart Packaging and the IoT

It is anticipated that the temperature monitoring market will reach over $3.2 billion by 2020. Smart sensor labels answer the needs for numerous indus­tries, particularly perishable goods. These printed electronics devices and labeling enable the IoT to reduce waste and improve consumer safety.

This technology allows pharmaceutical companies to keep temperature-sensitive products safe and effective, while pre­venting the unnecessary ruin of usable products. Retailers who use temperature-monitoring labels during shipment of produce and other food products as well as cosmetics and off-the-shelf healthcare items will have immediate insight with regards to both shelf life and food safety.

Some of the most ubiquitous wearables are fitness trackers like FitBit and Jaw­bone that hit the market like wildfire in 2013. 1 in 5 Americans today wear this technology to track their activity levels, sleep and more. Wearables will continue to evolve in size, usability, form factors and diverse power needs.

Assisted living and eldercare is another compelling and demanding wearable technology market. Wearable sensors for this market pose massive potential in generating big data for IoT, with a great applicability to biomedicine and ‘ambient assisted living’ (AAL). ‘Ambient intelligence’ in eldercare is being sensi­tive and responsive to the presence of people. Recent advancements in several technological areas have helped the vision of AAL to become a reality. These tech­nologies include of course smart homes, assistive robotics, and, in small form: e-textile, mobile and wearable sensors.

Another significant advancement is detecting common medical issues such as sleep apnea, which used to require an uncomfortable in-clinic sleep study. No more. Today, a patient can wear a device overnight in the privacy of their own home and send the results off to their physician. Other exciting uses include trackers in clothing, interactive toys, games and more.

Embedding Security

Target’s $10 million 2013 class action data breach lawsuit and privacy issue hammered home just how devastating security fraud really is. Since that time, many credit cards are now embedded with an EMV chip but there’s an even better solution emerging. Not only will a small form battery the size of a postage stamp power these new cards, a com­puter chip randomizes the code number about every hour, adding to its security. This renders the card useless to anyone who has written down your card number, expiration date and code. This applica­tion will effectively eliminate ‘card not present’ fraud. Other ultra-thin battery uses in a credit card could allow for a tiny screen on your card itself that displays your balance.

When Apple launched its biometric ID fingerprint reader on its iPhone 5S, many people adjusted quickly to the convenience of the fingerprint password. Building on that same technology, travel documents including drivers’ licenses and passports, as well as vital health information, can be included in one ultra-thin battery-powered, pocket-sized card that fits in your wallet.

Conclusion

By assessing the considerations outlined in this article, a product designer can effectively achieve a small-form factor product able to reliably operate with the right battery. Custom batteries can eliminate design complexities and opti­mize battery use for many applications.

About the Author

Venetia Espinoza is in charge of market­ing at BrightVolt, a worldwide leader in the design, development and scale manufacturing of thin film batteries. She holds more than 25 years of marketing and product experience with premier technology companies. She also served as Vice President and General Manager of Softcard, a joint venture established by industry giants Verizon, AT&T and T-Mobile. She holds an MBA and BS de­gree in Industrial Engineering.

Gigaphoton Inc., a major semiconductor lithography light source manufacturer, announced its new excimer laser brand “GIGANEX” on April 1, 2016.

Gigaphoton has announced they will develop a highly reliable excimer laser, “GIGANEX,” utilizing their considerable technical capabilities acquired by their experience in semiconductor lithography, for use in the fields of FPD production, flexible device processing, semiconductor fabrication, etc. Moving forward, Gigaphoton intends to explore further possibilities in excimer lasers, together with new innovative partners, to provide GIGANEX solutions.

Gigaphoton President and CEO Hitoshi Tomaru explains. “Our company has accumulated experience as a major semiconductor lithography light source manufacturer over more than 15 years, and in fiscal 2016 we are embarking on a new challenge – to expand the range of applications of our lasers into other fields. I expect Gigaphoton’s technology to expand even further and continue to contribute to the industrial world.”

Details of GIGANEX will introduced at SID Display Week, which will be held May 24-26, 2016.

Epitaxy, or growing crystalline film layers that are templated by a crystalline substrate, is a mainstay of manufacturing transistors and semiconductors. If the material in one deposited layer is the same as the material in the next layer, it can be energetically favorable for strong bonds to form between the highly ordered, perfectly matched layers. In contrast, trying to layer dissimilar materials is a great challenge if the crystal lattices don’t match up easily. Then, weak van der Waals forces create attraction but don’t form strong bonds between unlike layers.

In a study led by the Department of Energy’s Oak Ridge National Laboratory, scientists synthesized a stack of atomically thin monolayers of two lattice-mismatched semiconductors. One, gallium selenide, is a “p-type” semiconductor, rich in charge carriers called “holes.” The other, molybdenum diselenide, is an “n-type” semiconductor, rich in electron charge carriers. Where the two semiconductor layers met, they formed an atomically sharp heterostructure called a p-n junction, which generated a photovoltaic response by separating electron-hole pairs that were generated by light. The achievement of creating this atomically thin solar cell, published in Science Advances, shows the promise of synthesizing mismatched layers to enable new families of functional two-dimensional (2D) materials.

The idea of stacking different materials on top of each other isn’t new by itself. In fact, it is the basis for most electronic devices in use today. But such stacking usually only works when the individual materials have crystal lattices that are very similar, i.e., they have a good “lattice match.” This is where this research breaks new ground by growing high-quality layers of very different 2D materials, broadening the number of materials that can be combined and thus creating a wider range of potential atomically thin electronic devices.

“Because the two layers had such a large lattice mismatch between them, it’s very unexpected that they would grow on each other in an orderly way,” said ORNL’s Xufan Li, lead author of the study. “But it worked.”

The group was the first to show that monolayers of two different types of metal chalcogenides–binary compounds of sulfur, selenium or tellurium with a more electropositive element or radical–having such different lattice constants can be grown together to form a perfectly aligned stacking bilayer. “It’s a new, potential building block for energy-efficient optoelectronics,” Li said.

Upon characterizing their new bilayer building block, the researchers found that the two mismatched layers had self-assembled into a repeating long-range atomic order that could be directly visualized by the Moiré patterns they showed in the electron microscope. “We were surprised that these patterns aligned perfectly,” Li said.

Researchers in ORNL’s Functional Hybrid Nanomaterials group, led by David Geohegan, conducted the study with partners at Vanderbilt University, the University of Utah and Beijing Computational Science Research Center.

“These new 2D mismatched layered heterostructures open the door to novel building blocks for optoelectronic applications,” said senior author Kai Xiao of ORNL. “They can allow us to study new physics properties which cannot be discovered with other 2D heterostructures with matched lattices. They offer potential for a wide range of physical phenomena ranging from interfacial magnetism, superconductivity and Hofstadter’s butterfly effect.”

Li first grew a monolayer of molybdenum diselenide, and then grew a layer of gallium selenide on top. This technique, called “van der Waals epitaxy,” is named for the weak attractive forces that hold dissimilar layers together. “With van der Waals epitaxy, despite big lattice mismatches, you can still grow another layer on the first,” Li said. Using scanning transmission electron microscopy, the team characterized the atomic structure of the materials and revealed the formation of Moiré patterns.

The scientists plan to conduct future studies to explore how the material aligns during the growth process and how material composition influences properties beyond the photovoltaic response. The research advances efforts to incorporate 2D materials into devices.

For many years, layering different compounds with similar lattice cell sizes has been widely studied. Different elements have been incorporated into the compounds to produce a wide range of physical properties related to superconductivity, magnetism and thermoelectrics. But layering 2D compounds having dissimilar lattice cell sizes is virtually unexplored territory.

“We’ve opened the door to exploring all types of mismatched heterostructures,” Li said.

The title of the paper is “Two-dimensional GaSe/MoSe2 misfit bilayer heterojunctions by van der Waals epitaxy.”

The 62nd annual IEEE International Electron Devices Meeting (IEDM), to be held at the San Francisco Union Square Hilton hotel December 3 – 7, 2016, has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development.

The paper submission deadline this year is Wednesday, August 10, 2016. This deadline –– about 1½ months later than has been the norm for the IEDM – reduces the time between paper submissions and publication of the cutting-edge research results for which the conference is known. Also new for 2016 is that authors are asked to submit four-page camera-ready abstracts (instead of three pages), which will be published as-is in the proceedings.

Because of the more abbreviated schedule, only a very limited number of late-news papers will be accepted. Authors are asked to submit late-news abstracts announcing only the most recent and noteworthy developments. The late-news submission deadline is September 12, 2016.

“Because microelectronics technology changes so rapidly, it makes sense to shorten the time between when results are achieved and when they are discussed among the industry’s best and brightest who attend IEDM,” said Dr. Martin Giles, IEDM 2016 Publicity Chair and Intel Fellow and Director of Transistor Technology Variation in Intel’s Technology and Manufacturing Group. “This later submission deadline ensures that the freshest and most up-to-date work can be presented at the conference.”

Overall, the 2016 IEDM is seeking increased participation in the areas of power, wearable/Internet of Things (IoT), ultra-high speed, and quantum computing devices, which will be explored in depth in Special Focus Sessions in each area.

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics from industry, academia and government gather to participate in a technical program of more than 220 presentations, along with special luncheon presentations and a variety of panels, special sessions, Short Courses, IEEE/EDS award presentations and other events spotlighting more leading work in more areas of the field than any other conference.

Papers in the following areas are encouraged:

  • Circuit and Device Interaction
  • Characterization, Reliability and Yield
  • Compound Semiconductor and High-Speed Devices
  • Memory Technology
  • Modeling and Simulation
  • Nano Device Technology
  • Optoelectronics, Displays and Imagers
  • Power Devices
  • Process and Manufacturing Technology
  • Sensors, MEMS and BioMEMS

Further information

For more information, interested persons should visit the IEDM 2016 home page at www.ieee-iedm.org.

Nanoelectronics research center imec and Crystal Solar, a pioneer in direct wafer growing technologies for the next generation of solar photovoltaic products, today announced that they have achieved a 22.5 percent cell efficiency (certified by FhG ISE CalLab) with nPERT silicon (Si) solar cells manufactured on 6-inch mono-crystalline epitaxially grown kerfless wafers. Marking an industry first, imec and Crystal Solar have demonstrated the highest efficiency to-date for homojunction solar cells on epitaxially grown silicon wafers, paving the way toward industrialization of this promising technology.

Crystal Solar’s breakthrough manufacturing technology called Direct Gas to Wafer enables direct conversion of feedstock gas to mono crystalline silicon wafers by high throughput epitaxial growth. By skipping the polysilicon, ingoting and the wire-sawing steps altogether, this approach not only results in lowest cost/watt for the wafers but also significantly reduces the capital required to set up a manufacturing plant. Furthermore, this process enables the growth of high quality p-n junctions in-situ which reduces cell making steps while increasing the efficiency.

Imec has adapted its highly efficient nPERT Si solar cell process to align with the properties of Crystal Solar’s kerfless wafers. The 156x156mm2 cells were fabricated on 160 to 180 um thick grown n-type wafers with built-in rear p+ emitter. Imec’s n-PERT process included a selective front surface field realized by laser doping, advanced emitter surface passivation by Al2O3 and Ni/Cu plated contacts. The novel process using all industrially available processing steps resulted in record efficiencies for homojunction large area solar cells of 22.5 percent and a record Voc of 700mV. This high Voc illustrates the high quality of the wafers and the built-in junction.

Jozef Szlufcik, PV Department Director at imec: “We are extremely happy to have achieved such high conversion efficiencies on nPERT solar cells processed from kerfless wafers using imec’s pre-pilot industrial silicon PV manufacturing line. The combination of our advanced cell process and the innovative wafer manufacturing technique of Crystal Solar, is paving the way for manufacturing of highly efficient solar cells at substantially lower cost and will be disruptive for the complete solar manufacturing value chain.”

“We are pleased to see such a high conversion efficiency on our epitaxially grown n-type wafers with built in boron doped junctions,” said T.S. Ravi, CEO of Crystal Solar. “This approach represents a new paradigm in cell manufacturing with its unique ability to bypass significant steps in both wafer and cell manufacturing thereby dramatically reducing the capex and the overall cost per watt.  We expect to achieve >23% efficiencies with IMEC’s PERT technology in the very near future,” Mr. Ravi concluded.

Harnessing the power of the sun and creating light-harvesting or light-sensing devices requires a material that both absorbs light efficiently and converts the energy to highly mobile electrical current. Finding the ideal mix of properties in a single material is a challenge, so scientists have been experimenting with ways to combine different materials to create “hybrids” with enhanced features.

In two just-published papers, scientists from the U.S. Department of Energy’s Brookhaven National Laboratory, Stony Brook University, and the University of Nebraska describe one such approach that combines the excellent light-harvesting properties of quantum dots with the tunable electrical conductivity of a layered tin disulfide semiconductor. The hybrid material exhibited enhanced light-harvesting properties through the absorption of light by the quantum dots and their energy transfer to tin disulfide, both in laboratory tests and when incorporated into electronic devices. The research paves the way for using these materials in optoelectronic applications such as energy-harvesting photovoltaics, light sensors, and light emitting diodes (LEDs).

According to Mircea Cotlet, the physical chemist who led this work at Brookhaven Lab’s Center for Functional Nanomaterials (CFN), a DOE Office of Science User Facility, “Two-dimensional metal dichalcogenides like tin disulfide have some promising properties for solar energy conversion and photodetector applications, including a high surface-to-volume aspect ratio. But no semiconducting material has it all. These materials are very thin and they are poor light absorbers. So we were trying to mix them with other nanomaterials like light-absorbing quantum dots to improve their performance through energy transfer.”

One paper, just published in the journal ACS Nano, describes a fundamental study of the hybrid quantum dot/tin disulfide material by itself. The work analyzes how light excites the quantum dots (made of a cadmium selenide core surrounded by a zinc sulfide shell), which then transfer the absorbed energy to layers of nearby tin disulfide.

“We have come up with an interesting approach to discriminate energy transfer from charge transfer, two common types of interactions promoted by light in such hybrids,” said Prahlad Routh, a graduate student from Stony Brook University working with Cotlet and co-first author of the ACS Nano paper. “We do this using single nanocrystal spectroscopy to look at how individual quantum dots blink when interacting with sheet-like tin disulfide. This straightforward method can assess whether components in such semiconducting hybrids interact either by energy or by charge transfer.”

The researchers found that the rate for non-radiative energy transfer from individual quantum dots to tin disulfide increases with an increasing number of tin disulfide layers. But performance in laboratory tests isn’t enough to prove the merits of potential new materials. So the scientists incorporated the hybrid material into an electronic device, a photo-field-effect-transistor, a type of photon detector commonly used for light sensing applications.

As described in a paper published online March 24 in Applied Physics Letters, the hybrid material dramatically enhanced the performance of the photo-field-effect transistors-resulting in a photocurrent response (conversion of light to electric current) that was 500 percent better than transistors made with the tin disulfide material alone.

“This kind of energy transfer is a key process that enables photosynthesis in nature,” said Chang-Yong Nam, a materials scientist at Center for Functional Nanomaterials and co-corresponding author of the APL paper. “Researchers have been trying to emulate this principle in light-harvesting electrical devices, but it has been difficult particularly for new material systems such as the tin disulfide we studied. Our device demonstrates the performance benefits realized by using both energy transfer processes and new low-dimensional materials.”

Cotlet concludes, “The idea of ‘doping’ two-dimensional layered materials with quantum dots to enhance their light absorbing properties shows promise for designing better solar cells and photodetectors.”

In the world of nano-scale technology, where work is conducted at the atomic level, even the smallest changes can have an enormous impact. And a new discovery by a University of Alberta materials engineering researchers has caught the attention of electronics industry leaders looking for more efficient manufacturing processes.

Triratna Muneshwar, a postdoctoral fellow in the Department of Chemical and Materials Engineering and Ken Cadien, a materials engineering professor, have developed a new method of making thin films–materials that are essential in today’s computers and electronic devices–by adapting current atomic layer deposition techniques.

Atomic layer deposition (ALD) is exactly what the name implies. Thin films are coated with molecule-thin layers of materials like zinc, silicon, nitrogen, and so on. In the manufacturing process, the film is placed inside a small chamber and prepared by being treated with a “sticky” precursor layer. Gasses are then pumped inside, coating and chemically binding to receptors on the precursor layer.

The problem is that some of the molecules coming to rest on top of the precursor layer are so large that they block other receptor points. It’s like five people taking up 10 seats on a bus.

However, Muneshwar observed that those large molecules almost immediately shed ligands that do not connect to the precursor layer, freeing up previously blocked receptors. But by this time, the gas has been pumped out of the chamber and cannot be used a second time. “Although few strategies have been proposed to recycle this unreacted gas, residual impurities within remains a serious concern,” he notes.

Muneshwar wondered if he could create a more dense and uniform layer by pumping gas into the chamber in smaller doses, waiting just a fraction of a second for the ligands to slough off and free up receptors, and then pumping in another small dose of gas.

He developed the idea while working as a PhD under Cadien’s supervision.

“My interest in this came about in a conversation with Dr. Cadien and one of his colleagues who said that precursor costs are a challenge,” said Muneshwar. Then, while attending an international conference in last year, Muneshwar asked industry engineers and researchers about ALD and precursor costs in particular.

“I asked one fellow ‘What if I could cut your precursor costs in half?’ and he realized the impact this would have on their manufacturing processes. Later that day when I ran into him, I was told that he discussed this idea with his boss and they would be very interested in our work,” Muneshwar said.

After returning to campus, Muneshwar began crunching numbers and found that on paper, the pulsed layering concept held promise. After refining his work, Muneshwar had developed a mathematical model that demonstrated the technique would work.

“In a lot of cases you do an experiment and then come up with the formula that explains what happened,” Cadien said. “But Triratna wrote the model first and it predicted exactly what happened in the experiment.”

Muneshwar and Cadien have published a paper on their discovery in the Journal of Applied Physics. Since the article’s appearance, they have been contacted by industry leaders requesting copies of the paper.

While small amounts of materials like zinc or silicon are required to produce thin film devices, Cadien says the costs are not insignificant–they can come in at $500 or $600 per gram and the current processes are wasteful, dosing surfaces with anywhere from 100 to 10,000 times the molecules required.

“Some of these are big molecules and in semiconductor manufacturing if you’re a company producing 10,000 12-inch wafers a week–small amounts of something add up to big amounts of something.”

The market precursors used in ALD is estimated to hit $400 million U.S. by 2020.

The two hope their discovery can lead to collaborative work with new industry partners in the future. Cadien notes that Muneshwar’s work could have a lasting impact on industrial practices because he was willing to experiment with the high-tech equipment available to him here.

“There are more than 1,000 atomic layer deposition systems in the world,” said Cadien, “but there’s only a small handful of people asking why and how these things work, who are trying new things. When you’re doing that, you can come up with breakthroughs like this.”