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Recent trends in multi-sensor measurements within a mass flow controller are reviewed, with a focus on controller self-diagnostics.

BY WILLIAM VALENTINE and SHAUN PEWSEY, Brooks Instrument, Hatfield, PA

Sub 20nm nodes and complex 3D architecture are driving new process control challenges. In regards to gas delivery, these complex and highly sensitive processes require mass flow controllers (MFCs) to provide better accuracy, repeatability, long term stability and consistent dynamic response. In addition, foundries are driving a need for greater process and equipment flexibility which means the MFC must meet demanding process requirements across a wider control range.

While the quality, reliability, accuracy, response and range of MFCs continues to improve year after year, the process is still at risk because meaningful real-time in situ data is limited or nonexistent. Consequently, an error in delivered flow that is substantial enough to cause yield and scrap issues would go undetected until the next off-line flow check.

In situ data traditionally has been limited to detecting obvious hard failures such as an MFC that is not communicating; the flow output doesn’t meet the set point; or the MFC output at a zero set point is offset (not zero). A zero offset will cause a change in flow accuracy if it is due to an active change in the zero reference of the flow meter. However, zero offsets recorded during a process can also be caused by an MFC valve leak or even an isolation valve leak. A few fault detection and clarification (FDC) systems attempt to trend valve voltage but hysteresis of up to 40 percent of a reading means that only obvious failures can be detected.

In lieu of in situ flow data, flow tests are performed off-line using a technique such as chamber rate of rise (ROR). The ROR technique is simply to evacuate a known volume, flow gas into it and measure pressure change. With chamber ROR, the known volume is the processing chamber. The chamber is taken off-line (not running a process) and the MFC is given a flow set point. As gas flows into the constant volume chamber, the chamber pressure rises at a constant rate. Flow can be calcu- lated using the gas law as shown in FIGURE 1. Off-line testing reduces tool availability and can only detect flow errors after the fact, placing wafer lots at risk. Chamber ROR accuracy is +/- 3 percent of reading to +/- 5 percent of reading, depending on flow rate, gas properties, temperature gradients, manometer accuracy and chamber outgassing. Even if a better flow standard is available, flow tests are time-consuming. Chamber ROR testing every MFC at only one set point on a four-chamber etch tool can take 12 hours and is typically performed weekly.

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Process engineers are seeking an in situ flow verification process to ensure process repeatability enabling real-time FDC to alarm on conditions that could lead to wafer scrap. In situ flow data could also be used to intelligently determine when to take a tool down for flow verification tests instead of running time-consuming weekly flow maintenance checks on all MFCs.

The evolution of the MFC

In 2004, MFC manufacturers developed pressure transient insensitive (PTI) MFCs. Pressure sensors were added to measure fluctuations in pressure and advanced control concepts were introduced to compensate for pressure fluctuations in real time.

Recently, several manufacturers have experimented with using pressure and temperature signals available in PTI MFCs to determine if the controller accuracy is degrading. (The authors have used the phrase “multi- sensor diagnostics” to describe this new class of advanced MFCs). Every multi-sensor diagnostic technique involves some form of pressure rate of decay (ROD). ROD is similar to chamber ROR except instead of flowing into a constant volume and measuring the pressure rise, flow is released from a constant volume and the rate of pressure decay is measured. The concept has been around for 30 years and involves shutting off an upstream valve to create a constant volume and measuring the pressure drop within the volume. The technique wasn’t practical until digital processors with enough computational power were available to perform the technique.

Multi-sensor diagnostic instrumentation can be broken into two groups. The first group (idle self-diagnostic) can only perform self-diagnostics while the tool is idle or in between process steps. Pressure decay in the volume is measured but there is no attempt to control flow. The signature of the pressure drop is compared to a previous measurement and analyzed to look for changes. While considered an improvement, this technique does not provide true in situ data and a dynamic event during a process could easily go undetected. The second group (active self-diagnostic) actively controls process steps while the pressure decay is measured. Although more challenging to implement, this technique enables true in situ flow verification (FIGURE 2).

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Examples of idle self-diagnostics

Example 1 – thermal MFC: The upstream isolation valve is closed and the position of the flow control valve is frozen. The MFC then records pressure decay. The characteristics of the pressure decay curve are compared to a baseline curve. Changes in the curve are trended to determine if a flow sensor is degrading (FIGURE 3). Special maintenance checks would have to be programed into the tool controller to take advantage of this technique as it cannot be triggered during a normal process run.

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Example 2 – pressure-based MFC: Traditional pressure- based MFCs measure pressure drop across a laminar flow element (LFE) (FIGURE 4). The valve must be placed upstream for two reasons. First, the pressure measurement is more accurate and stable if P2 is vacuum; second, this method requires a stable inlet pressure, P1. The downside to placing the valve upstream is slow turn off. The gas must bleed through the laminar flow element after the gas is turned off. The bleed downtime is a function of gas properties, the laminar flow element volume upstream of the LFE, and pressure in the upstream volume. For multi-sensor diagnostics, the manufacturer takes advantage of the bleed-down and characterizes the pressure decay every time the MFC is given a command to shut off. Any deviation from baseline signifies a change in either the LFE flow path or pressure sensors, and would trigger the user to perform a maintenance check.

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Active self-diagnostics

Unlike idle self-diagnostics, where MFC characterization is performed when the MFC is not running a process, the latest development in multi-sensor self-diagnostics enables true in situ flow verification. This means flow anomalies can be captured in real-time during a process and assessed before several wafers are affected.

FIGURE 5 shows the cross-section of a multi-sensor self-diagnostic MFC mounted on a traditional surface mount gas stick. In this example, the MFC contains a pilot valve that enables the MFC to control the state of the upstream isolation valve. Other implementations integrate the isolation valve into the body of the MFC.

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The MFC closes the upstream isolation valve when it is ready to take a secondary flow measurement. This creates a fixed volume between the isolation valve and the MFC control valve. While pressure decays in the volume, the MFC control system continues to maintain flow while recording pressure, temperature and time. A secondary flow measurement is computed based on the pressure decay (ROD) and compared to baseline data recorded during the installation of the MFC on the tool. Once this measurement is complete, the MFC re-opens the isolation valve. PTI technology is used to compensate for the initial pressure spike, ensuring continued stable flow. The same measurement technique can be used to monitor zero drift and valve leak when the MFC is given a zero set point.

Case study on etch process tool at leading IDM

Two multi-sensor MFCs capable of active self-diagnostics were installed on an etch chamber at a major integrated device manufacturer. The MFCs were configured to store accuracy, zero drift and valve leak self-diagnostic data in flash memory located within the MFC. Perfor- mance transparency tests were run with self-diagnostics activated to ensure the technology did not change the process. The process engineers continued to perform regular off-line flow verification tests at a set point of 30 percent. No accuracy issues were detected by the tradi- tional maintenance tests and no adjustments such as re-zeroing or re-calibration were performed. Data was collected for 24 months.

Active multi-sensor diagnostics vs. off-line chamber ROR: Self-diagnostic data was collected during the regular off-line flow verification tests. FIGURE 6 shows that repeatability of self-diagnostics was 8X better than the time-consuming off-line flow verification tests.

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Active flow accuracy: The etch process utilized MFC set points of 4 percent, 12 percent, 24 percent and 40 percent (FIGURE 7). In situ active self-diagnostic data was automatically collected at each set point every three seconds during wafer processing. The MFC flow accuracy was very repeatable over the two-year test period at set points of 24 percent and 40 percent. However, flow accuracy at 4 percent shows an increase in flow of 1 percent over the two-year evaluation period. Note that off-line flow verification tests were only performed at a set point of 30 percent where the MFC is stable. Tradi- tional off-line chamber ROR flow tests proved not only to be costly, but also ineffective in detecting flow changes in this case.

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In situ zero drift trending: Increasing flow errors at low set points usually indicate a change in the zero of the flow meter. The output of a flow meter should be zero at no flow. However, all measurement instruments will eventually drift resulting in some level of zero offset. A small zero offset in the flow meter is a negligible part of the flow signal at a high flow rate. However, small zero offsets can become significant when the MFC is operated at low set point such as 4 percent shown in this tool data. Conse- quently, the self-diagnostic zero reading was analyzed to see if the accuracy error at a 4 percent set point correlated with zero drift.

The MFC zero drift rate was < 0.027 percent full scale (FS) per year. This is exceptionally stable and 20X less than the spec limit (FIGURE 8). No mainte- nance test performed today on-tool would identify this low level of zero drift. This data highlights recent improvements in the stability of thermal MFCs. However, expanding the zero drift axis does reveal a slight trend in zero of 0.045 percent FS. This offset is exactly equal to the 1.1 percent of reading flow error identified during process runs at the 4 percent set point.

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Valve leak: Valve leak is linked to first wafer effects and can indicate contamination in the gas delivery line. Excessive valve leak can cause loss of control at low set points. Self-diagnostic valve leak was trended during this study. The MFC valve leak was extremely low and stable throughout the study (FIGURE 9). Process engineers typically get concerned when valve leak reaches 0.5 percent FS to 1.0 percent FS. The data reveals excellent resolution of the valve measurement and demonstrates how easy it would be to detect changes in valve leak well before it could affect process yield.

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TABLE 1 compares data and resolution available in situ from a traditional MFC; a tool in idle mode; a tool off-line; and the active multi-sensor self-diagnostic data captured in this study. The process knowledge gained from this technology enables the process engineer to be proactive instead of reactive. In addition, an intelligent FDC system could use this data to identify more subtle MFC issues such as excessive sensitivity to changes in pressure or temperature, and even leaks in the gas stick isolation valves.

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Conclusions

This data highlights how current best known methods for MFC on-tool monitoring and off-line maintenance are unable to capture changes in process and ensure repeatability.
The on-tool study demonstrated multi-sensor self- diagnostic MFC technology is a process-transparent upgrade with the capability to:

• Track flow changes in situ with 10X better resolutionthan currently available for off-line flow verification processes

• Enable advanced fault detection and classification where MFC performance is tracked while running process, and logic trees can be set up to determine root causes of process degradation

• Increase tool up-time, where determining the root cause before taking the tool off-line will minimize downtime; reduce or eliminate scheduled flow-verification tests; reduce troubleshooting; and reduce tool maintenance

• Eliminate MFC-induced wafer scrap, using an alarm to alert for conditions that may lead to wafer scrap before producing product.

References

1. Shajii, Ali, et al, “Model-Based Solution for Multigas Mass Flow Control with Pressure Insensitivity.” Solid State Technology Magazine, July, 2004.
2. McDonald, Mike R., “Beyond Pressure Transients: Using Pressure-Insensitive Mass Flow Controllers to Control Gases in Semiconductor Manufacturing.” Semiconductor Manufac- turing Magazine, March, 2006.
3. Valentine, Bill and Pete Friedli, “New MFC Control System Improves Tool Uptime and Process Consistency.” Solid State Technology Magazine, April, 2002.

Integrated sub-fab systems allow HVM fab operators to safely and efficiently implement new processes containing hazardous process chemicals.

BY ANDREW CHAMBERS, Edwards Ltd., Clevedon, UK

The relentless scaling of structures and reduction in thermal process budgets that characterize state- of-the-art integrated circuit (IC) production have resulted in the incorporation of many complex and hazardous materials into high-volume manufacturing (HVM) processes. In order to meet the need to deposit these materials at ever-lower temperatures, many of the new process chemicals have low vapor pressures, are highly reactive and present serious hazards to personnel and equipment. Many new CVD precursors and their associated reaction by-products are flammable, pyrophoric, toxic (harmful-to-health), corrosive or otherwise hazardous to personnel or destructive to equipment, and have a tendency to condense in pipe-work, including process exhausts.

In this article we will review the risks associated with these materials and describe methods for mitigating process exhaust pipe hazards in high-volume manufacturing. In particular, we will describe an approach based on the integrating vacuum pumps and point-of-use abatement systems with essential safety devices and monitoring systems into a complete sub-fab vacuum and abatement solution. Such modular integrated sub-fab systems ensure safe system operation, including mitigation of process exhaust hazards, and reduce exposure of service staff to hazardous materials.

Process gas and reaction product hazards

Clearly, exposure of staff and equipment to hazardous chemicals leaking from process exhausts is a serious concern and careful attention to the design, control, safety qualification and maintenance of process exhaust systems is essential in configuring a safe and reliable sub fab operations.
The properties of process chemicals may be altered significantly as they pass through a process tool, and reaction products found in process tool exhausts may differ markedly from the original process precursors. For example, while high flows of tetraethylorthosilicate (TEOS) are widely used in CVD processes for deposition of silicon oxide films, the concentration of residual unreacted TEOS in a CVD process tool exhaust is minimal [1]. Instead, the TEOS is decomposed in the process chamber to form a greater volume of mixed hydrocarbon gases (ethene and ethanol, for example [2]), which are then pumped out of the process chamber into the process exhaust. When the safety of process exhausts is evaluated in the design of protective measures, interactions and transformations of process gases such as this must be considered carefully.

Deposition of hazardous materials in exhausts

In some cases, the process by-products which pass into the exhaust pipe are condensable. Frequently encountered condensable by-products include aluminum chloride (AlCl3) in metal etch, ammonium chloride (NH4Cl) in LPCVD nitride, and ammonium hexafluorosilicate ((NH4)2(SiF6)) in PECVD nitride. Several of these condensates have also been found to incorporate partly-reacted hazardous materials. For example, partly- reacted silicon-containing compounds which condense in exhaust pipes during a PECVD process may react violently with fluorine gas which flows through the exhaust pipe during a subsequent chamber cleaning process. This has caused exhaust pipe fires and serious equipment damage in a number of cases (FIGURE 1).

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In addition to the reactivity hazard posed by these materials, accumulation of condensed material during processing can block exhaust pipes, causing process tool downtime and possibly loss of production. Furthermore, the reaction of condensed fluorine- or chlorine-containing materials with atmospheric water vapor during removal and cleaning of exhaust pipes can release HF or HCl gas or other hazardous substances, posing a serious risk to service staff and requiring preventive measures.

A particularly serious example of harmful deposited materials in exhaust pipes is the condensation of extremely reactive polysiloxane materials in Si epi or Si-Ge epi exhausts [3]. These materials are particularly hazardous since they can react unpredictably and violently (explosively) on exposure to water vapor or air, or if they suffer a mechanical shock when the exhaust pipes are removed for cleaning. The consequences of process gases escaping through leaks in exhaust pipes and the tendency of materials to condense in process exhaust pipes should be carefully considered when a process exhaust system is designed. Indeed, the exhaust pipe should be considered as an important functional element of the whole sub-fab process tool support system, otherwise there may be increased risks of staff injury and process tool downtime.

Leak integrity of process exhausts

Escape of process gases or reaction products from leaking process exhaust pipes presents serious risks to fab operations. For example:

• Flammable gas escaping from exhaust pipes may mix with air in closed spaces to create a fire risk
• Toxicgasesleakingoutofnon-enclosedexhaustpipes present an injury risk to fab personnel
• Corrosive gases leaking out of non-enclosed process exhausts can harm personnel and cause severe damage to fab equipment
• Process gas odors may cause complaints from fab staff or local residents

Typically, area gas detectors are deployed in fabs to warn of process gas leaks. These are very effective in detecting escaping process gas, but when they are activated process operations are interrupted and fab output affected. Furthermore, gas detectors cannot detect inward leaks into reduced pressure pump exhausts, such as air entering exhaust pipes where it could mix with flammable process gases to form flammable mixtures. In the worst case, a flammable process gas / air mixture could be ignited by a local ignition source, such as a dry-pump or point-of-use abatement system, and cause an exhaust pipe fire.

Configuring the vacuum/abatement/exhaust components as a single coherent system can increase staff safety and manufacturing efficiency by reducing the risk of hazardous process gas escape and ensuring appropriate action if a leak is detected In particular, integrated sub fab systems enable the use of extracted secondary enclosures around vacuum pumps, point-of-use abatement systems, fuel gas delivery systems and all interconnecting pipework to contain escaping gas, while ownership, maintenance and integrity of the process exhaust pipes becomes the responsibility of the system supplier, rather than remaining undefined.

Exhaust dilution

A standard safety precaution widely used to avoid the possibility of fires in process exhausts is the dilution of flammable gases below their Lower Flammable Limit (LFL). However, there are risks with this strategy. Considering the previously cited example, if the required dilution flow is calculated based only on the volume of TEOS gas in the exhaust pipe, it will be insufficient to dilute the larger volume of hydrocarbon decomposition products below their LFL. A related risk is formation of a flammable mixture in the exhaust if there is an air leak into the exhaust pipe coincident with the TEOS being decomposed by the process chamber.

As noted above, the process dry-pump and point-of- use abatement system are both ignition sources that could ignite the hydrocarbon / air mixture and cause an exhaust pipe fire.

To operate process exhausts containing flammable gases safely using this strategy, not only must the dilution flow be calculated appropriately, but the vacuum and abatement system controller must include a capability to shut off the flammable gas flow from the process tool if the dilution flow should drop below some critical level, or if a fire occurs in the exhaust pipe, as required by semiconductor industry safety standards such as SEMI S18 [4].

In recent times, the risks associated with flammable and pyrophoric gases have become more severe as highly reactive compounds such as disilane and trimethyl aluminum have become more widely used in CVD processes. Some of these materials have extremely low LFLs – for example, disilane has a published LFL of 0.2% [5], and trimethyl aluminum is known to be extremely flammable though specific LFL data appears not to be widely available [6]. This characteristic makes their dilution to safe levels costly and inefficient from an operational efficiency perspective. For example, the low LFL of disilane requires a very large volume of nitrogen required to dilute it to a safe level, increasing the direct cost of the nitrogen and putting additional load on the fab facilities. The resulting high gas flow in the process exhaust increases the total cost of abatement by requiring larger, more expensive equipment, more sub-fab floor space, and a higher utility consumption. Finally, the abatement efficiency of highly-diluted process gases may be degraded, creating an environmental concern if emissions of process gas that exceed permitted levels.

Temperature control of process exhaust pipes

The risks posed by the condensation of process by-products in exhaust pipes can be mitigated by controlling the temperature of the exhaust pipes at a suitably high value (FIGURE 2). Commercial products are widely available to perform this function, but when selecting a suitable system, its capability to maintain a uniform temperature throughout the exhaust system should be considered carefully – in particular, cold spots caused by inadequate thermal insulation or lack of adequate real-time temperature control can cause localized by-product condensation and pipe blockage. At the other extreme, if exhaust pipes are heated to an excessively high temperature, unused CVD precursors may react, depositing solid materials in the exhaust pipe. Ideally, temperature will be actively and precisely controlled within a specified range.

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Integrated sub-fab systems

Integration of the process exhaust pipe assemblies together with dry-pumps and point-of-use abatement into a complete sub-fab system by the equipment manufacturer permits an optimization of safety, performance, efficiency and cost that cannot be achieved in the installation of discrete units by individual suppliers.

A typical integrated sub-fab system is designed to incorporate dry-pumps, point-of-use abatement systems, exhaust pipe assemblies, temperature management systems (TMS), together with all necessary safety devices, into a single entity which also includes a supervisory control system and all process tool and fab interfaces. Since all individual functional elements are integrated into a single unit, typically only one connection for each fab utility is required – not only does this reduce the overall installation cost of the sub-fab equipment, it also occupies less valuable sub-fabspace.Each such integrated system is typically used to support a single process tool, and is usually designed to fit conveniently within the “shadow” of the process tool in the sub-fab.

This close integration of the individual sub-fab functional elements into a unified system enables a reduction in risks associated with exhaust pipe leaks by continuously monitoring the leak status of the exhaust pipes, by monitoring the air extraction rate in secondary enclosures, and by monitoring the temperature and pressure in the process exhaust pipes. In the event of an excursion by any of these parameters into a critical condition, an integrated system can be designed to initiate shut-down of the process gas through its interfaces to the process tool, and alert the fab MES through its interface to a central monitoring system (CMS). Furthermore, real-time collection and processing of data from all the functional elements in the integrated system allows events leading up to previous alerts to be analyzed. Predictive algorithms can then be developed that can enable the CMS to antic- ipate or predict future failure events.

Provided the safety features of an integrated sub-fab system are properly designed, including those which specifically monitor the condition of the exhaust pipes, it becomes practical to reduce dilution rates of flammable gases safely, leading to significant reductions in required abatement capacity, capital equipment investment, utilities consumption and total operating costs in a high volume manufacturing environment (FIGURE 3).

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Implementation of Best Known Methods (BKMs)

Integrated sub-fab systems are typically built, installed and serviced by a single supplier, who takes responsibility for the complete system design, including all necessary safety functions and external interfaces. Safe sub-fab system operation is normally assured by a comprehensive safety assessment of the integrated system design and by compliance with global semiconductor industry safety standards such as SEMI S2 [7].

However, to ensure the most efficient operation it is also necessary to set-up the sub-fab system according to a Best Known Method (BKM) for each process tool. Application of process BKMs ensures that each integrated sub-fab system is fit-for-purpose to meet the specific require- ments of its allocated process tool, and shortens the time required to qualify the tool for process. Typically, sub-fab equipment suppliers use know-how based on experience of similar processes in other HVM facilities to define their own BKMs and set-up equipment properly. Once an integrated system is operational, service support, applications support and continuous improvement programs (CIP) are all available from a single source which ensures that all critical safety systems are properly maintained and comply with the latest BKMs (FIGURE 4).

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Summary

The concept of integrated sub-fab systems is a valuable tool that allows HVM fab operators to safely and efficiently implement new processes containing hazardous process chemicals. The integrated function- ality and comprehensive safety systems guard against hazardous process gas escape, leakage of air into exhausts containing flammable gas, and condensation of a wide range of hazardous materials in exhaust pipes. Collectively these attributes enable the safest and most efficient sub-fab operation for HVM.

References

1. Edwards Ltd. – unpublished data
2. M.G.M. Van Der Vis, E. Cordfunke, R. Konings: The thermody-
namic properties of Tetraethoxysilane and an infra-red study of its decomposition, Journal de Physique IV, 1993, 03 (C3), pp.C3-75-C3-82
3. Safety Applications Procedure SAP 00-01 – Pumping Reduced Pressure Epitaxy (RP Epi) Applications, Edwards Ltd.
4. SEMI S18-0312 Environmental, Health and Safety Guideline for Flammable Silicon Compound, SEMI
5. MSDS #1038 (Disilane) Air Products, Pub #320-708
6. MSDS #257222 (Trimethylaluminum) Sigma-Aldrich product
#257222
7. SEMI S2-0715, Environmental, Health and Safety Guideline for
Semiconductor Manufacturing Equipment, SEMI

ANDREW CHAMBERS currently holds the position of Senior Product Manager at Edwards Ltd., Clevedon BS21 6TH, UK [email protected]

ACM Research (Shanghai), Inc. has announced that it has solved the problem of patterned wafer cleaning. This is another breakthrough at ACM after it developed Space Alternating Phase Shift (SAPS) megasonic cleaning in 2011.

Compared to flat wafer cleaning, patterned wafer cleaning is much more complicated and challenging. With the decreasing line width and increasing aspect ratio, cleaning a patterned wafer without damage is much more difficult than ever. Meanwhile, as the feature size continues to shrink, the impact of fine particles (less than 30 nm) and contaminates to final device yields are much more significant.

“Finding the solution for patterned wafer cleaning has been an urgent challenge for the semiconductor equipment industry in recent years,” Dr. David Wang, President and CEO of ACM, mentioned. “When it comes to 1X nm and below manufacturing nodes, you must be capable of cleaning particle sizes smaller than tens of nm, and one cleaning step is used on average after every two non-clean processing steps in order to achieve high yield. This is where ACM’s proprietary megasonic cleaning technologies areuniquely effective.”

ACM’s newly-developed, proprietary Timely Energized Bubble Oscillation (TEBO) technology solved the problem of pattern damages caused by transit cavitation in the conventional megsonic clean process. By using TEBO, the cavitation becomes stable without bubble implosion or collapse during megasonic cleaning processing. The damage-free physical cleaning capability of TEBO with high Particle Removal Efficiency (PRE) has been demonstrated on 1X nm patterned wafers. The TEBO cleaning technology can be applied not only in FinFet manufacturing processes, but also in the high aspect ratio of DRAM and 3D NAND manufacture processes. (Aspect ratio of 30:1 or even 60:1.)

Nanoelectronics research center imec presents at OFC 2016, the international event for both the science and business of optical communications held March 20-24, performance improvements of various key building blocks of its wafer-scale integrated silicon photonics platform (iSiPP). The new results expand imec’s iSiPP device portfolio to support 50Gb/s non-return-to-zero (NRZ) lane rates, and are an important milestone for the realization of high data rate silicon integrated optical interconnects targeting high density, high bandwidth, low power telecom and datacom transceivers, as well as for low cost large volume applications such as sensors or LiDAR.

Through process and design optimizations, imec has improved the operating speed of the silicon based traveling-wave mach-zehnder modulators and ring modulators to reach 50Gb/s NRZ lane rates. In addition, a C-band GeSi electro-absorption modulator was developed with electro-optical bandwidth beyond 50GHz, enabling NRZ modulation at 56Gb/s and beyond.  All modulator types can be driven with competitive drive voltages of 2Vpp or below, enabling compatibility with power efficient CMOS driver circuits.

The responsivity of the high-speed Ge photodetectors has been improved to 1A/W, enabling highly sensitive 50Gb/s NRZ receivers both in the C-band and the O-band. Also, edge coupling structures were developed for broadband optical coupling to high-NA and lensed fiber with less than 3dB insertion loss in the C-band. Moreover, designers can exploit the superior patterning fidelity provided by 193-nm lithography, enabling robust active and passive waveguide devices.

The 50Gb/s components are included in imec’s 200mm silicon photonics multi-project wafer (MPW) offer, and are supported by a Process Design Kit (PDK). The MPW service is available via Europractice IC service and MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs. Imec’s active iSiPP50G run is now open for registration (deadline June 28th 2016) with first wafers out in January 9th 2017.

Imec also provides technology customization options with dedicated wafer fabrication services supported by a PDK. This service enables the use of full-size reticles, delivery of full wafers, and access to specialty modules enabling high efficiency integrated heaters, MOSCAP devices and flip-chip assembly amongst others.

The PDK’s have been validated with silicon data, based on a minimum of two process runs for most of the components, and describe the process and device performance statistics. They are supported in various EDA environments and include DRC, supporting first-time right designs.

imec 032116

IRT Nanoelec, an R&D consortium focused on information and communication technologies (ICT) using micro- and nanoelectronics, today announced the first co-integration of a III-V/silicon laser and silicon Mach Zehnder modulator demonstrating 25 Gbps transmission on a single channel. This transmission rate usually is achieved using an external source, over a 10 km single-mode fiber.

Current interconnect technologies, which use micro-optics integration to assemble a discrete laser and a silicon photonic circuit, will soon reach their limits and new, different solutions will have to be found to handle increasing traffic.

Integrating photonics capabilities on silicon chips is replacing currently established technologies, vastly increasing bandwidth, density and reliability, while dramatically reducing energy consumption. In the age of photonics-on-silicon, data transmission will be measured in terabits per second.

“Jointly obtained by STMicroelectronics and Leti in the frame of the IRT Nanoelec cooperation, these results, especially fabricating the laser directly on silicon, demonstrate IRT Nanoelec’s worldwide leadership in III/V-on-silicon integration to achieve high-data-rate fiber-optic modules,” said Stéphane Bernabé, project manager. “IRT Nanoelec and its partners on this project, Leti, STMicroelectronics, Samtec and Mentor Graphics, are paving the way to integrating this technology in next-generation transceivers for optical data links.”

To achieve these recent results, silicon photonics circuits integrating the modulator were processed first on a 200mm SOI wafer, although 300mm wafers also could be used in the near future. Then, a two-inch wafer of III-V material was directly bonded on the wafer. In the third step, the hybrid wafer was processed using conventional semiconductor and/or MEMS process steps to produce an integrated modulator-and-laser transmitter.

IRT Nanoelec launched its silicon photonics program in 2012, with core members Mentor Graphics, STMicroelectronics and CNRS. The program brings together, under one roof, the expertise and equipment needed to address the entire photonics-on-silicon value chain.

Leti, which will attend the Optical Fiber Communication Conference in Anaheim, Calif., March 20-24, and have a booth at the Exhibition Hall (3759), is a major innovation player in III-V/silicon integration for high-data-rate fiber optics modules.

Two-dimensional electronic devices could inch closer to their ultimate promise of low power, high efficiency and mechanical flexibility with a processing technique developed at the Department of Energy’s Oak Ridge National Laboratory.

A team led by Olga Ovchinnikova of ORNL’s Center for Nanophase Materials Sciences Division used a helium ion microscope, an atomic-scale “sandblaster,” on a layered ferroelectric surface of a bulk copper indium thiophosphate. The result, detailed in the journal ACS Applied Materials and Interfaces, is a surprising discovery of a material with tailored properties potentially useful for phones, photovoltaics, flexible electronics and screens.

This diagram illustrates the effect of helium ions on the mechanical and electrical properties of the layered ferroelectric: a.) Disappearance domains in the exposed area; as the mound forms yellow regions (ferroelectricity) gradually disappear; b.) Mechanical properties of the material; warmer colors indicate hard areas, cool colors indicate soft areas; c.) Conductivity enhancement; warmer colors show insulating areas, cooler colors show more conductive areas. Credit: ORNL

This diagram illustrates the effect of helium ions on the mechanical and electrical properties of the layered ferroelectric: a.) Disappearance domains in the exposed area; as the mound forms yellow regions (ferroelectricity) gradually disappear; b.) Mechanical properties of the material; warmer colors indicate hard areas, cool colors indicate soft areas; c.) Conductivity enhancement; warmer colors show insulating areas, cooler colors show more conductive areas. Credit: ORNL

“Our method opens pathways to direct-write and edit circuitry on 2-D material without the complicated current state-of-the-art multi-step lithographic processes,” Ovchinnikova said.

She and colleague Alex Belianinov noted that while the helium ion microscope is typically used to cut and shape matter, they demonstrated that it can also be used to control ferroelectric domain distribution, enhance conductivity and grow nanostructures. Their work could establish a path to replace silicon as the choice for semiconductors in some applications.

“Everyone is looking for the next material – the thing that will replace silicon for transistors,” said Belianinov, the lead author. “2-D devices stand out as having low power consumption and being easier and less expensive to fabricate without requiring harsh chemicals that are potentially harmful to the environment.”

Reducing power consumption by using 2-D-based devices could be as significant as improving battery performance. “Imagine having a phone that you don’t have to recharge but once a month,” Ovchinnikova said.

GLOBALFOUNDRIES today announced new advanced radio-frequency (RF) silicon solutions, further expanding the portfolio of Silicon Germanium (SiGe) power amplifier (PA) technologies designed to enable performance-optimized cellular and Wi-Fi solutions in increasingly sophisticated mobile devices and hardware.

GLOBALFOUNDRIES’ 5PAx and 1K5PAx, together called PAx, are the latest extensions to its broad family of SiGe-based PA technologies. The advanced offerings deliver optimized PA, LNA and switch technology with improved power efficiency, noise figure and insertion loss enabling more power efficient next-generation Wi-Fi and cellular solutions for faster data access and uninterrupted connections.

“Mobile suppliers are facing mounting pressure to expand network capacity as wireless data consumption continues to increase rapidly,” said Dr. Bami Bastani, senior vice president of GLOBALFOUNDRIES RF business unit. “Our broad portfolio of high-performance SiGe power amplifier technologies provides a distinct design, performance and cost advantage that enables our mobility customers to deliver cost-effective solutions with faster data throughput, support wider coverage areas, and consume less power.”

Skyworks, a leader in high-performance analog semiconductor solutions, plans to use the technology to enhance both the power capability and efficiency for the next generation of mobile WLAN products and high-performance WLAN products, including access points, routers and IoT applications.

“The advances that are part of GLOBALFOUNDRIES’ SiGe PAx technologies enable RF front-end solutions for all levels of performance and complexity,” said Bill Vaillancourt, vice president and general manager of Mobile Connectivity at Skyworks Solutions. “With these advanced features and the ability to minimize form factor by implementing multiple RF functions on a chip, GLOBALFOUNDRIES’ latest PAx offerings enhance the capabilities of integrated semiconductor solutions that support customers’ needs for high performance, cost effective technologies addressing portable wireless communication devices.”

There are four technologies in GLOBALFOUNDRIES’ SiGe PA family, SiGe 5PAe, 1KW5PAe, and now 5PAx and 1K5PAx. All four offerings feature GLOBALFOUNDRIES’ proven through-silicon via technology and provide significant performance, integration functionality and cost advantages for customers who are currently using gallium arsenide (GaAs)-based alternatives. Today, there are more than three billion SiGe power amplifiers shipped worldwide using this family of technologies, and GLOBALFOUNDRIES has recently invested in additional manufacturing capacity to address the anticipated growth in the mobile sector. The newest offerings, 5PAx and 1K5PAx, are optimized to meet the rigorous demands of evolving mobile standards like 802.11ac, which demands three times faster data throughput than the previous generation of standards.

For 5GHz applications, SiGe 5PAx, the follow-on to SiGe 5PAe, supports 2dB gain along with a 5 percent PAE and 0.2dB low noise amplifier (LNA) improvements relative to the previous generation. SiGe 1K5PAx, like its predecessor 1KW5PAe, is built on a high-resistivity substrate, and is tuned for integration and higher performance. It features RF switches with approximately 15 percent better Ron-Coff compared to 1KW5PAe, and like 1KW5PAe, enables designers to minimize form factor by implementing multiple functions, such as power amplifiers, RF switches and LNAs, on a single chip.

It’s hardly a character flaw, but organic transistors–the kind envisioned for a host of flexible electronics devices–behave less than ideally, or at least not up to the standards set by their rigid, predictable silicon counterparts. When unrecognized, a new study finds, this disparity can lead to gross overestimates of charge-carrier mobility, a property key to the performance of electronic devices.

If measurements fail to account for these divergent behaviors in so-called “organic field-effect transistors” (OFETs), the resulting estimates of how fast electrons or other charge carriers travel in the devices may be more than 10 times too high, report researchers from the National Institute of Standards and Technology (NIST), Wake Forest University and Penn State University. The team’s measurements implicate an overlooked source of electrical resistance as the root of inaccuracies that can inflate estimates of organic semiconductor performance.

A circuit made from organic thin-film transistors is fabricated on a flexible plastic substrate. A team of NIST, Wake Forest, and Penn State University researchers has identified an overlooked source of electrical resistance that can exert a dominant influence on organic-semiconductor performance. Credit: Patrick Mansell/Penn State

A circuit made from organic thin-film transistors is fabricated on a flexible plastic substrate. A team of NIST, Wake Forest, and Penn State University researchers has identified an overlooked source of electrical resistance that can exert a dominant influence on organic-semiconductor performance. Credit: Patrick Mansell/Penn State

Their article appears in the latest issue of Nature Communications.

Already used in light-emitting diodes, or LEDs, electrically conductive polymers and small molecules are being groomed for applications in flexible displays, flat-panel TVs, sensors, “smart” textiles, solar cells and “Internet of Things” applications. Besides flexibility, a key selling point is that the organic devices–sometimes called “plastic electronics”–can be manufactured in large volumes and far more inexpensively than today’s ubiquitous silicon-based devices.

A key sticking point, however, is the challenge of achieving the high levels of charge-carrier mobility that these applications require. In the semiconductor arena, the general rule is that higher mobility is always better, enabling faster, more responsive devices. So chemists have set out to hurry electrons along. Working from a large palette of organic materials, they have been searching for chemicals–alone or in combination–that will up the speed limit in their experimental devices.

Just as for silicon semiconductors, assessments of performance require measurements of current and voltage. In the basic transistor design, a source electrode injects charge into the transistor channel leading to a drain electrode. In between sits a gate electrode that regulates the current in the channel by applying voltage, functioning much like a valve.

Typically, measurements are analyzed according to a longstanding theory for silicon field-effect transistors. Plug in the current and voltage values and the theory can be used to predict properties that determine how well the transistor will perform in a circuit.

Results are rendered as a series of “transfer curves.” Of particular interest in the new study are curves showing how the drain current changes in response to a change in the gate electrode voltage. For devices with ideal behavior, this relationship provides a good measure of how fast charge carriers move through the channel to the drain.

“Organic semiconductors are more prone to non-ideal behavior because the relatively weak intermolecular interactions that make them attractive for low-temperature processing also limit the ability to engineer efficient contacts as one would for state-of-the-art silicon devices,” says electrical engineer David Gundlach, who leads NIST’s Thin Film Electronics Project. “Since there are so many different organic materials under investigation for electronics applications, we decided to step back and do a measurement check on the conventional wisdom.”

Using what Gundlach describes as the semiconductor industry’s “workhorse” measurement methods, the team scrutinized an OFET made of single-crystal rubrene, an organic semiconductor with a molecule shaped a bit like a microscale insect. Their measurements revealed that electrical resistance at the source electrode–the contact point where current is injected into the OFET– significantly influences the subsequent flow of electrons in the transistor channel, and hence the mobility.

In effect, contact resistance at the source electrode creates the equivalent of a second valve that controls the entry of current into the transistor channel. Unaccounted for in the standard theory, this valve can overwhelm the gate–the de facto¬ regulator between the source and drain in a silicon semiconductor transistor–and become the dominant influence on transistor behavior.

At low gate voltages, this contact resistance at the source can overwhelm device operation. Consequently, model-based estimates of charge-carrier mobility in organic semiconductors may be more than 10 times higher than the actual value, the research team reports.

Hardly ideal behavior, but the aim of the study, the researchers write, is to improve “understanding of the source of the non-ideal behavior and its impact on extracted figures of merit,” especially charge-carrier mobility. This knowledge, they add, can inform efforts to develop accurate, comprehensive measurement methods for benchmarking organic semiconductor performance, as well as guide efforts to optimize contact interfaces.

GLOBALFOUNDRIES today announced the availability of a new set of process design kits (PDKs) with an interoperable co-design flow to help chip designers improve design efficiency and deliver differentiated RF front-end solutions in increasingly sophisticated mobile devices.

GLOBALFOUNDRIES’ RF Silicon-on-Insulator (RF SOI) technologies offer significant performance, integration and area advantages in front-end RF solutions for mobile devices and RF chips for high-frequency, high-bandwidth wireless infrastructure applications. GLOBALFOUNDRIES’ most advanced RF SOI technology, 7SW SOI, is optimized for multi-band RF switching in next-generation smartphones and poised to drive innovation in Internet of Things (IoT) applications.

The challenges of high-frequency and large-signal design in these applications have increased the need for an interoperable co-design flow. Designed for use with Keysight Technologies’ Advanced Design System (ADS) EDA software, GLOBALFOUNDRIES’ new 7SW SOI PDKs allow designers to edit their designs in ADS using a single Si2 OpenAccess database without any interference.

The RFIC interoperability simplifies the design process by enabling the user to work from a single design database in ADS. This allows the user to edit and simulate schematic designs created in ADS. The same is true for layout where, for example, a user can open an IC layout cell view in ADS, instantiate the cell within a package or module, and then run an electromagnetic simulation on the complete design to validate its overall system performance.

“After releasing the first co-design PDK for our 5PAe silicon germanium offering, we are now extending our coverage of ADS PDK to our most advanced RF SOI technology, 7SW SOI. Our 7SW platform, with superior LNA, switch devices, and trap-rich substrates, offer improved devices reception, interference rejection, and battery life for fewer dropped calls and longer talk time,” said Peter Rabbeni, senior director of RF product marketing and business development at GLOBALFOUNDRIES. “Our RF SOI technology has gained significant industry traction for cellular front-end module applications, and the new RFIC interoperability feature will allow us to provide our 7SW customers additional design flexibility with a single PDK.”

“GLOBALFOUNDRIES customers can now access ADS’ dedicated RF design flow tools based on an OpenAccess based silicon PDK,” said Volker Blaschke, Silicon RFIC product marketing manager, Keysight EEsof EDA. “The new interoperability feature facilitates the design process by using a single OpenAccess design data library, removing redundant steps of keeping the design across different EDA environments in sync.”

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, and JOANNEUM RESEARCH (JR), an international research organization based in Graz, Austria, today announced that they are collaborating on a joint-solution for research and development activities in large-area nanoimprinting leveraging the EVG770 automated UV-nanoimprint lithography (NIL) step-and-repeat system. Specifically, the two organizations have adapted the EVG770 with new capabilities to accommodate foil substrates that will enable the EVG770 to be used at JR to manufacture flexible master templates applied in roll-to-roll NIL processing for photonics, functional surfaces and microfluidic device production.

In UV-NIL processing, templates are used to imprint device patterns and structures onto a substrate, such as a wafer or a foil, which is coated with a UV-curable photoresist.

“Nanoimprint lithography is an inherently lower-cost patterning process compared to other lithographic approaches and is ideally suited for certain high-volume production applications, particularly in the photonics and medical industries. However, the time and cost associated with manufacturing working stamps for roller-based NIL can still be significant, and this limits the flexibility that organizations have in conducting research to explore NIL’s potential in these application areas,” stated Dr. Ursula Palfinger, project leader at JOANNEUM RESEARCH MATERIALS. “EV Group’s equipment and process expertise in NIL make them an ideal partner to realize the full potential of NIL and to bridge the gap in manufacturing large-scale master templates for roll-to-roll NIL out of original small-scale templates. The results of this work can have a profound impact on enabling greater process flexibility and further cost reductions in NIL processing.”

This research being conducted by JOANNEUM RESEARCH in cooperation with EVG involves the use of the innovative EVG770 NIL system to reproduce small pattern fields in a step-and-repeat fashion across a large-area substrate (up to 629 mm x 270 mm) in order to produce flexible large-area master stamps for use in roll-to-roll NIL processes. This first-of-its-kind approach to master template fabrication offers a cost-effective and high-throughput alternative to other approaches such as e-beam writing. In addition, the EVG770 NIL offers extremely-high resolution (sub-30nm), overlay alignment accuracy and repeatability, which are essential for ensuring the production of high-quality master templates using a step-and-repeat NIL patterning process.

JOANNEUM RESEARCH offers research pilot lines to serve its customers in implementing new innovations and products from idea to prototype, and to develop the necessary manufacturing methods. The pilot line for roll-to-roll micro and nanostructuring at JR MATERIALS Institute for Surface Technologies and Photonics in Weiz, Austria involves simulation, design and material development (polymers, coatings), and offers pattern fabrication and reproduction from mastering to roll-to-roll manufacturing and testing. The EVG770 NIL stepper with its unique capabilities concerning large flexible substrates and high alignment accuracy perfectly completes this pilot line in terms of scaling up master and working stamps for roller-based processes.

“For more than 30 years, EV Group has developed innovative lithography solutions for micro- and nanoelectronics manufacturing. Our expertise and close collaborations with customers and industry partners has enabled us to extend the capabilities of our solutions to enable many exciting new applications,” stated Dr. Thomas Glinsner, corporate technology director at EV Group. “This latest project with JOANNEUM RESEARCH allows us to demonstrate the ability of our benchmark EVG770 NIL stepper to provide a cost-efficient solution for larger-area mastering applications beyond wafer-size substrates. As a result, this can create exciting new opportunities for both EV Group and our customers.”