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Light and electrons interact in a complex dance within fiber optic devices. A new study by University of Illinois engineers found that in the transistor laser, a device for next-generation high-speed computing, the light and electrons spur one another on to faster switching speeds than any devices available.

Milton Feng, the Nick Holonyak Jr. Emeritus Chair in electrical and computer engineering, found the speed-stimulating effects with graduate students Junyi Qiu and Curtis Wang and Holonyak, the Bardeen Emeritus Chair in electrical and computer engineering and physics. The team published its results in the Journal of Applied Physics.

As big data become bigger and cloud computing becomes more commonplace, the infrastructure for transferring the ever-increasing amounts of data needs to speed up, Feng said. Traditional technologies used for fiber optic cables and high-speed data transmission, such as diode lasers, are reaching the upper end of their switching speeds, Feng said.

“You can compute all you want in a data center. However, you need to take that data in and out of the system for the user to use,” Feng said. “You need to transfer the information for it to be useful, and that goes through these fiber optic interconnects. But there is a fundamental switching limitation of the diode laser used. This technology, the transistor laser, is the next-generation technology, and could be a hundred times faster.”

Diode lasers have two ports: an electrical input and a light output. By contrast, the transistor laser has three ports: an electrical input, and both electrical and light outputs.

The three-port design allows the researchers to harness the intricate physics between electrons and light. For example, the fastest way for current to switch in a semiconductor material is for the electrons to jump between bands in the material in a process called tunneling. Light photons help shuttle the electrons across, a process called photon-assisted tunneling, making the device much faster.

In the latest study, Feng’s group found that not only does photon-assisted tunneling occur in the transistor laser, but that it in turn stimulates the photon absorption process within the laser cavity, making the optical switching in the device even faster and allowing for ultra-high-speed signal modulation.

“The collector can absorb the photon from the laser for very quick tunneling, so that becomes a direct-voltage-modulation scheme, much faster than using current modulation,” Feng said. “We also proved that the stimulated photon-assisted tunneling process is much faster than regular photon-assisted tunneling. Previous engineers could not find this because they did not have the transistor laser. With just a diode laser, you cannot discover this.

“This is not only proving the scientific point, but it’s very useful for high-speed device modulation. We can directly modulate the laser into the femtosecond range. That allows a tremendous amount of energy-efficient data transfer,” Feng said.

The researchers plan to continue to develop the transistor laser and explore its unique physics while also forming industry partnerships to commercialize the technology for energy-efficient big data transfer.

A team of researchers, led by a group at the University of California, Riverside, have demonstrated for the first time the transmission of electrical signals through insulators in a sandwich-like structure, a development that could help create more energy efficient electronic devices.

Conventional electronic devices rely on the transport of electrons in a semiconductor such as silicon. Now, researchers are exploiting the ‘spin’ of the electron rather than its charge to create a new generation of ‘spintronic’ devices that are potentially more energy efficient and more versatile than those currently making up silicon chips and circuit elements.

The UC Riverside-led research, which was published online Wednesday (March 2) in the journal Nature Communications, is significant because it demonstrates that a tri-layer, sandwich-like, structure can serves as a scalable pure spin current device, an essential ingredient in spintronics.

A key element in this breakthrough is the material. To demonstrate the effect, the magnetic insulator needs to be truly insulating, or there will be a parasitic signal from leakage. On the other hand, a high-quality magnetic insulator grown on metal had never been demonstrated.

Using combination of sputtering (for metals) and pulsed laser deposition (for insulator), we successfully showed that the 50-100 nanometer thick magnetic insulator, such as yttrium iron garnet, is not only magnetic and insulating, but also of high quality when it is grown on 5 nanometer thick platinum.

In the structures used by the researchers, there are two metals and a magnetic insulator in between. The metals are for spin current generation and detection (conversion of spin current back to charge current) via the so-called spin Hall effect and inverse spin Hall effect.

The magnetic insulator is an electrical insulator but a good spin current conductor. The spin current flowing in the insulator does not involve mobile electrons therefore it does not dissipate energy as an electrical current does in joule heating.

The researchers have also demonstrated that the signal transmission can be switched on and off and modulated in its strength by a magnetic field. The electrical signal transmission through the magnetic insulators can be switched on and off depending on the magnetic state, or direction of the magnetization, of the magnetic insulators.

So the direction of the magnetization can be regarded as a memory state of non-volatile random access memory devices. In addition, the signal level can be modulated by changing the direction of the magnetization; therefore, it can also be used as analog devices. The sandwich structure can be made small by nanofabrication so that the devices can be scaled down.

Nano-electronics research center imec and Nova Measuring Instruments, a key provider of metrology solutions for advanced process control used in semiconductor manufacturing, announced this week at the SPIE advanced lithography conference that they are jointly developing an innovative scatterometry approach to enable SAQP process control.

As 193nm immersion lithography is reaching its optical resolution limit using single exposure, advanced multipatterning concepts are studied to reach lower nodes. Targeting the N7 node, self-aligned quadruple patterning (SAQP) is an advanced patterning approach that uses pitch splitting to extend the capability of double patterning (SADP) 193nm immersion lithography. Nova and imec jointly developed an approach based on scatterometry technology to determine the main contributors to the CD (critical dimension) variation between different populations of lines and spaces. Using parallel interpretation of multiple scatterometry targets with slightly variable pitches, the researchers revealed that scatterometry is capable of measuring different space populations, and the developed metrology solutions can be utilized to monitor and control each process step of SAQP patterning.

“Collaborating with Nova has enabled us to develop a method to improve process control in SAQP for the most advanced nodes,” said An Steegen, senior vice president process technology at imec. “Such collaboration is helping the entire semiconductor industry to lower risks and shorten the time to market for the next generation technologies by delivering innovative metrology solutions for the key process control challenges ahead.”

“We are excited with the opportunity to collaborate with imec, join its Affiliation Program and demonstrate the value of our optical CD for early R&D stages,” said Dr. Shay Wolfling, Nova’s CTO. “We believe that the growing process challenges arising from the advance technology nodes require close partnership between research centers, customers and vendors and this is part of Nova’s stated long-term strategy. Such collaboration with imec, early in the development cycle, allows us to align our technology roadmap accordingly and contribute to our customers’ success.”

Mentor Graphics Corp. ushered in a new era of emulation by announcing new applications for the Veloce emulation platform. The new Veloce Apps—Veloce Deterministic ICE, Veloce DFT and Veloce FastPath—overcome critical system-level verification challenges in complex SoC and system designs. They run on an upgraded Veloce OS3 operating system that significantly accelerates design compile cycles, gate-level flows, and the time it takes to review results (“time to visibility”). The combination of Veloce Apps on Veloce OS3 puts more capabilities into the hands of more engineers more quickly than hardware-centric strategies.

Each of the new Veloce Apps addresses a specific verification issue:

  • Veloce Deterministic ICE overcomes unpredictability in In-circuit Emulation (ICE) environments by adding 100% visibility and repeatability for debug, and provides access to other ‘virtual-based’ use models;
  • Veloce DFT accelerates Design for Test (DFT) verification prior to tape-out to
    minimize the risk of catastrophic failure, and significantly reduces run times when verifying designs after DFT insertion; and
  • Veloce FastPath optimizes emulation performance when verifying large multi- clock SoC designs by enabling faster model execution speed.

These new Veloce Apps join Veloce Power, Veloce Enterprise Server and other apps in an expanding arsenal of software innovations for the Veloce emulation platform. Mentor will continue to expand the library of Veloce Apps to introduce new ways to ensure designs meet their functional and performance specifications on schedule.

The new Veloce Deterministic ICE, Veloce DFT and Veloce FastPath applications expand the Veloce Apps library to put more emulation capabilities the hands of more engineers.

The new Veloce Deterministic ICE, Veloce DFT and Veloce FastPath applications expand the Veloce Apps library to put more emulation capabilities the hands of more engineers.

The Veloce OS operating system adds software programmability and resource management to the Veloce platform, making it easier to add new use models that increase the ROI of the emulator. The recent upgrade of Veloce OS3 covers several innovations:

  • Integration of new High Performance Computing platforms cuts compile time by 50%.
  • A faster gate-level flow operates as “plug-and-play”—able to accept flat or hierarchical designs. This flow reduces the amount of memory needed for compilation, which improves performance. By making it easier to load and verify gate-level designs, the new flow improves confidence in silicon fidelity.
  • The combination of software and hardware improvements spanning the run time and debug cycles achieves 200% faster time-to-visibility.

These new Veloce emulation capabilities demonstrate how innovative software, running on powerful, qualified hardware and an extensible operating system, can target design risks faster than hardware-centric strategies. As emulation enters its fourth decade and expands across mainstream markets, the Veloce emulation platform has become a powerful resource across a range of hardware, software and system verification flows.

“Mentor continues to demonstrate its technology leadership through its application-based strategy for the Veloce emulation platform,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “These latest innovations accelerate overall verification throughput performance for our customers. The focus on software apps for specific SoC and system-level challenges is driving the future of emulation.”

About the Veloce emulation platform

The Veloce emulation platform is a core technology in the Mentor Enterprise Verification Platform (EVP) – a platform that boosts productivity in ASIC and SoC functional verification by combining advanced verification technologies in a comprehensive platform.

Now considered among the most versatile and powerful of verification tools, project teams use emulation for hardware debugging, hardware/software co-verification or integration, system- level prototyping, low-power verification and power estimation and performance characterization.

Today, at SPIE Advanced Lithography Conference (San Jose, Feb 21-25), nanoelectronics research center imec will present electrical results of DSA (directed self-assembly)-formed vias, gaining insight in the impact of DSA processing variations on electrical readout. The results accelerate learning towards implementation of DSA for via patterning at the N7 technology node and beyond.

DSA processes with cylinder-forming block copolymers (BCP) have gained attention for contact hole shrink applications with improved contact hole roughness, and for their potential to increase the contact hole density that is obtained with optical lithography. R&D efforts have focused on optimizing the process to obtain (pre-pattern) templates resulting in straight profiles after the DSA process, on increasing the feature density and on maximizing the open hole yield after pattern transfer. However, knowledge on electrical results from such DSA-based shrink processes is scarce.

Over recent years, imec has developed a templated grapho-epitaxy DSA flow for contact hole shrink and multiplication. Imec has applied this DSA flow to a short-loop test vehicle based on its 28nm node technology. Through testing the electrical performance of the DSA-formed vias, imec determined the via chain resistance as a function of process conditions including template dimension and BCP film thickness. Among a set of process conditions, increasing via chain resistance is observed with decreasing via CD (critical dimension). SEM images indicate high-quality via filling after metallization. The learning is now being applied to DSA via patterning in imec’s N7 technology.

Imec’s research into advanced patterning is performed in cooperation with imec’s core and strategic IC manufacturing partners including Samsung, Micron, Intel, Toshiba-Sandisk, SK Hynix, TSMC, GlobalFoundries and material and equipment makers.

imec dsa

SEMI today announced the “Call for Papers” for technical sessions and presentations for SEMICON Europa 2016 which takes place 25-27 October in Grenoble, France.

SEMICON Europa 2016 will feature more than 100 hours of technical sessions and presentations focused on critical industry topics that are shaping the design and manufacturing of semiconductors, MEMS, printed and flexible electronics, and other related technologies.  Abstracts for presentations are now being accepted for:

  • Advanced Packaging Conference: “The Balancing Act between Consumer and Harsh Environment Packaging”
  • Power Electronics Conference: “The Power Awakens”
  • 2016FLEX Europe: “Silicon Electronics + Flexible Systems Enabling New Markets”

The SEMICON Europa 2016 abstract submission deadline is 29 April.  Prospective presenters are invited to submit abstracts (1,000-2,000 characters). Material must be original, non-commercial and non-published. Abstracts must clearly detail the nature, scope, content, organization, key points, and significance of the proposed presentation.  Visit www.semiconeuropa.org or contact Christina Fritsch, SEMI Europe, at Tel: +49 30 303080770 or email [email protected].

Co-located and leveraging SEMICON Europa 2016, 2016FLEX Europe(formerly known as PE Europe)will also take place in Grenoble from 25-27 October.

SEMICON Europa and 2016FLEX Europe (now powered by SEMI’s Strategic Association Partner FlexTech) will attract over 5,500 attendees involved in the microelectronics supply chain, from equipment and material suppliers, IC manufacturers, system integrators to end users. Special programs this year focus on advanced and smart manufacturing (Industry 4.0), power electronics, imaging, electronics and materials for the medical and automotive applications, creating an opportunity to explore applications and manufacturing solutions for flexible, printed and hybrid electronics.

At this week’s SPIE Advanced Lithography Conference, nanoelectronics research center imec, Inpria, a company pioneering high performance EUV photoresists, and TEL, a semiconductor/flat panel display production equipment company, will present the first integrated patterning process for next generation high-resolution devices using a non-chemically amplified metal containing photoresist and EUV lithography.

The novel metal-oxide photoresist based process enables a significant process simplification and cost reduction compared to fab processes based on traditional organic EUV photoresists. The team transferred the metal-oxide photoresist process from lab to the fab, demonstrating manufacturing compatibility with standard fab equipment and excellent pattern transfer capability using ASML’s EUV NXE3300 full field scanner tool and imec’s integrated process line.

A negative tone metal-oxide EUV resist was developed by Inpria and integrated into imec’s 7nm BEOL process module on TEL’s etching system, more specifically as a block mask layer for metal patterning with pillar dimensions as small as 21nm. The intrinsic metal-oxide properties enabled the photoresist to also serve as a thin spin-on hard mask for the subsequent etching step. Moreover, because of the nature of the negative tone imaging of the photoresist, further simplification in the litho-etch patterning scheme is possible, as it eliminates the tone reversal scheme required by the conventional positive tone approaches for this block patterning layer.

imec euv advanced litho

A team of Korean researchers, affiliated with UNIST has recently pioneered in developing a new type of multilayered (Au NPs/TiO2/Au) photoelectrode that boosts the ability of solar water-splitting to produce hydrogen. According to the research team, this special photoelectrode, inspired by the way plants convert sunlight into energy is capable of absorbing visible light from the sun, and then using it to split water molecules (H2O) into hydrogen and oxygen.

This study is a collaboration among scientists, including Prof. Jeong Min Baik (School of Materials Science and Engineering, UNIST), Prof. Jae Sung Lee (School of Energy and Chemical Engineering, UNIST), Prof. Heon Lee (School of Materials Science and Engineering, Korea University), and Prof. Jonghwa Shin (Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology).

This multilayered photoelectrode takes the form of two-dimensional hybrid metal-dielectric structure, which mainly consists of three layers of gold (Au) film, ultrathin TiO2 layer (20 nm), and gold nanoparticles (Au NPs). In a study, reported in the January 21, 2016 issue of Nano Energy, the team reported that this promising photoelectrode shows high light absorption of about 90% in the visible range 380-700nm, as well as significant enhancement in photo-catalytic applications.

Many structural designs, such as hierarchical and branched assemblies of nanoscale materials have been suggested to increase the UV-visible absorption and to enhance water-splitting efficiency. However, through incorporation of plasmonic metal nanoparticles (i.e. Au) to TiO2 structures, their photoelectrodes have shown to enhance the photoactivity in the entire UV-visible region of solar spectrum when compared to the existing ones, the team reports.

Prof. Jeong Min Baik of UNIST (School of Materials Science and Engineering) states, “Several attemps have been made to use UV-based photoelectrodes for hydrogen production, but this is the first time to use the metal-dielectric hybrid-structured film with TiO2 for oxygen production.” Moreover, according to Prof. Baik, this special type of photoelectrode uses approximately 95% of the visible spectrum of sunlight, which makes up a substantial portion (40%) of full sunlight. He adds, “The developed technology is expected to improve hydrogen production efficiency.”

Prof. Heon Lee (Korean University) states, “This metal-dielectric hybrid-structured film is expected to further reduce the overall cost of producing hydrogen, as it doesn’t require complex operation processes.” He continues by saying, “Using nanoimprint lithography, mass production of hydrogen will be soon possible.”

Prof. Baik adds, “This simple system may serve as an efficient platform for solar energy conversion, utilizing the whole UV-visible range of solar spectrum based on two-dimensional plasmonic photoelectrodes.”

This work was supported by the Pioneer Center Program through the National Research Foundation of Korea (NRF) grant, funded by the Korean government (MSIP). It has been also equivalently funded by the 2014 Research Fund of UNIST (Ulsan National Institute of Science and Technology), as well as by the KIST-UNIST partnership program.

Heterostructures formed by different three-dimensional semiconductors form the foundation for modern electronic and photonic devices. Now, University of Washington scientists have successfully combined two different ultrathin semiconductors — each just one layer of atoms thick and roughly 100,000 times thinner than a human hair — to make a new two-dimensional heterostructure with potential uses in clean energy and optically-active electronics. The team, led by Boeing Distinguished Associate Professor Xiaodong Xu, announced its findings in a paper published Feb. 12 in the journal Science.

Senior author Xu and lead authors Kyle Seyler and Pasqual Rivera, both doctoral students in the UW physics department, synthesized and investigated the optical properties of this new type of semiconductor sandwich.

“What we’re seeing here is distinct from heterostructures made of 3-D semiconductors,” said Xu, who has joint appointments in the Department of Physics and the Department of Materials Science and Engineering. “We’ve created a system to study the special properties of these atomically thin layers and their potential to answer basic questions about physics and develop new electronic and photonic technologies.”

When semiconductors absorb light, pairs of positive and negative charges can form and bind together to create so-called excitons. Scientists have long studied how these excitons behave, but when they are squeezed down to the 2-D limit in these atomically thin materials, surprising interactions can occur.

While traditional semiconductors manipulate the flow of electron charge, this device allows excitons to be preserved in “valleys,” a concept from quantum mechanics similar to the spin of electrons. This is a critical step in the development of new nanoscale technologies that integrate light with electronics.

“It was already known that these ultrathin 2-D semiconductor have these unique properties that you cannot find in other 2-D or 3-D arrangements,” said Xu. “But as we show here, when we put these two layers together — one on top of the other — the interface between these sheets becomes the site of even more new physical properties, which you don’t see in each layer on its own or in the 3-D version.”

Xu and his team wanted to create and explore the properties of a 2-D semiconductor heterostructure made up of two different layers of material, a natural expansion of their previous studies on atomically thin junctions, as well as nanoscale lasers based on atomically thin layers of semiconductors. By studying how laser light interacts with this heterostructure, they gathered information about the physical properties at the atomically sharp interface.

“Many groups have studied the optical properties of single 2-D sheets,” said Seyler. “What we do here is carefully stack one material on top of another, and then study the new properties that arise at the interface.”

The team obtained two types of semiconducting crystals, tungsten diselenide (WSe2) and molybdenum diselenide (MoSe2), from collaborators at Oak Ridge National Laboratory. They used facilities developed in-house to precisely arrange two layers, one derived from each crystal, a process that took a few years to fully develop.

“But now that we know how to do it properly, we can make new ones in one or two weeks,” said Xu.

Getting these devices to emit light posed a unique challenge, due to the properties of electrons in each layer.

“Once you have these two sheets of material, an essential question is how to position the two layers together,” said Seyler. The electrons in each layer have unique spin and valley properties, and “how you position them — their twist angle — affects how they interact with light.”

By aligning the crystal lattices, the authors could excite the heterostructure with a laser and create optically active excitons between the two layers.

“These excitons at the interface can store valley information for orders of magnitude longer than either of the layers on their own,” said Rivera. “This long lifetime allows for fascinating effects which may lead to further optical and electronic applications with valley functionality.”

Now that they can efficiently make a semiconductor heterostructure out of 2-D materials, Xu and his team would like to explore a number of fascinating physical properties, including how exciton behavior varies as they change angles between the layers, the quantum properties excitons between layers and electrically driven light emission.

“There’s a whole industry that wants to use these 2-D semiconductors to make new electronic and photonic devices,” said Xu. “So we’re trying to study the fundamental properties of these new heterostructures for things like efficient laser technology, light-emitting diodes and light-harvesting devices. These will hopefully be useful for clean energy and information technology applications. It is quite exciting but there’s a lot work to do.”

Ever smaller, ever faster, ever cheaper – since the start of the computer age the performance of processors has doubled on average every 18 months. 50 years ago already, Intel co-founder Gordon E. Moore prognosticated this astonishing growth in performance. And Moore’s law seems to hold true to this day.

But the miniaturization of electronics is now reaching its physical limits. “Today already, transistors are merely a few nanometers in size. Further reductions are horrendously expensive,” says Professor Jonathan Finley, Director of the Walter Schottky Institute at TUM. “Improving performance is achievable only by replacing electrons with photons, i.e. particles of light.”

Photonics – the silver bullet of miniaturization

Data transmission and processing with light has the potential of breaking the barriers of current electronics. In fact, the first silicon-based photonics chips already exist. However, the sources of light for the transmission of data must be attached to the silicon in complicated and elaborate manufacturing processes. Researchers around the world are thus searching for alternative approaches.

Scientists at the TU Munich have now succeeded in this endeavor: Dr. Gregor Koblmüller at the Department of Semiconductor Quantum-Nanosystems has, in collaboration with Jonathan Finley, developed a process to deposit nanolasers directly onto silicon chips. A patent for the technology is pending.

The candidate Benedikt Mayer and Masters student Lisa Janker in an experiment at the molecular beam epitaxy in the Walter Schottky Institute of the Technische Universitaet Muenchen am teaching Suhl for semiconductor nanostructures and quantum devices, with Prof. Dr. Jonathan Finley; persons depicted (from left): Benedikt Mayer, Lisa Janker; Location: Walter Schottky Institute, Am Coulombwall 4, 85748 Garching, Germany; Date: 02/10/2016; CREDIT: Uli Benz / TU Muenchen

The candidate Benedikt Mayer and Masters student Lisa Janker in an experiment at the molecular beam epitaxy in the Walter Schottky Institute of the Technische Universitaet Muenchen am teaching Suhl for semiconductor nanostructures and quantum devices, with Prof. Dr. Jonathan Finley; persons depicted (from left): Benedikt Mayer, Lisa Janker; Location: Walter Schottky Institute, Am Coulombwall 4, 85748 Garching, Germany; Date: 02/10/2016; CREDIT: Uli Benz / TU Muenchen

Growing a III-V semiconductor onto silicon requires tenacious experimentation. “The two materials have different lattice parameters and different coefficients of thermal expansion. This leads to strain,” explains Koblmüller. “For example, conventional planar growth of gallium arsenide onto a silicon surface results therefore in a large number of defects.”

The TUM team solved this problem in an ingenious way: By depositing nanowires that are freestanding on silicon their footprints are merely a few square nanometers. The scientists could thus preclude the emerging of defects in the GaAs material.

Atom by atom to a nanowire

But how do you turn a nanowire into a vertical-cavity laser? To generate coherent light, photons must be reflected at the top and bottom ends of the wire, thereby amplifying the light until it reaches the desired threshold for lasing.

To fulfil these conditions, the researchers had to develop a simple, yet sophisticated solution: “The interface between gallium arsenide and silicon does not reflect light sufficiently. We thus built in an additional mirror – a 200 nanometer thick silicon oxide layer that we evaporated onto the silicon,” explains Benedikt Mayer, doctoral candidate in the team led by Koblmüller and Finley. “Tiny holes can then be etched into the mirror layer. Using epitaxy, the semiconductor nanowires can then be grown atom for atom out of these holes.”

Only once the wires protrude beyond the mirror surface they may grow laterally – until the semiconductor is thick enough to allow photons to jet back and forth to allow stimulated emission and lasing. “This process is very elegant because it allows us to position the nanowire lasers directly also onto waveguides in the silicon chip,” says Koblmüller.

GaAs nanowires on a silicon surface - Picture: Thomas Stettner / Philipp Zimmermann / TUM

GaAs nanowires on a silicon surface – CREDIT: Thomas Stettner / Philipp Zimmermann / TUM

Basic research on the path to applications

Currently, the new gallium arsenide nanowire lasers produce infrared light at a predefined wavelength and under pulsed excitation. “In the future we want to modify the emission wavelength and other laser parameters to better control temperature stability and light propagation under continuous excitation within the silicon chips,” adds Finley.

The team has just published its first successes in this direction. And they have set their sights firmly on their next goal: “We want to create an electric interface so that we can operate the nanowires under electrical injection instead of relying on external lasers,” explains Koblmüller.

“The work is an important prerequisite for the development of high-performance optical components in future computers,” sums up Finley. “We were able to demonstrate that manufacturing silicon chips with integrated nanowire lasers is possible.”

The research was funded by the German Research Foundation (DFG) through the TUM Institute for Advanced Study, the Excellence Cluster Nanosystems Initiative Munich (NIM) and the International Graduate School of Science and Engineering (IGSSE) of the TUM, as well as by IBM through an international postgraduate program.