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The IEEE Photonics Society will hold the fifth annual Optical Interconnects Conference on 9 – 11 May 2016 at the Hyatt Regency Mission Bay Spa & Marina in San Diego, CA.

Established as the Workshop on Interconnections within High Speed Digital Systems more than 25 years ago, the conference is designed to facilitate collaboration between the optical industry’s leading engineers and researchers to bring new optical interconnect architectures and technologies from research lab concepts to commercial realities, covering the complete spectrum of high performance interconnect technologies, from on-chip interconnects to enterprise-wide communications networks.

The conference program will cover the latest innovations in a wide range of interconnect challenges, including network systems, subsystems, architectures, applications and devices, delivered in more than 80 technical presentations that combine invited talks with refereed papers and poster sessions. A special evening panel session will be held on Monday evening to enable attendees to engage with expert panelists from industry and academia to exchange ideas about the future for optical interconnect technology.

“Optical interconnect strategies can only be fully realized when optimized at the system level,” said Lukas Chrostowski, University of British Columbia and Samuel Palermo, Texas A&M University, OI Conference 2016 General Co-Chairs. “This year’s Optical Interconnects Conference promises to be an important step in the exploration of the interconnect potential for future petascale and exascale platforms in supercomputers and datacenters.”

Papers will be accepted immediately, and the paper submission deadline is 24 January 2016. Authors will be notified in March of their paper status. Accepted papers are published on the IEEE Xplore digital library shortly after the conference, providing worldwide exposure for all authors.  The complete Call for Papers can be found at http://www.oi-ieee.org/call-for-papers.

When people think about Wide Band Gap (WBG) materials for power electronics applications, they usually think of GaN or SiC. This is a not a surprise: indeed SiC and GaN are currently the most advanced WBG technologies for power electronics applications. However, there are materials with an even larger band gap which can further increase power device performance. What is the development status of such innovative technologies? Are there already some products available on the market? What is the added-value of such materials?

Yole Développement (Yole) proposes a comprehensive overview of the whole WBG solutions dedicated to the power electronics industry. This survey is entitled SiC, GaN and other WBG materials for power electronics applications. Including a detailed analysis of the most advanced WBG materials, SiC and GaN, Yole’s report also highlights the added-value of disruptive technologies such as Ga2O3, diamond and AlN. Yole’s analysts detail the status of such new solutions and the related technology roadmap. The “More than Moore” market research and strategy consulting company also presents the technical and market challenges facing WBG players.

wbj materials

As the Si technology is reaching the theoretical limits, new semiconductor materials called wide band gap (WBG) is becoming the new choice for power electronics applications. Different WBG materials are SiC, GaN, Ga2O3, Diamond and AlN. The development status of these WBG materials varies from one to other. Indeed SiC and GaN-on-Si based power devices are commercially available today; the development of GaN-on-GaN power devices is ongoing; Ga2O3, diamond and AlN power devices are just at a primitive stage. And Yole details:

•  Thanks to its high band gap and doping possibility at room temperature, Ga2O3 has been proposed for power electronics applications. Compared to existing SiC and bulk GaN technology, GaSO3 key selling point is the possibility of using melt growth to make large, inexpensive wafers. Under this process, much little energy is used compared to energy-consuming methods employed for GaN and SiC bulk crystals and substrates creation: sublimation, vapor phase epitaxy, and high-pressure synthesis.

“It is estimated that the power dissipated per-unit-area of substrate at the time of production is just one-third of that associated with SiC sublimation, due to a lower growth temperature and a higher growth rate,” explained Dr. Hong Lin, Technology & Market Analyst at Yole. “As the same system configuration for sapphire is used, it should be possible to make cheaper Ga2O3 substrates than bulk GaN or SiC. If there is demand, it should be also possible to make 6” Ga2O3 substrates at a low unit cost. However, the demand is quite limited so far and the price remains high.”

•  Diamond is the ideal candidate for power electronic applications, thanks to a combination of unique properties. Electronics applications identified by Yole are Schottky diodes, transistors, etc. They require high-quality single-crystalline CVD diamond.

•  Having initially targeted UV LED applications but finding subpar demand, some AlN suppliers are now targeting the power market in order to diversify their activities. AlN’s key value proposition for power applications is the fact that it has the largest band gap.

Under its WBG materials report, Yole’s analysts reveal the state-of-the-art materials like SiC, GaN, Ga2O3, diamond, and AlN. They define a comprehensive technology roadmap and propose a deep understanding of the WBG materials evolution in the power electronics sector.

Scientists at the National University of Singapore (NUS) have demonstrated a new way of controlling electrons by confining them in a device made out of atomically thin materials, and applying external electric and magnetic fields. This research, published on Dec. 23, 2015 in the prestigious scientific journal Nature, was led by Professor Antonio Castro Neto and his research team at the Centre for Advanced 2D Materials (CA2DM) of the NUS Faculty of Science.

Almost all modern technology like motors, light bulbs and semiconductor chips runs on electricity, harnessing the flow of electrons through devices. Explained Prof Castro Neto, “Not only are electrons small and fast, they naturally repel each other due to their electric charge. They obey the strange laws of quantum physics, making it difficult to control their motion directly.”

To control electron behaviour, many semiconductor materials require chemical doping, where small amounts of a foreign material are embedded in the material to either release or absorb electrons, creating a change in the electron concentration that can in turn be used to drive currents.

However, chemical doping has limitations as a research technique, since it causes irreversible chemical change in the material being studied. The foreign atoms embedded into the material also disrupt its natural ordering, often masking important electronic states of the pure material.

The NUS research team was able to replicate the effects of chemical doping in this study by using only external electric and magnetic fields applied to an atomically thin material, titanium diselenide (TiSe2), encapsulated with boron-nitride (hBN). The researchers were able to control the behaviour of the electrons accurately and reversibly, making measurements that had been theoretical up to now. The thinness of the two materials was crucial, confining the electrons within the material to a two-dimensional layer, over which the electric and magnetic fields had a strong, uniform effect.

Scientists at the National University of Singapore have demonstrated a new way of controlling electrons by confining them in a device made out of an atomically thin material and applying external electric and magnetic fields. Credit: National University of Singapore

“In particular, we could also drive the material into a state called superconductivity, in which electrons move throughout the material without any heat or energy loss,” Prof Castro Neto said.

Because they are atomically thin, two-dimensional superconducting materials would have advantages over traditional superconductors, in applications such as smaller, portable magnetic resonance imaging (MRI) machines.

One specific goal of the NUS research team is to develop high-temperature two-dimensional superconducting materials. Current materials require an extremely cold temperature of -270°C to function, ruling out exciting applications such as lossless electrical lines, levitating trains and MRI machines.

The technique, which took the researchers two years to develop, will enable new experiments that shine light on high-temperature superconductivity and other solid-state phenomena of interest. With a wide range of materials awaiting testing, electric field doping greatly widens the possibilities of solid-state science.

Engineers at MIT have devised a new technique for trapping hard-to-detect molecules, using forests of carbon nanotubes.

The team modified a simple microfluidic channel with an array of vertically aligned carbon nanotubes — rolled lattices of carbon atoms that resemble tiny tubes of chicken wire. The researchers had previously devised a method for standing carbon nanotubes on their ends, like trees in a forest. With this method, they created a three-dimensional array of permeable carbon nanotubes within a microfluidic device, through which fluid can flow.

Now, in a study published this week in the Journal of Microengineering and Nanotechnology, the researchers have given the nanotube array the ability to trap certain particles. To do this, the team coated the array, layer by layer, with polymers of alternating electric charge.

“You can think of each nanotube in the forest as being concentrically coated with different layers of polymer,” says Brian Wardle, professor of aeronautics and astronautics at MIT. “If you drew it in cross-section, it would be like rings on a tree.”

Depending on the number of layers deposited, the researchers can create thicker or thinner nanotubes and thereby tailor the porosity of the forest to capture larger or smaller particles of interest.

The nanotubes’ polymer coating may also be chemically manipulated to bind specific bioparticles flowing through the forest. To test this idea, the researchers applied an established technique to treat the surface of the nanotubes with antibodies that bind to prostate specific antigen (PSA), a common experimental target. The polymer-coated arrays captured 40 percent more antigens, compared with arrays lacking the polymer coating.

Wardle says the combination of carbon nanotubes and multilayer coatings may help finely tune microfluidic devices to capture extremely small and rare particles, such as certain viruses and proteins.

“There are smaller bioparticles that contain very rich amounts of information that we don’t currently have the ability to access in point-of-care [medical testing] devices like microfluidic chips,” says Wardle, who is a co-author on the paper. “Carbon nanotube arrays could actually be a platform that could target that size of bioparticle.”

The paper’s lead author is Allison Yost, a former graduate student who is currently an engineer at Accion Systems. Others on the paper include graduate student Setareh Shahsavari; postdoc Roberta Polak; School of Engineering Professor of Teaching Innovation Gareth McKinley; professor of materials science and engineering Michael Rubner, and Raymond A. And Helen E. St. Laurent Professor of Chemical Engineering Robert Cohen.

A porous forest

Carbon nanotubes have been a subject of intense scientific study, as they possess exceptional electrical, mechanical, and optical properties. While their use in microfluidics has not been well explored, Wardle says carbon nanotubes are an ideal platform because their properties may be manipulated to attract certain nanometer-sized molecules. Additionally, carbon nanotubes are 99 percent porous, meaning a nanotube is about 1 percent carbon and 99 percent air.

“Which is what you need,” Wardle says. “You need to flow quantities of fluid through this material to shed all the millions of particles you don’t want to find and grab the one you do want to find.”

What’s more, Wardle says, a three-dimensional forest of carbon nanotubes would provide much more surface area on which target molecules may interact, compared with the two-dimensional surfaces in conventional microfluidics.

“The capture efficiency would scale with surface area,” Wardle notes.

A versatile array

The team integrated a three-dimensional array of carbon nanotubes into a microfluidic device by using chemical vapor deposition and photolithography to grow and pattern carbon nanotubes onto silicon wafers. They then grouped the nanotubes into a cylinder-shaped forest, measuring about 50 micrometers tall and 1 millimeter wide, and centered the array within a 3 millimeter-wide, 7-millimeter long microfluidic channel.

The researchers coated the nanotubes in successive layers of alternately charged polymer solutions in order to create distinct, binding layers around each nanotube. To do so, they flowed each solution through the channel and found they were able to create a more uniform coating with a gap between the top of the nanotube forest and the roof of the channel. Such a gap allowed solutions to flow over, then down into the forest, coating each individual nanotube. In the absence of a gap, solutions simply flowed around the forest, coating only the outer nanotubes.

After coating the nanotube array in layers of polymer solution, the researchers demonstrated that the array could be primed to detect a given molecule, by treating it with antibodies that typically bind to prostate specific antigen (PSA). They pumped in a solution containing small amounts of PSA and found that the array captured the antigen effectively, throughout the forest, rather than just on the outer surface of a typical microfluidic element.

Wardle says that the nanotube array is extremely versatile, as the carbon nanotubes may be manipulated mechanically, electrically, and optically, while the polymer coatings may be chemically altered to capture a wide range of particles. He says an immediate target may be biomarkers called exosomes, which are less than 100 nanometers wide and can be important signals of a disease’s progression.

“Science is really picking up on how much information these particles contain, and they’re sort of everywhere, but really hard to find, even with large-scale equipment,” Wardle says. “This type of device actually has all the characteristics and functionality that would allow you to go after bioparticles like exosomes and things that really truly are nanometer scale.”

By Dr. Phil Garrou, Contributing Editor

At the 12th annual 3D ASIP [Architectures for Semiconductor Interconnect and Packaging] Conference, sponsored by RTI Int, in Redwood City CA last week, Professor Mitsumasa Koyanagi of Tohoku University and Dr. Peter Ramm of Fraunhofer EMFT were the conference’s first recipients of the “3DIC Pioneer Award”.

Conference Chair Dr. Phil Garrou from Microelectronic Consultants of NC commented, “Since we are now more than a decade into the concerted effort to commercialize 2.5 and 3DIC technology it seemed appropriate to look back and document who actually led the way in this technically challenging effort. After significant study, we are convinced that the research groups in Tohoku University and Fraunhoffer – Munich were not only the first in the field, but also have continued their studies to this day to help commercialize this important leading edge technology.”

Professor Koyanagi (left) and Dr. Ramm (right) accept 3DIC Pioneering Award from conference chair Garrou.

Professor Koyanagi (left) and Dr. Ramm (right) accept 3DIC Pioneering Award from conference chair Garrou.

Profesor Koyanagi’s work started back with his seminal paper “Roadblocks in achieving 3-dimensional LSI” presented at the Symposium on Future Electronic Devices in 1989. His 1995 paper “Three dimensional Integration Technology Based on a Wafer Bonding Technique Using Micro Bumps” showed a process sequence similar to todays TSV etch, thin and bond for an image sensor circuit.

Dr. Ramm began his work in the early 1990s in collaboration with Siemens under the German sponsored R&D program “Cubic Integration – VIC”. Their paper “Performance Improvement of the Memory Hierarchy of RISC-Systems by Application of 3-D Technology,” which appeared in IEEE Trans on Components, Packaging and Manufacturing Technology in 1996 woke up the larger community to the possibilities of using 3DIC. A key patent from that era was USP 5,563,084 “Method of Making a 3 Dimensional Integrated Circuits” which issued in 1996.

The movement of charge carriers perpendicular to an electric driving field – even without a magnetic field – constitutes one of the most intriguing properties of carriers in solids. This anomalous velocity is at the origin of fascinating physical phenomena – with the spin Hall effect and the anomalous Hall effect being two prominent examples – and might be important for future spintronic applications or even new quantum computers. At the Physikalisch-Technische Bundesansstalt (PTB), the German National Metrology Institute, researchers have now succeeded in detecting the anomalous velocity in a semiconductor made of GaAs with a sub-picosecond time resolution. On the one hand, this work gives new insight into the microscopic origins of the anomalous velocity. On the other hand, it opens a new area of research for studying important physical effects on ultrafast time scales. The results have been published in the present issue of the renowned journal Physical Review Letters.

The anomalous velocity has different microscopic origins; one typically distinguishes between intrinsic and extrinsic contributions. The intrinsic contribution depends on the intrinsic properties of the solid (i.e. on the so-called Berry curvature), while the extrinsic contribution is caused by carrier scattering. Despite intensive investigations of the anomalous velocity in the past years, no simple technique has been developed which would enable the distinction between intrinsic and extrinsic contributions in a straightforward way. Moreover, the anomalous velocity has not yet been studied on ultrafast time scales on which factors such as coherent effects might significantly influence the anomalous velocity.

At PTB, the anomalous velocity has now, for the first time, been detected with sub-picosecond time resolution. For this purpose a semiconductor made of GaAs was excited by means of an optical femtosecond laser and a pulsed high-frequency electric field. While the optical laser pulse excites carriers with a particular spin direction, the high-frequency field accelerates these carriers. During this process, the carriers gain not only a velocity parallel to the electric field, but also the anomalous velocity perpendicular to it. This velocity was detected by a time-resolved study of the electromagnetic radiation emitted from the sample.

The PTB researchers have shown that the time-resolved detection of the anomalous velocity is very important for its further understanding. On the one hand, such investigations enable the distinction between intrinsic and extrinsic contributions, since these contributions have different time-domain shapes. On the other hand, it is now possible to investigate the dependence of the anomalous velocity on the momentum and energy of the carriers involved which, in turn, allows new studies of other important physical phenomena.

A team of engineers from Cornell University, the University of Notre Dame and the semiconductor company IQE has created gallium nitride (GaN) power diodes capable of serving as the building blocks for future GaN power switches — with applications spanning nearly all electronics products and electricity distribution infrastructures.

Power semiconductor devices are a critical part of the energy infrastructure — all electronics rely on them to control or convert electrical energy. Silicon-based semiconductors are rapidly approaching their performance limits within electronics, so materials such as GaN are being explored as potential replacements that may render silicon switches obsolete.

But along with having many desirable features as a material, GaN is notorious for its defects and reliability issues. So the team zeroed in on devices based on GaN with record-low defect concentrations to probe GaN’s ultimate performance limits for power electronics. They describe their results in a paper in the journal Applied Physics Letters, from AIP Publishing.

“Our engineering goal is to develop inexpensive, reliable, high-efficiency switches to condition electricity — from where it’s generated to where it’s consumed within electric power systems — to replace generations-old, bulky, and inefficient technologies,” said Zongyang Hu, a postdoc working in Professor Grace Huili Xing’s research group within the School of Electrical and Computer Engineering at Cornell University. “GaN-based power devices are enabling technologies to achieve this goal.”

The team examined semiconductor p-n junctions, made by joining p-type (free holes) and n-type (free electrons) semiconductor materials, which have direct applications in solar cells, light-emitting diodes (LEDs), rectifiers in circuits, and numerous variations in more complex devices such as power transistors. “For our work, high-voltage p-n junction diodes are used to probe the material properties of GaN,” Hu explained.

To describe how much the device’s current-voltage characteristics deviate from the ideal case in a defect-free semiconductor system, the team uses a “diode ideality factor.” This is “an extremely sensitive indicator of the bulk defects, interface and surface defects, and resistance of the device,” he added.

Defects exist within all materials, but at varying levels. “So one parameter we used to effectively describe the defect level in a material is the Shockley-Read-Hall (SRH) recombination lifetime,” Hu said.

SRH lifetime is the averaged time it takes injected electrons and holes in the junction to move around before recombining at defects. “The lower the defect level, the longer the SRH lifetime,” Hu explained. “It’s also interesting to note that for GaN, a longer SRH lifetime results in a brighter light emission produced by the diode.”

The work is significant because many researchers around the globe are working to find ways to make GaN materials reliable for use within future electronics. Due to the presence of defects with high concentrations in typical GaN materials today, GaN-based devices often operate at a fraction of what GaN is truly capable of.

It’s worth noting that, in 2014, a Nobel Prize in physics was awarded to three scientists for making seminal and breakthrough contributions to the field of GaN-based LEDs. Though operating at compromised conditions, GaN LEDs are helping to shift the global lighting industry to a much more energy-efficient, solid-state lighting era.

The work led by Xing at Cornell University is the first report of GaN p-n diodes with near-ideal performance in all aspects simultaneously: a unity ideality factor, avalanche breakdown voltage, and about a two-fold improvement in device figure-of-merits over previous records.

“Our results are an important step toward understanding the intrinsic properties and the true potential of GaN,” Hu noted. “And these achievements are only possible in high-quality GaN device structures (an effort led by IQE engineers) prepared on high-quality GaN bulk substrates and with precisely tuned fabrication technologies (an effort led by Dr. Kazuki Nomoto, a research associate at Cornell University).”

One big surprise for the team came in the form of unexpectedly low differential-on-resistance of the GaN diode. “It’s as if the body of the entire p-n diode is transparent to the current flow without resistance,” he said. “We believe this is due to high-level injection of minority carriers and their long lifetime, and are exploring it further.”

The team’s work is part of the U.S. Department of Energy’s (DOE) Advanced Research Projects Agency-Energy (ARPA-E) “SWITCHES” program, monitored by Dr. Timothy Heidel. “Leading one of these projects, we at Cornell, in collaboration with our industrial partners IQE, Qorvo, and UTRC, have established an integrated plan to develop three terminal GaN power transistors, package them, and insert them into circuits and products,” Xing said.

Beyond the DOE ARPA-E project, the team is open to collaboration with any researchers or companies interested in helping drive GaN power electronics to its fruition.

Applied Materials, Inc. today announced that Dr. Chorng-Ping Chang, who leads the company’s strategic external research with universities and industry consortia, has been named a 2016 IEEE Fellow. Dr. Chang is being recognized for his contributions to “replacement gate and shallow trench isolation for CMOS technology,” which have had a profound impact on the advancement of integrated circuit (IC) fabrication. The IEEE Grade of Fellow is conferred by the IEEE Board of Directors upon a person with an outstanding record of accomplishments in any of the IEEE fields of interest. IEEE Fellow is the highest grade of membership and is recognized by the technical community as a prestigious honor and an important career achievement. The total number selected in any one year cannot exceed one-tenth of one-percent of the total voting membership.

“Chorng-Ping’s brilliant work helped the industry adopt novel methods in CMOS scaling and made important contributions to the performance, functionality and size of the electronic products we use every day,” said Dr. Om Nalamasu, senior vice president and CTO of Applied Materials. “I commend him on this well-deserved honor and for his efforts leading Applied Materials’ collaborations with universities and consortia.”  

Dr. Chang’s outstanding technical contributions and extensive semiconductor industry community service span nearly three decades. While working at Bell Laboratories he led pioneering research that helped the industry through one of the most significant transitions in the history of CMOS technology – the shift from the gate-first to the gate-last (replacement gate) process. His work on extending the use of replacement gate technology continued at Applied Materials, and today virtually all state-of-the-art CMOS logic devices, including FinFET transistors, use replacement gate technology. In addition, early on in his career Dr. Chang made pivotal contributions in deposition, etching and advanced plasma processing technologies.

Another critical area where Dr. Chang made significant contributions is advanced shallow trench isolation (STI). He led an early detailed study that demonstrated how changing the shape of the top trench corners helped resolve serious issues of defect density, junction leakage and device threshold voltage control. This research had a long-term impact on the robustness and extendibility of STI in mainstream CMOS manufacturing, to the extent that major CMOS process technologies introduced in recent years have used STI corner engineering techniques developed by Dr. Chang and his team.

Dr. Chang has served the IEEE community in several facets throughout his career, including as editor of IEEE Electron Device Letters for 12 years. He has also been a member of the program committees of various international technical conferences on IC technology, and is currently the U.S. Chair of the International Technology Roadmap for Semiconductors (ITRS) Process, Integration, Devices and Structures Chapter. Dr. Chang holds a bachelor’s degree from National Tsing Hua University and a Ph.D. in engineering from the University of California, Berkeley.

At last week’s IEEE International Electron Devices Meeting 2015, nano-electronics research center imec presented three novel aluminum gallium nitride (AlGaN)/ gallium nitride (GaN) stacks featuring optimized low dispersion buffer designs. Moreover, imec optimized the epitaxial p-GaN growth process on 200mm silicon wafers, achieving e-mode devices featuring beyond state-of-the-art high threshold voltage (Vt) and high drive current (Id).

To achieve a good, current-collapse-free device operation in AlGaN/GaN-on-Silicon (Si) devices, dispersion must be kept to a minimum. Trapped charges in the buffer between the GaN-based channel and the silicon substrate are known to be a critical factor in causing dispersion. Imec compared the impact of different types of buffers on dispersion and optimized three types: a classic step-graded buffer, a buffer with low-temperature AlN interlayers, and a super lattice buffer. These three types of buffers were optimized for low dispersion, leakage and breakdown voltage over a wide temperature range and bias conditions.

Imec also optimized the epitaxial p-GaN growth process demonstrating improved electrical performance of p-GaN HEMTs, achieving a beyond state-of-the-art combination of high threshold voltage, low on-resistance and high drive current (Vt >2V, RON = 7 Ω.mm and Id >0.4A/mm at 10V). The P-GaN HEMT results outperformed their MISHEMT counterparts.

Imec’s GaN-on-Si R&D program aims at bringing this technology towards industrialization. Imec’s offering includes a complete 200mm CMOS-compatible 200V GaN process line that features excellent specs on e-mode devices. Imec’s program allows partners early access to next-generation devices and power electronics processes, equipment and technologies, and speed up innovation at shared costs. Current R&D focuses on improving the performance and reliability of imec’s e-mode devices, while in parallel pushing the boundaries of the technology through innovation in substrate technology, higher levels of integration and exploration of novel device architectures.

“Imec’s presentations at the renowned IEDM meeting last week are a testament to the capabilities, sophistication, and maturity of our 200mm GaN-on-Silicon platform,” stated Rudi Cartuyvels, executive vice president of smart systems and energy technology at imec. “Building upon this success, we are now working with our GaN partners to implement and transfer specific device customizations. in parallel, we are exploring alternative substrate technologies to further push the boundaries of the GaN technology.”

At this week’s IEEE IEDM conference, nano-electronics research center imec demonstrates record enhancement of novel InGaAs Gate-All-Around (GAA) channel devices integrated on 300mm Silicon and explores emerging tunnel devices based on optimization of the same III-V compound semiconductor.

III-V-on-Si GAA devices with a record peak transconductance at 0.5V has been achieved by optimizing both the channel epitaxy quality and the gate-channel passivation. In search of device technologies beyond FinFETs and GAA-nanowires for sub-0.5V operations, imec investigates InGaAs Tunnel-FET (TFETs). Homo-junction III-V TFETs achieving a record ON-state current (ION) and superior subthreshold swing have been demonstrated. These results increase the knowledge on the impact of defectivity and channel optimization on device operations, and pave the way to advanced logic devices based on III-V-On-Si for high performance or ultra-low power applications.

Imec’s R&D program on advanced logic scaling is targeting the new and mounting challenges for performance, power, cost, and density scaling for future process technologies. One of the directions that imec is following, looks into beyond-Si solutions, such as integrating high-mobility materials into the channels of CMOS devices to increase their performance, and the integration challenges of these materials with silicon. Gate-All-Around Nanowire (GAA NW) FETs have been proven to offer significantly better short-channel electrostatics, and quantum-well FinFETs (with SiGe, Ge, or III-V channels) achieving high carrier mobility, are interesting concepts to increase device performance. Tunnel FETs, on the other hand, offering a steeper than 60mV/dec subthreshold swing, are a promising option for ultra-low power applications.

At IEDM, imec presented gate-all-around InGaAs Nanowire FETs (Lg=50nm) that performed at an average peak transconductance (gm) of 2200µS/µm with a SSSAT of 110mV/dec. Imec succeeded in increasing the performance by gate stack engineering using a novel gate stack ALD inter-layer (IL) material developed by ASM, and high pressure annealing. The novel IL/HfO2 stack achieved a 2.2 times higher gm for a device with a gate length (Lg) of 50nm, compared to the reference Al2O3/HfO2 stack.

Imec also presented a planar InGaAs homo-junction TFET with 70 percent Indium (In) content. The increase of In content from 53 to 70 percent in a 8nm channel, was found to significantly boost the performance of the device. A record ON-state current (ION) of 4µA/µm (IOFF = 100pA/µm, Vdd = 0.5V and Vd = 0.3V) with a minimum subthreshold swing (SSmin) of 60mV/dec at 300k was obtained for a planar homo-junction TFET device. It was also shown that subthreshold swing and transconductance in TFET devices were more immune to positive bias temperature instability (PBTI) compared to MOSFET devices.

“Imec’s R&D enables Moore’s Law beyond the 5nm technology node through 3 approaches. First, we are tackling the technology challenges to extend silicon CMOS devices towards smaller nodes. At the same time, we research into disruptive heterogeneous solutions for beyond-silicon CMOS devices to increase performance and introduce new functionalities. Lastly, imec pursues emerging beyond-CMOS devices and systems such as spintronics to investigate further functional scaling beyond device-density-driven scaling,” stated Aaron Thean, vice president and director of imec’s advanced logic R&D program. “Boosting the performance of advanced compound semiconductor logic devices is extremely important, and these results support the quest of the semiconductor industry to find solutions that enable 5nm technology nodes and beyond.”

“ASM and imec have a long history of R&D collaboration using many of ASM’s products and advanced deposition and thermal processes,” says Ivo Raaijmakers, ASM CTO and Director of R&D. “As a leader in ALD, we are glad to see this breakthrough new ALD material now demonstrated in imec’s high mobility devices and presented at IEDM 2015.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, Panasonic, Qualcomm, Samsung, SK Hynix, Sony and TSMC.

TEM of complete gate-all-around InGaAs Nanowire FET and HRTEM of the gatestack

TEM of complete gate-all-around InGaAs Nanowire FET and HRTEM of the gatestack