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Graphene, an atom-thick material with extraordinary properties, is a promising candidate for the next generation of dramatically faster, more energy-efficient electronics. However, scientists have struggled to fabricate the material into ultra-narrow strips, called nanoribbons, that could enable the use of graphene in high-performance semiconductor electronics.

Now, University of Wisconsin-Madison engineers have discovered a way to grow graphene nanoribbons with desirable semiconducting properties directly on a conventional germanium semiconductor wafer. This advance could allow manufacturers to easily use graphene nanoribbons in hybrid integrated circuits, which promise to significantly boost the performance of next-generation electronic devices. The technology could also have specific uses in industrial and military applications, such as sensors that detect specific chemical and biological species and photonic devices that manipulate light.

In a paper published Aug. 10 in the journal Nature Communications, Michael Arnold, an associate professor of materials science and engineering at UW-Madison, Ph.D. student Robert Jacobberger, and their collaborators describe their new approach to producing graphene nanoribbons. Importantly, their technique can easily be scaled for mass production and is compatible with the prevailing infrastructure used in semiconductor processing.

“Graphene nanoribbons that can be grown directly on the surface of a semiconductor like germanium are more compatible with planar processing that’s used in the semiconductor industry, and so there would be less of a barrier to integrating these really excellent materials into electronics in the future,” Arnold says.

Graphene, a sheet of carbon atoms that is only one atom in thickness, conducts electricity and dissipates heat much more efficiently than silicon, the material most commonly found in today’s computer chips. But to exploit graphene’s remarkable electronic properties in semiconductor applications where current must be switched on and off, graphene nanoribbons need to be less than 10 nanometers wide, which is phenomenally narrow. In addition, the nanoribbons must have smooth, well-defined “armchair” edges in which the carbon-carbon bonds are parallel to the length of the ribbon.

Researchers have typically fabricated nanoribbons by using lithographic techniques to cut larger sheets of graphene into ribbons. However, this “top-down” fabrication approach lacks precision and produces nanoribbons with very rough edges.

Another strategy for making nanoribbons is to use a “bottom-up” approach such as surface-assisted organic synthesis, where molecular precursors react on a surface to polymerize nanoribbons. Arnold says surface-assisted synthesis can produce beautiful nanoribbons with precise, smooth edges, but this method only works on metal substrates and the resulting nanoribbons are thus far too short for use in electronics.

To overcome these hurdles, the UW-Madison researchers pioneered a bottom-up technique in which they grow ultra-narrow nanoribbons with smooth, straight edges directly on germanium wafers using a process called chemical vapor deposition. In this process, the researchers start with methane, which adsorbs to the germanium surface and decomposes to form various hydrocarbons. These hydrocarbons react with each other on the surface, where they form graphene.

Arnold’s team made its discovery when it explored dramatically slowing the growth rate of the graphene crystals by decreasing the amount of methane in the chemical vapor deposition chamber. They found that at a very slow growth rate, the graphene crystals naturally grow into long nanoribbons on a specific crystal facet of germanium. By simply controlling the growth rate and growth time, the researchers can easily tune the nanoribbon width be to less than 10 nanometers.

“What we’ve discovered is that when graphene grows on germanium, it naturally forms nanoribbons with these very smooth, armchair edges,” Arnold says. “The widths can be very, very narrow and the lengths of the ribbons can be very long, so all the desirable features we want in graphene nanoribbons are happening automatically with this technique.”

The nanoribbons produced with this technique start nucleating, or growing, at seemingly random spots on the germanium and are oriented in two different directions on the surface. Arnold says the team’s future work will include controlling where the ribbons start growing and aligning them all in the same direction.

The researchers are patenting their technology through the Wisconsin Alumni Research Foundation. The research was primarily supported by the Department of Energy’s Basic Energy Sciences program.

A Korean team of scientists tune BP’s band gap to form a superior conductor, allowing for the application to be mass produced for electronic and optoelectronics devices

The research team operating out of Pohang University of Science and Technology (POSTECH), affiliated with the Institute for Basic Science’s (IBS) Center for Artificial Low Dimensional Electronic Systems (CALDES), reported a tunable band gap in BP, effectively modifying the semiconducting material into a unique state of matter with anisotropic dispersion. This research outcome potentially allows for great flexibility in the design and optimization of electronic and optoelectronic devices like solar panels and telecommunication lasers.

The research team operating out of Pohang University of Science and Technology, affiliated with the Institute for Basic Science’s Center for Artificial Low Dimensional Electronic Systems, reported a tunable band gap in BP, effectively modifying the semiconducting material into a unique state of matter with anisotropic dispersion. This research outcome potentially allows for great flexibility in the design and optimization of electronic and optoelectronic devices like solar panels and telecommunication lasers. Credit: Institute for Basic Science

To truly understand the significance of the team’s findings, it’s instrumental to understand the nature of two-dimensional (2-D) materials, and for that one must go back to 2010 when the world of 2-D materials was dominated by a simple thin sheet of carbon, a layered form of carbon atoms constructed to resemble honeycomb, called graphene. Graphene was globally heralded as a wonder-material thanks to the work of two British scientists who won the Nobel Prize for Physics for their research on it.

Graphene is extremely thin and has remarkable attributes. It is stronger than steel yet many times lighter, more conductive than copper and more flexible than rubber. All these properties combined make it a tremendous conductor of heat and electricity. A defect-free layer is also impermeable to all atoms and molecules. This amalgamation makes it a terrifically attractive material to apply to scientific developments in a wide variety of fields, such as electronics, aerospace and sports. For all its dazzling promise there is however a disadvantage; graphene has no band gap.

Stepping stones to a unique state

A material’s band gap is fundamental to determining its electrical conductivity. Imagine two river crossings, one with tightly-packed stepping-stones, and the other with large gaps between stones. The former is far easier to traverse because a jump between two tightly-packed stones requires less energy. A band gap is much the same; the smaller the gap the more efficiently the current can move across the material and the stronger the current.

Graphene has a band gap of zero in its natural state, however, and so acts like a conductor; the semiconductor potential can’t be realized because the conductivity can’t be shut off, even at low temperatures. This obviously dilutes its appeal as a semiconductor, as shutting off conductivity is a vital part of a semiconductor’s function.

Birth of a revolution

Phosphorus is the fifteenth element in the periodic table and lends its name to an entire class of compounds. Indeed it could be considered an archetype of chemistry itself. Black phosphorus is the stable form of white phosphorus and gets its name from its distinctive color. Like graphene, BP is a semiconductor and also cheap to mass produce. The one big difference between the two is BP’s natural band gap, allowing the material to switch its electrical current on and off. The research team tested on few layers of BP called phosphorene which is an allotrope of phosphorus.

Keun Su Kim, an amiable professor stationed at POSTECH speaks in rapid bursts when detailing the experiment, “We transferred electrons from the dopant – potassium – to the surface of the black phosphorus, which confined the electrons and allowed us to manipulate this state. Potassium produces a strong electrical field which is what we required to tune the size of the band gap.”

This process of transferring electrons is known as doping and induced a giant Stark effect, which tuned the band gap allowing the valence and conductive bands to move closer together, effectively lowering the band gap and drastically altering it to a value between 0.0 ~ 0.6 electron Volt (eV) from its original intrinsic value of 0.35 eV. Professor Kim explained, “Graphene is a Dirac semimetal. It’s more efficient in its natural state than black phosphorus but it’s difficult to open its band gap; therefore we tuned BP’s band gap to resemble the natural state of graphene, a unique state of matter that is different from conventional semiconductors.”

The potential for this new improved form of black phosphorus is beyond anything the Korean team hoped for, and very soon it could potentially be applied to several sectors including engineering where electrical engineers can adjust the band gap and create devises with the exact behavior desired. The 2-D revolution, it seems, has arrived and is here for the long run.

Nano-electronics research center imec announced today that it is extending its Gallium Nitride-on-Silicon (GaN-on-Si) R&D program, and is now offering joint research on GaN-on-Si 200mm epitaxy and enhancement mode device technology. The extended R&D initiative includes exploration of novel substrates to improve the quality of the epitaxial layers, new isolation modules to increase the level of integration, and the development of advanced vertical devices. Imec welcomes new partners interested in next generation GaN technologies and companies looking for low-volume manufacturing of GaN-on-Si devices to enable the next generation of more efficient and compact power converters.

next gen GaN imec

GaN technology offers faster switching power devices with higher breakdown voltage and lower on-resistance than silicon, making it an outstanding material for advanced power electronic components. Imec’s R&D program on GaN-on-Si was launched to develop a GaN-on-Si process and bring GaN technology towards industrialization. Building on imec’s excellent track record in GaN epi-layer growth, new device concepts and CMOS device integration, imec has now developed a complete 200mm CMOS-compatible GaN process line. Imec’s GaN-on-Si technology is reaching maturity, and companies can gain access to the platform by joining imec’s GaN-on-Si industrial affiliation program (IIAP). The process line is also open to fabless companies interested in low-volume production of GaN-on-Si devices tailored to their specific needs, through dedicated development projects.

Imec’s portfolio includes three types of buffers optimized for breakdown voltage and low traps-related phenomena (i.e. current dispersion): a step graded AlGaN buffer, a super lattice buffer, and a buffer with low-temperature AlN interlayers. Imec explored side-by-side enhancement mode power devices of the MISHEMT and p-GaN HEMT type, as well as a gate-edge terminated Schottky power diode featuring low reverse leakage and low turn-on voltage.

The latest generation of imec enhancement mode power devices shows a threshold voltage beyond +2V, an on-resistance below 10 ohm mm and output current beyond 450 mA/mm. These devices represents the state of the art of enhancement mode power devices.

In this next phase of the GaN program, imec is focusing on further improving the performance and reliability of its current power devices, while in parallel pushing the boundaries of the technology through innovation in substrate technology, higher levels of integration and exploration of novel device architectures.

“Since the program’s launch in July 2009, we have benefited from strong industry engagement, including participation from IDMs, epi-vendors and equipment and material suppliers. This underscores the industrial relevance of our offering,” stated Rudi Cartuyvels, executive vice president of smart systems at imec. “Interested companies are invited to become a partner and actively participate in our program. Imec’s open innovation model allows companies to have early access to next-generation devices and power electronics processes, equipment and technologies and speed up innovation at shared cost.”

Scientists at Rice University have created a solid-state memory technology that allows for high-density storage with a minimum incidence of computer errors.

The memories are based on tantalum oxide, a common insulator in electronics. Applying voltage to a 250-nanometer-thick sandwich of graphene, tantalum, nanoporous tantalum oxide and platinum creates addressable bits where the layers meet. Control voltages that shift oxygen ions and vacancies switch the bits between ones and zeroes.

The discovery by the Rice lab of chemist James Tour could allow for crossbar array memories that store up to 162 gigabits, much higher than other oxide-based memory systems under investigation by scientists. (Eight bits equal one byte; a 162-gigabit unit would store about 20 gigabytes of information.)

A schematic shows the layered structure of tantalum oxide, multilayer graphene and platinum used for a new type of memory developed at Rice University. The memory device overcomes crosstalk problems that cause read errors in other devices. Credit: Tour Group/Rice University

Details appear online in the American Chemical Society journal Nano Letters.

Like the Tour lab’s previous discovery of silicon oxide memories, the new devices require only two electrodes per circuit, making them simpler than present-day flash memories that use three. “But this is a new way to make ultradense, nonvolatile computer memory,” Tour said.

Nonvolatile memories hold their data even when the power is off, unlike volatile random-access computer memories that lose their contents when the machine is shut down.

Modern memory chips have many requirements: They have to read and write data at high speed and hold as much as possible. They must also be durable and show good retention of that data while using minimal power.

Tour said Rice’s new design, which requires 100 times less energy than present devices, has the potential to hit all the marks.

“This tantalum memory is based on two-terminal systems, so it’s all set for 3-D memory stacks,” he said. “And it doesn’t even need diodes or selectors, making it one of the easiest ultradense memories to construct. This will be a real competitor for the growing memory demands in high-definition video storage and server arrays.”

The layered structure consists of tantalum, nanoporous tantalum oxide and multilayer graphene between two platinum electrodes. In making the material, the researchers found the tantalum oxide gradually loses oxygen ions, changing from an oxygen-rich, nanoporous semiconductor at the top to oxygen-poor at the bottom. Where the oxygen disappears completely, it becomes pure tantalum, a metal.

The researchers determined three related factors give the memories their unique switching ability.

First, the control voltage mediates how electrons pass through a boundary that can flip from an ohmic (current flows in both directions) to a Schottky (current flows one way) contact and back.

Second, the boundary’s location can change based on oxygen vacancies. These are “holes” in atomic arrays where oxygen ions should exist, but don’t. The voltage-controlled movement of oxygen vacancies shifts the boundary from the tantalum/tantalum oxide interface to the tantalum oxide/graphene interface. “The exchange of contact barriers causes the bipolar switching,” said Gunuk Wang, lead author of the study and a former postdoctoral researcher at Rice.

Third, the flow of current draws oxygen ions from the tantalum oxide nanopores and stabilizes them. These negatively charged ions produce an electric field that effectively serves as a diode to hinder error-causing crosstalk. While researchers already knew the potential value of tantalum oxide for memories, such arrays have been limited to about a kilobyte because denser memories suffer from crosstalk that allows bits to be misread.

The graphene does double duty as a barrier that keeps platinum from migrating into the tantalum oxide and causing a short circuit.

Tour said tantalum oxide memories can be fabricated at room temperature. He noted the control voltage that writes and rewrites the bits is adjustable, which allows a wide range of switching characteristics.

Wang said the remaining hurdles to commercialization include the fabrication of a dense enough crossbar device to address individual bits and a way to control the size of the nanopores.

Toshiba America Electronic Components, Inc. (TAEC) today unveiled the new generation of BiCS FLASH, a three-dimensional (3D) stacked cell structure flash memory. The new device is the world’s first 256-gigabit (Gb4) (32 gigabyte) 48-layer BiCS FLASH device and also deploys industry-leading 3-bit-per-cell TLC (triple-level cell) technology. Sample shipments will start in September.

toshiba storage pic

BiCS FLASH is based on a leading-edge 48-layer stacking process that surpasses the capacity of mainstream two dimensional NAND flash memory, while enhancing write/erase reliability endurance and boosting write speeds. The new 256Gb device is suited for diverse applications, including consumer SSDs, smartphones, tablets, memory cards, and enterprise SSDs for data centers.

Since announcing the prototype BiCS FLASH technology in June 2007, Toshiba has continued development towards optimization for mass production. To meet further growth in the flash memory market in 2016 and beyond, Toshiba is proactively promoting migration to BiCS FLASH by rolling out a product portfolio that emphasizes large capacity applications, such as SSDs.

“From day one, Toshiba’s strategy has been to extend our floating gate technology, which features the world’s smallest 15nm 128Gb die ,” noted Scott Nelson, senior vice president of TAEC’s Memory Business Unit. “Our announcement of BiCS FLASH, the industry’s first 48-layer 3D technology, is very significant in that we are enabling a competitive, smooth migration to 3D flash memory – to support the storage market’s demand for ever-increasing densities.”

Toshiba has a long-standing commitment to flash memory, and is currently readying for mass production of BiCS FLASH in the new Fab2 at Yokkaichi Operations, its production site for NAND flash memories. Fab2 will be completed in the first half of 2016.

Graphene has been called a wonder material, capable of performing great and unusual material acrobatics. Boron nitride nanotubes are no slackers in the materials realm either, and can be engineered for physical and biological applications. However, on their own, these materials are terrible for use in the electronics world. As a conductor, graphene lets electrons zip too fast–there’s no controlling or stopping them–while boron nitride nanotubes are so insulating that electrons are rebuffed like an overeager dog hitting the patio door.

But together, these two materials make a workable digital switch, which is the basis for controlling electrons in computers, phones, medical equipment and other electronics.

Yoke Khin Yap, a professor of physics at Michigan Technological University, has worked with a research team that created these digital switches by combining graphene and boron nitride nanotubes. The journal Scientific Reports recently published their work.

“The question is: How do you fuse these two materials together?” Yap says. The key is in maximizing their existing chemical structures and exploiting their mismatched features.

Hair-like boron nitride nanotubes intersect a sheet of graphene to create a digital switch. Credit: Michigan Tech, Yoke Khin Yap

Hair-like boron nitride nanotubes intersect a sheet of graphene to create a digital switch. Credit: Michigan Tech, Yoke Khin Yap

Nanoscale Tweaks

Graphene is a molecule-thick sheet of carbon atoms; the nanotubes are like straws made of boron and nitrogen. Yap and his team exfoliate graphene and modify the material’s surface with tiny pinholes. Then they can grow the nanotubes up and through the pinholes. Meshed together like this, the material looks like a flake of bark sprouting erratic, thin hairs.

“When we put these two aliens together, we create something better,” Yap says, explaining that it’s important that the materials have lopsided band gaps, or differences in how much energy it takes to excite an electron in the material. “When we put them together, you form a band gap mismatch–that creates a so-called ‘potential barrier’ that stops electrons.”

The band gap mismatch results from the materials’ structure: graphene’s flat sheet conducts electricity quickly, and the atomic structure in the nanotubes halts electric currents. This disparity creates a barrier, caused by the difference in electron movement as currents move next to and past the hair-like boron nitride nanotubes. These points of contact between the materials–called heterojunctions–are what make the digital on/off switch possible.

“Imagine the electrons are like cars driving across a smooth track,” Yap says. “They circle around and around, but then they come to a staircase and are forced to stop.”

Yap and his research team have also shown that because the materials are respectively so effective at conducting or stopping electricity, the resulting switching ratio is high. In other words, how fast the materials can turn on and off is several orders of magnitude greater than current graphene switches. In turn, this speed could eventually quicken the pace of electronics and computing.

Solving the Semiconductor Dilemma

To get to faster and smaller computers one day, Yap says this study is a continuation of past research into making transistors without semiconductors. The problem with semiconductors like silicon is that they can only get so small, and they give off a lot of heat; the use of graphene and nanotubes bypasses those problems. In addition, the graphene and boron nitride nanotubes have the same atomic arrangement pattern, or lattice matching. With their aligned atoms, the graphene-nanotube digital switches could avoid the issues of electron scattering.

“You want to control the direction of the electrons,” Yap explains, comparing the challenge to a pinball machine that traps, slows down and redirects electrons. “This is difficult in high speed environments, and the electron scattering reduces the number and speed of electrons.”

Much like an arcade enthusiast, Yap says he and his team will continue trying to find ways to outsmart or change the pinball set-up of graphene to minimize electron scattering. And one day, all their tweaks could make for faster computers–and digital pinball games–for the rest of us.

By Zvi Or-Bach, President and CEO, MonolithIC 3D Inc.

SEMICON West 2015 had a strong and rich undercurrent – the roadmap forward is most certainly 3DIC. Yes, the industry can and we will keep pushing dimensions down, but for most designs the path forward would be “More than Moore.” As Globalfoundries’ CEO Jha recently voiced: It’s clear that More-than-Moore is now mainstream rather than niche. Really it is leading-edge pure digital that is the niche. Instead the high-cost leading edge processes are really niche processes optimized for applications in data centers or for high computational loads, albeit niches with volumes of hundreds of millions of units per year.”

CEA Leti’s CEO in her opening presentation for the SEMICON West–Leti day presented the following slide:

3DIC CEA-Leti

Calling the 28nm as the ‘switch node’ from the homogeneous march of the industry with dimensional scaling to the bifurcation we now see, where “More than Moore” approaches such as SOI and 3DIC are taking on an important portion of future progress.

CEA Leti went even further by dedicating its SEMICON West day entirely to 3D technologies, as is seen in their invitation:

leti day logo

GOING VERTICAL WITH LETI: Solutions to new applications using 3D technologies

  • Welcome– Leti’s 3D integration for tomorrow’s devices > N Semeria
  • CoolCubeTM: 3D sequential integration to maintain Moore’s Law > Faynot
  • Photonics: why 3D integration is mandatory > Metras
  • Computing: 3D technology for better performance > Cheramy
  • Lighting: 3D integration for cost effectiveness > C Robin
  • Nanocharacterization for 3D Bleuet
  • Conclusion– Silicon Impulse > N Semeria

Olivier Faynot, Microelectronic Section Manager at LETI, presented the following slide in his CoolCube presentation.

3DIC Cea-Leti coolcub

This illustrates that monolithic 3DIC of 4 tiers could provide the equivalent scaling value of the 5nm node at a far less infrastructure or NRE cost. As the slide states: “New scaling path, compared to 2D.” The time is now for monolithic 3D approaches to take hold a grow.

A similar message is projected by a slide presented by An Steegen of IMEC at their pre-SEMICON Technology Forum:

3DIC device stacking

The same assessment was also presented by Intel’s Jeff Groff from his synopsis of Intel’s Q2 call: “In summary, it seems that Intel is executing fairly well on the process technology side of the business considering the ever increasing difficulty of pushing forward with Moore’s Law. We can expect exciting new structures and materials (just maybe not at 10nm) and an increasing importance of 3-D structures in both logic and memory fabrication.” This resonates with our blog Intel Calls for 3D IC, and was recently voiced by Intel process guru Mark Bohr: “Bohr predicted that Moore’s Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.” Bohr’s ISSCC slide from earlier this year reasserts this:

3DIC ISSCC

The key two concerns regarding 3DIC stacking using TSV are (a) Cost, noted in the slide above “Poor for Low Cost,” and (b) Vertical connectivity, as voiced by Mark Bohr: “Intel’s Bohr agrees that 3D structures will become more important. He said the kind of through-silicon vias used for today’s chip stacks need to improve in their density by orders of magnitude.”

These limitations are the driver behind the efforts to develop monolithic 3D technology. Monolithic 3D would provide a very cost effective alternative to dimensional scaling with 10,000x higher than TSV vertical connectivity, as illustrated by the following slide of CEA Leti.

3DIC coolcube 2

A 1,000x improvement in energy efficiency using monolithic 3D was calculated by Stanford Prof. Subhasish Mitra. His sum-up at a SEMICON West keynote panel: “We have an opportunity for a thousand-fold increase in energy efficiency…from collaboration between dense computing and memory elements and dense 3-D integration of them.”

Until recently, all monolithic 3D process flows required a significantly new transistor formation flow. Since the transistor process is where the majority of the R&D budget and talent is being allocated, and carries with it fresh reliability concerns, the industry has been most hesitant with respect to monolithic 3D adoption. Yet in this recent industry gathering there is a sense that industry wide interest is strengthening for 3D technologies. The success of 3D NAND as the first monolithic 3D industry wide adoption could help this new interest build even faster.

A recent technology breakthrough, first presented in IEEE S3S 2014 conference (Precision Bonders – A Game Changer for Monolithic 3D) introduced a game changer in the ease of monolithic 3D adoption. Enhancement of this breakthrough will be presented in this year’s IEEE S3S 2015. This new monolithic 3D flow allows the use of the existing fab transistor process for the fabrication of monolithic 3D devices, offering a most attractive path for the industry future scaling technology.

P.S.

A good conference to learn more about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program, Qualcomm will present some of their work on monolithic 3D – 3DV, and three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies, and many other authors will be talking about their work on monolithic 3DIC and its ecosystem.

More blog posts from Zvi Or-Bach: 

Moore’s Law to keep on 28nm

Paradigm shift in semi equipment – Confirmed

Moore’s Law has stopped at 28nm

Paradigm shift: Semi equipment tells the future

Using a hybrid silica sol-gel material and self-assembled monolayers of a common fatty acid, researchers have developed a new capacitor dielectric material that provides an electrical energy storage capacity rivaling certain batteries, with both a high energy density and high power density.

Members of the research group of Joe Perry pose in their laboratory, where samples of their new hybrid sol-gel dielectric material are fabricated. (Credit: John Toon, Georgia Tech)

Members of the research group of Joe Perry pose in their laboratory, where samples of their new hybrid sol-gel dielectric material are fabricated. (Credit: John Toon, Georgia Tech)

If the material can be scaled up from laboratory samples, devices made from it could surpass traditional electrolytic capacitors for applications in electromagnetic propulsion, electric vehicles and defibrillators. Capacitors often complement batteries in these applications because they can provide large amounts of current quickly.

The new material is composed of a silica sol-gel thin film containing polar groups linked to the silicon atoms and a nanoscale self-assembled monolayer of an octylphosphonic acid, which provides insulating properties. The bilayer structure blocks the injection of electrons into the sol-gel material, providing low leakage current, high breakdown strength and high energy extraction efficiency.

Samples of the new hybrid sol-gel material are shown placed on a clear plastic substrate for testing. (Credit: John Toon, Georgia Tech)

Samples of the new hybrid sol-gel material are shown placed on a clear plastic substrate for testing. (Credit: John Toon, Georgia Tech)

“Sol-gels with organic groups are well known and fatty acids such as phosphonic acids are well known,” noted Joseph Perry, a professor in the School of Chemistry and Biochemistry at the Georgia Institute of Technology. “But to the best of our knowledge, this is the first time these two types of materials have been combined into high-density energy storage devices.”

The research, supported by the Office of Naval Research and the Air Force Office of Scientific Research, was reported July 14 in the journal Advanced Energy Materials.

The need for efficient, high-performance materials for electrical energy storage has been growing along with the ever-increasing demand for electrical energy in mobile applications. Dielectric materials can provide fast charge and discharge response, high energy storage, and power conditioning for defense, medical and commercial applications. But it has been challenging to find a single dielectric material able to maximize permittivity, breakdown strength, energy density and energy extraction efficiency.

Perry and colleagues in Georgia Tech’s Center for Organic Photonics and Electronics (COPE) had been working on other capacitor materials to meet these demands, but were not satisfied with the progress. The hybrid sol-gel materials had shown potential for efficient dielectric energy storage because of their high orientational polarization under an electric field, so the group decided to pursue these materials for the new capacitor applications.

Georgia Tech professor Joseph Perry and researcher Yunsang Kim examine a sample of sol-gel solution, which is used for spin processing in the fabrication of hybrid sol-gel dielectric materials. (Credit: John Toon, Georgia Tech)

Georgia Tech professor Joseph Perry and researcher Yunsang Kim examine a sample of sol-gel solution, which is used for spin processing in the fabrication of hybrid sol-gel dielectric materials. (Credit: John Toon, Georgia Tech)

Using an aluminized mylar film coated with the hybrid sol-gel capacitor material, they showed that the capacitor could be rolled and re-rolled several times while maintaining high energy density, demonstrating its flexibility. But they were still seeing high current leakage. To address that, they deposited a nanoscale self-assembled monolayer of n-octylphosphonic acid on top of the hybrid sol-gel. Less than a nanometer thick, the monolayer serves as an insulating layer.

“Our silica sol-gel is a hybrid material because it has polar organic groups attached to the silica framework that gives the sol-gel a high dielectric constant, and in our bilayer dielectric, the n-octylphosphonic acid groups are inserted between the sol-gel layer and the top aluminum layer to block charge injection into the sol-gel,” Perry explained. “It’s really a bilayer hybrid material that takes the best of both reorientation polarization and approaches for reducing injection and improving energy extraction.”

In their structures, the researchers demonstrated maximum extractable energy densities up to 40 joules per cubic centimeter, an energy extraction efficiency of 72 percent at a field strength of 830 volts per micron, and a power density of 520 watts per cubic centimeter. The performance exceeds that of conventional electrolytic capacitors and thin-film lithium ion batteries, though it doesn’t match the lithium ion battery formats commonly used in electronic devices and vehicles.

“This is the first time I’ve seen a capacitor beat a battery on energy density,” said Perry. “The combination of high energy density and high power density is uncommon in the capacitor world.”

Researchers in Perry’s lab have been making arrays of small sol-gel capacitors in the lab to gather information about the material’s performance. The devices are made on small substrates about an inch square.

“What we see when we apply an electric field is that the polarization response – which measures how much the polar groups line up in a stable way with the field – behaves in a linear way,” said Perry. “This is what you want to see in a capacitor dielectric material.”

The next step will be to scale up the materials to see if the attractive properties transfer to larger devices. If that is successful, Perry expects to commercialize the material through a startup company or SBIR project.

“The simplicity of fully solution-based processes for our dielectric material system provides potential for facile scale-up and fabrication on flexible platforms,” the authors wrote in their paper. “This work emphasizes the importance of controlling the electrode-dielectric interface to maximize the performance of dielectric materials for energy storage application.”

In addition to Perry, the research team included Yunsang Kim, Mohanalingam Kathaperumal and Vincent Chen from the Georgia Tech School of Chemistry and Biochemistry; Yohan Park from the Georgia Tech School of Materials Science and Engineering; Canek Fuentes-Hernandez and Bernard Kippelen from the Georgia Tech School of Electrical and Computer Engineering, and Ming-Hen Pan from the Naval Research Laboratory.

This research was supported by the Office of Naval Research Dielectric Films Program (Grant N000141110462) and U.S. Air Force Office of Scientific Research, BioPAINTS MURI Program (Grant FA9550-09-0669).  The content of this article is solely the responsibility of the authors and does not necessarily represent the official views of the sponsoring agencies.

CITATION: Yunsang Kim, et al., “Bilayer Structure with Ultra-high Energy/Power Density Using Hybrid Sol-Gel Dielectric and Charge Blocking Monolayer, (Advanced Energy Materials, 2015). http://www.dx.doi.org/10.1002/aenm.201500767

A team of researchers from Berkeley Lab and Columbia University has passed a major milestone in molecular electronics with the creation of the world’s highest-performance single-molecule diode. Working at Berkeley Lab’s Molecular Foundry, a U.S. Department of Energy (DOE) Office of Science User Facility, the team used a combination of gold electrodes and an ionic solution to create a single-molecule diode that outperforms the best of its predecessors by a factor of 50.

“Using a single symmetric molecule, an ionic solution and two gold electrodes of dramatically different exposed surface areas, we were able to create a diode that resulted in a rectification ratio, the ratio of forward to reverse current at fixed voltage, in excess of 200, which is a record for single-molecule devices,” says Jeff Neaton, Director of the Molecular Foundry, a senior faculty scientist with Berkeley Lab’s Materials Sciences Division and the Department of Physics at the University of California Berkeley, and a member of the Kavli Energy Nanoscience Institute at Berkeley (Kavli ENSI).

“The asymmetry necessary for diode behavior originates with the different exposed electrode areas and the ionic solution,” he says. “This leads to different electrostatic environments surrounding the two electrodes and superlative single-molecule device behavior.”

With “smaller and faster” as the driving mantra of the electronics industry, single-molecule devices represent the ultimate limit in electronic miniaturization. In 1974, molecular electronics pioneers Mark Ratner and Arieh Aviram theorized that an asymmetric molecule could act as a rectifier, a one-way conductor of electric current. Since then, development of functional single-molecule electronic devices has been a major pursuit with diodes – one of the most widely used electronic components – being at the top of the list.

A typical diode consists of a silicon p-n junction between a pair of electrodes (anode and cathode) that serves as the “valve” of an electrical circuit, directing the flow of current by allowing it to pass through in only one “forward” direction. The asymmetry of a p-n junction presents the electrons with an “on/off” transport environment. Scientists have previously fashioned single-molecule diodes either through the chemical synthesis of special asymmetric molecules that are analogous to a p-n junction; or through the use of symmetric molecules with different metals as the two electrodes. However, the resulting asymmetric junctions yielded low rectification ratios, and low forward current. Neaton and his colleagues at Columbia University have discovered a way to address both deficiencies.

“Electron flow at molecular length-scales is dominated by quantum tunneling,” Neaton explains. “The efficiency of the tunneling process depends intimately on the degree of alignment of the molecule’s discrete energy levels with the electrode’s continuous spectrum. In a molecular rectifier, this alignment is enhanced for positive voltage, leading to an increase in tunneling, and is reduced for negative voltage. At the Molecular Foundry we developed an approach to accurately compute energy-level alignment and tunneling probability in single-molecule junctions. This method allowed myself and Zhenfei Liu to understand the diode behavior quantitatively.”

In collaboration with Columbia University’s Latha Venkataraman and Luis Campos and their respective research groups, Neaton and Liu fabricated a high-performing rectifier from junctions made of symmetric molecules with molecular resonance in nearly perfect alignment with the Fermi electron energy levels of the gold electrodes. Symmetry was broken by a substantial difference in the size of the area on each gold electrode that was exposed to the ionic solution. Owing to the asymmetric electrode area, the ionic solution, and the junction energy level alignment, a positive voltage increases current substantially; a negative voltage suppresses it equally significantly.

“The ionic solution, combined with the asymmetry in electrode areas, allows us to control the junction’s electrostatic environment simply by changing the bias polarity,” Neaton says. “In addition to breaking symmetry, double layers formed by ionic solution also generate dipole differences at the two electrodes, which is the underlying reason behind the asymmetric shift of molecular resonance. The Columbia group’s experiments showed that with the same molecule and electrode setup, a non-ionic solution yields no rectification at all.”

The Berkeley Lab-Columbia University team believes their new approach to a single-molecule diode provides a general route for tuning nonlinear nanoscale-device phenomena that could be applied to systems beyond single-molecule junctions and two-terminal devices.

“We expect the understanding gained from this work to be applicable to ionic liquid gating in other contexts, and mechanisms to be generalized to devices fabricated from two-dimensional materials,” Neaton says. “Beyond devices, these tiny molecular circuits are petri dishes for revealing and designing new routes to charge and energy flow at the nanoscale. What is exciting to me about this field is its multidisciplinary nature – the need for both physics and chemistry – and the strong beneficial coupling between experiment and theory.

“With the increasing level of experimental control at the single-molecule level, and improvements in theoretical understanding and computational speed and accuracy, we’re just at the tip of the iceberg with what we can understand and control at these small length scales.”

Neaton, Venkataraman and Campos are the corresponding authors of a paper describing this research in Nature Nanotechnology. The paper is titled “Single-molecule diodes with high rectification ratios through environmental control.” Other co-authors are Brian Capozzi, Jianlong Xia, Olgun Adak, Emma Dell, Zhen-Fei Liu and Jeffrey Taylor.

When it comes to installing solar cells, labor cost and the cost of the land to house them constitute the bulk of the expense. The solar cells — made often of silicon or cadmium telluride — rarely cost more than 20 percent of the total cost. Solar energy could be made cheaper if less land had to be purchased to accommodate solar panels, best achieved if each solar cell could be coaxed to generate more power.

A huge gain in this direction has now been made by a team of chemists at the University of California, Riverside that has found an ingenious way to make solar energy conversion more efficient.  The researchers report in Nano Letters that by combining inorganic semiconductor nanocrystals with organic molecules, they have succeeded in “upconverting” photons in the visible and near-infrared regions of the solar spectrum.

“The infrared region of the solar spectrum passes right through the photovoltaic materials that make up today’s solar cells,” explained Christopher Bardeen, a professor of chemistry. The research was a collaborative effort between him and Ming Lee Tang, an assistant professor of chemistry. “This is energy lost, no matter how good your solar cell. The hybrid material we have come up with first captures two infrared photons that would normally pass right through a solar cell without being converted to electricity, then adds their energies together to make one higher energy photon. This upconverted photon is readily absorbed by photovoltaic cells, generating electricity from light that normally would be wasted.”

Bardeen added that these materials are essentially “reshaping the solar spectrum” so that it better matches the photovoltaic materials used today in solar cells. The ability to utilize the infrared portion of the solar spectrum could boost solar photovoltaic efficiencies by 30 percent or more.

In their experiments, Bardeen and Tang worked with cadmium selenide and lead selenide semiconductor nanocrystals. The organic compounds they used to prepare the hybrids were diphenylanthracene and rubrene. The cadmium selenide nanocrystals could convert visible wavelengths to ultraviolet photons, while the lead selenide nanocrystals could convert near-infrared photons to visible photons.

In lab experiments, the researchers directed 980-nanometer infrared light at the hybrid material, which then generated upconverted orange/yellow fluorescent 550-nanometer light, almost doubling the energy of the incoming photons. The researchers were able to boost the upconversion process by up to three orders of magnitude by coating the cadmium selenide nanocrystals with organic ligands, providing a route to higher efficiencies.

“This 550 — nanometer light can be absorbed by any solar cell material,” Bardeen said. “The key to this research is the hybrid composite material — combining inorganic semiconductor nanoparticles with organic compounds. Organic compounds cannot absorb in the infrared but are good at combining two lower energy photons to a higher energy photon. By using a hybrid material, the inorganic component absorbs two photons and passes their energy on to the organic component for combination. The organic compounds then produce one high-energy photon. Put simply, the inorganics in the composite material take light in; the organics get light out.”

Besides solar energy, the ability to upconvert two low energy photons into one high energy photon has potential applications in biological imaging, data storage and organic light-emitting diodes. Bardeen emphasized that the research could have wide-ranging implications.

“The ability to move light energy from one wavelength to another, more useful region, for example, from red to blue, can impact any technology that involves photons as inputs or outputs,” he said.