Tag Archives: letter-wafer-tech

New research from Rice University could make it easier for engineers to harness the power of light-capturing nanomaterials to boost the efficiency and reduce the costs of photovoltaic solar cells.

Although the domestic solar-energy industry grew by 34 percent in 2014, fundamental technical breakthroughs are needed if the U.S. is to meet its national goal of reducing the cost of solar electricity to 6 cents per kilowatt-hour.

In a study published July 13 in Nature Communications, scientists from Rice’s Laboratory for Nanophotonics (LANP) describe a new method that solar-panel designers could use to incorporate light-capturing nanomaterials into future designs. By applying an innovative theoretical analysis to observations from a first-of-its-kind experimental setup, LANP graduate student Bob Zheng and postdoctoral research associate Alejandro Manjavacas created a methodology that solar engineers can use to determine the electricity-producing potential for any arrangement of metallic nanoparticles.

LANP researchers study light-capturing nanomaterials, including metallic nanoparticles that convert light into plasmons, waves of electrons that flow like a fluid across the particles’ surface. For example, recent LANP plasmonic research has led to breakthroughs in color-display technology, solar-powered steam production and color sensors that mimic the eye.

“One of the interesting phenomena that occurs when you shine light on a metallic nanoparticle or nanostructure is that you can excite some subset of electrons in the metal to a much higher energy level,” said Zheng, who works with LANP Director and study co-author Naomi Halas. “Scientists call these ‘hot carriers’ or ‘hot electrons.'”

Halas, Rice’s Stanley C. Moore Professor of Electrical and Computer Engineering and professor of chemistry, bioengineering, physics and astronomy, and materials science and nanoengineering, said hot electrons are particularly interesting for solar-energy applications because they can be used to create devices that produce direct current or to drive chemical reactions on otherwise inert metal surfaces.

Today’s most efficient photovoltaic cells use a combination of semiconductors that are made from rare and expensive elements like gallium and indium. Halas said one way to lower manufacturing costs would be to incorporate high-efficiency light-gathering plasmonic nanostructures with low-cost semiconductors like metal oxides. In addition to being less expensive to make, the plasmonic nanostructures have optical properties that can be precisely controlled by modifying their shape.

“We can tune plasmonic structures to capture light across the entire solar spectrum,” Halas said. “The efficiency of semiconductor-based solar cells can never be extended in this way because of the inherent optical properties of the semiconductors.”

The plasmonic approach has been tried before but with little success.

Zheng said, “Plasmonic-based photovoltaics have typically had low efficiencies, and it hasn’t been entirely clear whether those arose from fundamental physical limitations or from less-than-optimal designs.”

He and Halas said Manjavacas, a theoretical physicist in the group of LANP researcher Peter Nordlander, conducted work in the new study that offers a fundamental insight into the underlying physics of hot-electron-production in plasmonic-based devices.

Manjavacas said, “To make use of the photon’s energy, it must be absorbed rather than scattered back out. For this reason, much previous theoretical work had focused on understanding the total absorption of the plasmonic system.”

He said a recent example of such work comes from a pioneering experiment by another Rice graduate student, Ali Sobhani, where the absorption was concentrated near a metal semiconductor interface.

“From this perspective, one can determine the total number of electrons produced, but it provides no way of determining how many of those electrons are actually useful, high-energy, hot electrons,” Manjavacas said.

He said Zheng’s data allowed a deeper analysis because his experimental setup selectively filtered high-energy hot electrons from their less-energetic counterparts. To accomplish this, Zheng created two types of plasmonic devices. Each consisted of a plasmonic gold nanowire atop a semiconducting layer of titanium dioxide. In the first setup, the gold sat directly on the semiconductor, and in the second, a thin layer of pure titanium was placed between the gold and the titanium dioxide. The first setup created a microelectronic structure called a Schottky barrier and allowed only hot electrons to pass from the gold to the semiconductor. The second setup allowed all electrons to pass.

“The experiment clearly showed that some electrons are hotter than others, and it allowed us to correlate those with certain properties of the system,” Manjavacas said. “In particular, we found that hot electrons were not correlated with total absorption. They were driven by a different, plasmonic mechanism known as field-intensity enhancement.”

LANP researchers and others have spent years developing techniques to bolster the field-intensity enhancement of photonic structures for single-molecule sensing and other applications. Zheng and Manjavacas said they are conducting further tests to modify their system to optimize the output of hot electrons.

Halas said, “This is an important step toward the realization of plasmonic technologies for solar photovoltaics. This research provides a route to increasing the efficiency of plasmonic hot-carrier devices and shows that they can be useful for converting sunlight into usable electricity.”

By encoding information in photons via their spin, “photonic” computers could be orders of magnitude faster and efficient than their current-day counterparts. Likewise, encoding information in the spin of electrons, rather than just their quantity, could make “spintronic” computers with similar advantages.

University of Pennsylvania engineers and physicists have now discovered a property of silicon that combines aspects of all of these desirable qualities.

In a study published in Science, they have demonstrated a silicon-based photonic device that is sensitive to the spin of the photons in a laser shined on one of its electrodes. Light that is polarized clockwise causes current to flow in one direction, while counter-clockwise polarized light makes it flow in the other direction.

This property was hiding in plain sight; it is a function of the geometric relationship between the pattern of atoms on the surface of silicon nanowires and how electrodes placed on those wires intersect them. The interaction between the semiconducting silicon and the metallic electrodes produces an electric field at an angle that breaks the mirror symmetry that silicon typically exhibits. This chiral property is what sends electrons in one direction or the other down the nanowire depending on the polarity of the light that hits the electrodes.

The study was led by Ritesh Agarwal, a professor in the Department of Materials Science and Engineering in Penn’s School of Engineering and Applied Science, and Sajal Dhara, a postdoctoral researcher in Agarwal’s lab. They collaborated with Eugene Mele, a professor in the Department of Physics and Astronomy in Penn’s School of Arts & Sciences.

“Whenever you change a symmetry, you can do new things,” said Agarwal. “In this case, we have demonstrated how to make a photodetector sensitive to a photon’s spin. All photonic computers need photodetectors, but they currently only use the quantity of photons to encode information. This sensitivity to photon spin would be an extra degree of freedom, meaning you could encode additional information on each photon.

“Typically, materials with heavy elements show this property due to their spins strongly interacting with electron’s orbital motion, but we have demonstrated this effect on the surface of silicon, originating only from the electron’s orbital motion”

Agarwal and Dhara reached out to Mele due to his work on topological insulators. He, along with fellow Penn physicist Charles Kane, laid the foundation for this new a class of materials, which are electrical insulators on their interiors but conduct electricity on their surfaces.

Agarwal’s group was working on various materials that exhibit topological effects, but as a check on their methods, Mele suggested trying their experiments with silicon as well. As a light, highly symmetric material, silicon was not thought to be able to exhibit these properties.

“We expected the control experiment to give a null result, instead we discovered something new about nanomaterials,” Mele said.

Silicon is the heart of computer industry, so finding ways of producing these types of effects in that element is preferable to learning how to work with the heavier, rarer elements that naturally exhibit them.

Once it was clear that silicon was capable of having chiral properties, the researchers set out to find out the atomic mechanisms behind it.

“The effect was coming from the surface of the nanowire,” Dhara said. “The way most silicon nanowires are grown, the atoms are bound in zigzag chains that go along the surface, not down into the wire.”

These zigzag patterns are such that placing a mirror on top of them would produce an image that could be superimposed on the original. This is why silicon is not intrinsically chiral. However, when metal electrodes are placed on the wire in the typical perpendicular fashion, they intersect the direction of the chains at a slight angle.

“When you have any metal and any semiconductor in contact, you’ll get an electric field at the interface, and it’s this field that is breaking the mirror symmetry in the silicon chains,” Dhara said.

Because the direction of the electric field does not exactly match the direction of the zigzag chains, there are angles where the silicon is asymmetric. This means it can exhibit chiral properties. Shining a circularly polarized laser at the point on the nanowire where metal and semiconductor meet produces a current, and the spin of the photons in that laser determines the direction of the current’s flow.

Dhara and Agarwal are currently working on ways to get planar silicon to exhibit these properties using the same mechanism.

Ben-Gurion University of the Negev (BGU) and University of Western Australia researchers have developed a new process to develop few-layer graphene for use in energy storage and other material applications that is faster, potentially scalable and surmounts some of the current graphene production limitations.

Graphene is a thin atomic layer of graphite (used in pencils) with numerous properties that could be valuable in a variety of applications, including medicine, electronics and energy. Discovered only 11 years ago, graphene is one of the strongest materials in the world, highly conductive, flexible, and transparent. However, current methods for production currently require toxic chemicals and lengthy and cumbersome processes that result in low yield that is not scalable for commercial applications.

The new revolutionary one-step, high-yield generation process is detailed in the latest issue of Carbon, published by a collaborative team that includes BGU Prof. Jeffrey Gordon of the Alexandre Yersin Department of Solar Energy and Environmental Physics at the Jacob Blaustein Institutes for Desert Research and Prof. H.T. Chua’s group at the University of Western Australia (UWA, Perth).

Their ultra-bright lamp-ablation method surmounts the shortcomings and has succeeded in synthesizing few-layer (4-5) graphene in higher yields. It involves a novel optical system (originally invented by BGU Profs. Daniel Feuermann and Jeffrey Gordon) that reconstitutes the immense brightness within the plasma of high-power xenon discharge lamps at a remote reactor, where a transparent tube filled with simple, inexpensive graphite is irradiated.

The process is relatively faster, safer and green — devoid of any toxic substances (just graphite plus concentrated light).

Following this proof of concept, the BGU-UWA team is now planning an experimental program to scale up this initial success toward markedly improving the volume and rate at which few-layer (and eventually single-layer) graphene can be synthesized.

Semiconductors, metals and insulators must be integrated to make the transistors that are the electronic building blocks of your smartphone, computer and other microchip-enabled devices. Today’s transistors are miniscule–a mere 10 nanometers wide–and formed from three-dimensional (3D) crystals.

But a disruptive new technology looms that uses two-dimensional (2D) crystals, just 1 nanometer thick, to enable ultrathin electronics. Scientists worldwide are investigating 2D crystals made from common layered materials to constrain electron transport within just two dimensions. Researchers had previously found ways to lithographically pattern single layers of carbon atoms called graphene into ribbon-like “wires” complete with insulation provided by a similar layer of boron nitride. But until now they have lacked synthesis and processing methods to lithographically pattern junctions between two different semiconductors within a single nanometer-thick layer to form transistors, the building blocks of ultrathin electronic devices.

Now for the first time, researchers at the Department of Energy’s Oak Ridge National Laboratory have combined a novel synthesis process with commercial electron-beam lithography techniques to produce arrays of semiconductor junctions in arbitrary patterns within a single, nanometer-thick semiconductor crystal. The process relies upon transforming patterned regions of one existing, single-layer crystal into another. The researchers first grew single, nanometer-thick layers of molybdenum diselenide crystals on substrates and then deposited protective patterns of silicon oxide using standard lithography techniques. Then they bombarded the exposed regions of the crystals with a laser-generated beam of sulfur atoms. The sulfur atoms replaced the selenium atoms in the crystals to form molybdenum disulfide, which has a nearly identical crystal structure. The two semiconductor crystals formed sharp junctions, the desired building blocks of electronics. Nature Communications reports the accomplishment.

“We can literally make any kind of pattern that we want,” said Masoud Mahjouri-Samani, who co-led the study with David Geohegan. Geohegan, head of ORNL’s Nanomaterials Synthesis and Functional Assembly Group at the Center for Nanophase Materials Sciences, is the principal investigator of a Department of Energy basic science project focusing on the growth mechanisms and controlled synthesis of nanomaterials. Millions of 2D building blocks with numerous patterns may be made concurrently, Mahjouri-Samani added. In the future, it might be possible to produce different patterns on the top and bottom of a sheet. Further complexity could be introduced by layering sheets with different patterns.

Added Geohegan, “The development of a scalable, easily implemented process to lithographically pattern and easily form lateral semiconducting heterojunctions within two-dimensional crystals fulfills a critical need for ‘building blocks’ to enable next-generation ultrathin devices for applications ranging from flexible consumer electronics to solar energy.”

Tuning the bandgap

“We chose pulsed laser deposition of sulfur because of the digital control it gives you over the flux of the material that comes to the surface,” said Mahjouri-Samani. “You can basically make any kind of intermediate alloy. You can just replace, say, 20 percent of the selenium with sulfur, or 30 percent, or 50 percent.” Added Geohegan, “Pulsed laser deposition also lets the kinetic energy of the sulfur atoms be tuned, allowing you to explore a wider range of processing conditions.”

It is important that by controlling the ratio of sulfur to selenium within the crystal, the researchers can tune the bandgap of the semiconductors, an attribute that determines electronic and optical properties. To make optoelectronic devices such as electroluminescent displays, microchip fabricators integrate semiconductors with different bandgaps. For example, molybdenum disulfide’s bandgap is greater than molybdenum diselenide’s. Applying voltage to a crystal containing both semiconductors causes electrons and “holes” (positive charges created when electrons vacate) to move from molybdenum disulfide into molybdenum diselenide and recombine to emit light at the bandgap of molybdenum diselenide. For that reason, engineering the bandgaps of monolayer systems can allow the generation of light with many different colors, as well as enable other applications such as transistors and sensors, Mahjouri-Samani said.

Next the researchers will see if their pulsed laser vaporization and conversion method will work with atoms other than sulfur and selenium. “We’re trying to make more complex systems in a 2D plane–integrate more ingredients, put in different building blocks–because at the end of the day, a complete working device needs different semiconductors and metals and insulators,” Mahjouri-Samani said.

To understand the process of converting one nanometer-thick crystal into another, the researchers used powerful electron microscopy capabilities available at ORNL, notably atomic-resolution Z-contrast scanning transmission electron microscopy, which was developed at the lab and is now available to scientists worldwide using the Center for Nanophase Materials Sciences. Employing this technique, electron microscopists Andrew Lupini and visiting scientist Leonardo Basile imaged hexagonal networks of individual columns of atoms in the nanometer-thick molybdenum diselenide and molybdenum disulfide crystals.

“We could directly distinguish between sulfur and selenium atoms by their intensities in the image,” Lupini said. “These images and electron energy loss spectroscopy allowed the team to characterize the semiconductor heterojunction with atomic precision.”

In the last decade, graphene has been intensively studied for its unique optical, mechanical, electrical and structural properties. The one-atom-thick carbon sheets could revolutionize the way electronic devices are manufactured and lead to faster transistors, cheaper solar cells, new types of sensors and more efficient bioelectric sensory devices. As a potential contact electrode and interconnection material, wafer-scale graphene could be an essential component in microelectronic circuits, but most graphene fabrication methods are not compatible with silicon microelectronics, thus blocking graphene’s leap from potential wonder material to actual profit-maker.

Now researchers from Korea University, in Seoul, have developed an easy and microelectronics-compatible method to grow graphene and have successfully synthesized wafer-scale (four inches in diameter), high-quality, multi-layer graphene on silicon substrates. The method is based on an ion implantation technique, a process in which ions are accelerated under an electrical field and smashed into a semiconductor. The impacting ions change the physical, chemical or electrical properties of the semiconductor.

In a paper published this week in the journal Applied Physics Letters, from AIP Publishing, the researchers describe their work, which takes graphene a step closer to commercial applications in silicon microelectronics.

“For integrating graphene into advanced silicon microelectronics, large-area graphene free of wrinkles, tears and residues must be deposited on silicon wafers at low temperatures, which cannot be achieved with conventional graphene synthesis techniques as they often require high temperatures,” said Jihyun Kim, the team leader and a professor in the Department of Chemical and Biological Engineering at Korea University. “Our work shows that the carbon ion implantation technique has great potential for the direct synthesis of wafer-scale graphene for integrated circuit technologies.”

Discovered just over a decade ago, graphene is now considered the thinnest, lightest and strongest material in the world. Graphene is completely flexible and transparent while being inexpensive and non-toxic, and it can conduct electricity as well as copper, carrying electrons with almost no resistance even at room temperature, a property known as ballistic transport. Graphene’s unique optical, mechanical and electrical properties have lead to the one-atom-thick form of carbon being heralded as the next generation material for faster, smaller, cheaper and less power-hungry electronics.

“In silicon microelectronics, graphene is a potential contact electrode and an interconnection material linking semiconductor devices to form the desired electrical circuits,” said Kim. “This renders high processing temperature undesirable, as temperature-induced damage, strains, metal spiking and unintentional diffusion of dopants may occur.”

Thus, although the conventional graphene fabrication method of chemical vapor deposition is widely used for the large-area synthesis of graphene on copper and nickel films, the method is not suited for silicon microelectronics, as chemical vapor deposition would require a high growth temperature above 1,000 degrees Celsius and a subsequent transfer process of the graphene from the metallic film to the silicon.

“The transferred graphene on the target substrate often contains cracks, wrinkles and contaminants,” said Kim. “Thus, we are motivated to develop a transfer-free method to directly synthesize high quality, multilayer graphene in silicon microelectronics.”

Kim’s method relies on ion implantation, a microelectronics-compatible technique normally used to introduce impurities into semiconductors. In the process, carbon ions were accelerated under an electrical field and bombarded onto a layered surface made of nickel, silicon dioxide and silicon at the temperature of 500 degrees Celsius. The nickel layer, with high carbon solubility, is used as a catalyst for graphene synthesis. The process is then followed by high temperature activation annealing (about 600 to 900 degrees Celsius) to form a honeycomb lattice of carbon atoms, a typical microscopic structure of graphene.

Kim explained that the activation annealing temperature could be lowered by performing the ion implantation at an elevated temperature. Kim and his colleagues then systematically studied the effects of the annealing conditions on the synthesis of high-quality, multi-layer graphene by varying the ambient pressure, ambient gas, temperature and time during the treatment.

According to Kim, the ion implantation technique also offers finer control on the final structure of the product than other fabrication methods, as the graphene layer thickness can be precisely determined by controlling the dose of carbon ion implantation.

“Our synthesis method is controllable and scalable, allowing us to obtain graphene as large as the size of the silicon wafer [over 300 millimeters in diameter],” Kim said.

The researchers’ next step is to further lower the temperature in the synthesis process and to control the thickness of the graphene for manufacturing production.

By Pete Singer, Editor-in-Chief

Continued advances in the semiconductor will increasingly be enabled by materials technology, versus the scaling that has been commonplace over the last 50 years as defined by Moore’s Law. Yet new materials technology will itself create new challenges, not only in terms of deposition, etching, cleaning, planarization and cleaning, but in terms of handling. “I like to at materials within the context of what a lot of people are describing as the inflection points in the industry,” said Jim O’Neill, Chief Tech- nology Officer at Entegris. “Most materials innovations and new material introductions have been associated with those.”

O’Neill joined Entegris in 2014 as part of the ATMI acquisition. Prior to that, he was director of 14nm technology development at IBM where he led process development activi- ties at both Albany Nanotech and East Fishkill facilities.

“Historically, Moore’s Law has really been about miniaturization, but we’ve run into patterning limitations with wavelengths,” O’Neill said. “We’ve run into mobility problems with the channel ma- terials we now have. In order to maintain the spirit of Moore’s Law, materials have really been front and center.”

Today, materials are being driven most aggressively by multi-patterning: “There’s been a class of materials that have been increasingly emphasized in terms of low temperature silicon for the whole patterning stack,” O’Neill said.

Another key area is the device and the transition from planar to 3D structures, such as finFETs on the transistor side, and 3D NAND on the memory side. “This has put an increased emphasis on deposition and a transition from CVD to ALD type precursors,” O’Neill said. “Also, very specific materials such as fluorine-free tungsten, for example, for 3D NAND.”

New high mobility channel materials are also needed in the frontend. In the back end, there’s whole class of new materials being introduced for interconnects and metallurgies to try to improve RC delay performance and reliability, including cobalt and ruthenium.

One of the biggest challenges with introducing these new materials is that the infrastructure that surrounds them needs need approaches. “What you end up having to do — and what’s so disruptive to our customers — is change the whole integration scheme,” O’Neill said.

In the case of cobalt, for example, clean processes and post-polish process have need to be cobalt-compatible. “You’re not just putting in a new CVD material. You’re putting in that material and changing the enabling infrastructure that surrounds it. That’s a real challenge for our customer, the process integrators and the fab folks. But for us it creates a great opportunity,” O’Neill added.

O’Neill said Entegris’ deposition business is growing, driven to some degree by the increased need for ALD materials for 3D structures, which is the ATMI part of the business. But there are also new challenges in handling those materials. “Many of the precursors that we’re dealing with are solids. The whole challenge of handling solid materials and deriving a gas from a solid that ends up delivering a film on a wafer goes beyond the material itself and deals with the container: Its filtration, its handling. Those are really expertises of the traditional Entegris,” O’Neill said.

Entegris is now working on capabilities that would take the solid precursor in a delivery vessel with the appropriate filtration to remove any entrained particulates in the delivery stream, then sensor monitor capabilities to ensure that there is feed gas flow. “That’s really an entire materials delivery solution focused on enablement and no defectivity,” O’Neill said.

Monday, at SEMICON West, Entegris announced the release of Torrento X Series 7 nm filters with FlowPlane linear filtration technology. FlowPlane is the semiconductor industry’s first scalable, linear, high-flow filtration platform enabling advanced wet cleaning applications for the 10nm node and beyond. The first in a series of filters based on the linear filtration technology, the FlowPlane S model is designed for point of dispense (POD) applications, enabling improvements in both on-wafer defectivity and yield for critical wet cleaning applications.

“We’ve reached an inflection point where filter design must evolve to meet the needs of the most complex semiconductor manufacturing processes,” said Entegris Vice-President of the Liquid Microcontamination Control business unit, Clint Haris. “A filter is the last line of defense to prevent defect-causing contaminants from reaching the wafer. Our smaller, more powerful filtration solution will enable our customers to effectively implement their 10 and 7nm technology nodes.”

Torrento X series 7nm filters with FlowPlane linear filtration technology improve retention and increase flow rate performance by 100% compared to similarly sized radial filters. Moreover, FlowPlane users will benefit from the format’s smaller device footprint as well as improved wafer defectivity performance.

By Pete Singer, Editor-in-Chief

“Let no element on the periodic table go un-used!” That may well be the rallying cry of the semiconductor industry moving forward. One problem is that many of the new materials being considered are flammable, corrosive, toxic, pyrophoric, carcinogenic and/or hazardous in general.

“We’re all familiar with silane and hydrogen as flammable materials, but there are many other materials finding their way into manufacturing,” said Andrew Chambers, a Technical Manager at Edwards Ltd. “Disilane springs to mind, which is extremely hazardous and flammable.”

In various manufacturing process such as CVD and etch, materials are introduced into the tool as gases, liquids and solids. They react with each other and what’s on the wafer, and byproducts are pumped out of the chamber and into exhaust pipes. They are often diluted and treated by a gas abatement system, and ultimately vented to the atmosphere.

One of the biggest concerns in the fab is with flammable gas and the catastrophic dam- age that a fire could cause in the fab or sub-fab to equipment and, of course, to personnel. “If you have an exhaust pipe with flammable materials in it, it’s routine to dilute them with nitrogen to keep the concentrations below their lower flammable limit,” explained Chambers. “So even if there’s an escape to the environment, it can’t be ignited.”

A pending problem is that as process gas flows increase, more flammable materials such as hydrogen, silane and disilane are being used. “The amount of nitrogen you need to put into the exhaust pipe to dilute it to a safe level becomes extremely large,” Chambers said. “That has a number of consequences. The consumption rate increases significantly. While nitrogen in itself is not that expensive of a commodity, as you start to approach the nitrogen generation limit of your plant, it suddenly gets a lot more expensive if you have to get into extending the nitrogen supply infrastructure in your fab.”

In addition, the point of use abatement system on the end of your exhaust pipe has to be correspondingly large to deal with the very large volume of nitrogen that goes into the front of it. “The abatement of process gases in high dilution flows is very inefficient. The consequence of that is not only are you using a lot of nitrogen, but you’re having to buy very much more gas abatement capacity than you need. With that goes the additional expense of installing the equipment, providing it with water, natural gas, electrical power and so on,” Chambers said.

Edwards is presently exploring alternatives to using a gas dilution strategy to ensure safety. “We have imaginative ways of keeping the operation of the exhaust pipe safe, while reducing the cost of doing that. This includes treating the gas pipe as part of an entire inte- grated sub-fab system that is comprised of the vacuum pumps, the exhaust pipe, the end-of-pipe abatement system and the support infrastructure that goes with that. We would put in place measures so that the flammable gas is not diluted to the same level that they are accustomed to, but the safety of that gas is assured by doing a number of things. It might be that the concentration in the exhaust pipe is higher than its lower flammable limit, but that in itself is not a problem providing you keep air or oxygen or other oxidants out of the pipe at the same time,” Chambers explained.

Chambers said those kinds of ideas are starting to get some traction, because it allows the end user to regulate nitrogen consumption, reduce the amount of abatement capacity needed and generally provide a lower cost of ownership.

Clearly, properly assembled exhaust pipes with conventional joint seals will exclude air from exhausts containing flammable gases, but the operational risk is assurance of exhaust pipe integrity through years of continuous operation and numerous invasive service interventions. He said that a unified process exhaust design, with a clearly identified owner responsible for safe operation and servicing and appropriate integrated safety features, provides assurance of exhaust system integrity during prolonged operation, including routine servicing.

The same argument applies to process gases which may not be flammable but which are corrosive or toxic and could easily condense into the exhaust pipe during normal process operation. Ammonium chloride (NH4Cl), for example, is a common concern during metal etch. Ammonium hexafluorosilicate ((NH4)2 SiF6) is a nasty byproduct of nitride CVD.

“Over a period of time, they’re going to block the exhaust. Once the exhaust become blocked, you’re into areas where you need to take the tool out of manufacturing, pull the ex- haust pipe to pieces, clean it all out, leak check it and get it back into service again,” Chambers said. “There’s strong motivation for end users to provide ways of avoiding condensation in exhaust pipes.”

Interestingly, Chambers said what is perceived as a common solution to the problem — heater jackets — is not effective. “What we’ve found through a lot of experience is that, in many instances, the heater jackets and the heating systems for exhaust pipes are really badly applied. Heating the exhaust pipe and its maintenance at the required temperature is patchy at best and completely ineffective at worst.”

The best way to address all of this, according to Chambers, is to consider the sub-fab system as a complete integrated package. “We’ve been selling integrated systems comprising pumps and abatement systems for many years. If you join that whole thing together as an integrated system, it enables you to get data out of your system that can be used to provide diagnostic routines. It’s going to tell you about impending problems with your vacuum pumps, abatement system and exhaust pipe,” he said.

Inside every new smartphone, tablet or other digital gizmo are microchips with more circuits — and more processing power — than manufacturers could make a year or two before.

And behind each advance in microchips are innovations, such as one emerging next week from a Twin Cities firm, that consumers never think about or see.

Subodh Kulkarni, chief executive of Golden Valley-based CyberOptics, displayed a new sensor that measures humidity in chip-making.

Subodh Kulkarni, chief executive of Golden Valley-based CyberOptics, displayed a new sensor that measures humidity in chip-making.

At SEMICON West 2015, Golden Valley-based CyberOptics Corp. will unveil a sensor product that lets chipmakers measure the vibration, leveling and humidity inside the machines turning plain silicon wafers into chips. It’s an advance from a previous product that combined two measurements.

For chipmakers, that means slightly less time in a production run needs to be spent taking measurements, and more time can be devoted to making chips. It’s a jump in efficiency that is one of the reasons that digital gadgets keep getting better and cheaper.

For CyberOptics, it’s an addition to a lineup of semiconductor sensors that is the fastest-growing product segment in the company, which has about $45 million in annual sales. “What we are good at is taking different types of sensors and putting them together,” said Subodh Kulkarni, the company’s chief executive.

CyberOptics was started in the 1980s by a University of Minnesota electrical engineering professor named Steven Case, who recognized the role that laser-based sensors could play in lining up circuit boards. Its products were originally used by makers of computers and other electronics items for the assembly of circuits onto boards. It still makes those kinds of sensors, which have advanced to where they measure in 3-D and at eye-blinking speeds.

The company moved into the chip manufacturing industry in 2004 when it first combined a miniature sensor with a Bluetooth wireless transmitter and placed it on a substrate the size of a silicon wafer. That sensor device could then be run through a chipmaking machine to measure its accuracy and performance, sending data wirelessly in real time.

Since chipmakers need to check several attributes, such as whether wafers are being kept level or whether there is dust or other particles in the machine, they needed to run separate sensors through, consuming time that would otherwise be used for actual production.

The company’s new product adds humidity sensors into the multi-sensor package. Keeping track of humidity inside the machines that make chips has become more important as the distance between circuits has shrunk, the innovation that allows more circuits to be put on a chip.

Ever smaller chips

Just this week, IBM announced a breakthrough in making computer chips even smaller, creating a test version of the world’s first semiconductor that shrinks the circuitry to a separation of 7 nanometers. By contrast, today’s fastest computers and servers use microprocessors with circuits of 14- and 22-nanometers. The width of a human hair is about 10,000 times bigger. A strand of human DNA is 2.5 nanometers.

At such tiny widths, moisture inside the machine that is making a chip can create oxidation that renders the silicon wafer useless. While the IBM innovation is several years from becoming a commercial process, each step toward smaller circuits means that the machines and processes to make them need to be better.

“This is all good for us because, when transistors were hundreds of nanometers, you didn’t need to measure things that precisely,” Kulkarni said. “But as the chips get more sophisticated, the manufacturers can no longer afford to use the existing crude tools to do measurements and sensing.”

CyberOptics sold about $8 million worth of advanced sensors for chipmaking last year. It doesn’t break out profitability of such products but, in a filing to securities regulators, it said that its newest products, including semiconductor sensors, “have more favorable margins compared to products we have sold in the past.”

Because it can achieve extreme deformation, Equal Channel Angular Extrusion (ECAE) can deliver submicron, high strength and uniform microstructures. The resulting improvements in strength allow for monolithic targets with a longer target life of 20-100%.

BY STEPHANE FERRASSE, SUSAN STROTHERS and CHRISTIE HAUSMAN, Honeywell Electronic Materials, Sunnyvale, CA

First observed in 1852, cathodic sputtering is a form of physical vapor deposition (PVD) that involves the bombardment of a target material by positive ions to physically remove atoms from the surface, forming a vapor for substrate coating. It wasn’t until the 1960s and the growth of the electronics industry, however, that sputtering received significant attention.

Since then, sputtering has become entrenched in many integrated circuit (IC) production processes. While sputtering performance has benefited from advanced sputtering system designs and target material improvements, more is needed to meet future demands as device features shrink and thin film specifications become tighter.

The physical and chemical properties of sputtering targets play an integral role in thin film performance and device yield since they impact thin film composition, uniformity, consistency, defects (particulate), and step coverage. In addition, target utilization and lifetime is a factor in cost of ownership (CoO) as it correlates to chamber throughput and uptime.

This article explores how the microstructure of sputtering targets can be engineered to improve strength, life and thin film quality. It also compares conventional thermo-mechanical processing (TMP) to the breakthrough TMP of Equal Channel Angular Extrusion (ECAE) technology from Honeywell.

Key sputtering target properties

A great deal of research has been directed toward improving the microstructure of sputtering targets. Key target properties and challenges that impact thin film functionality and device yield include:

Chemical purity: Elemental impurities in sputtering targets are undesirable as they transfer to the thin film and adversely impact performance. However, higher purity metals are weaker and less able to withstand the stresses induced in the sputtering chamber. This poses unique manufacturing and end-use challenges unlike most other uses of metallic products.

Metallurgical defects: Thin film particulate contamination has been an ongoing and growing challenge with each successive technology node. Porosity, inclusions, inconsistent grain structures, and large second phases present in the target material can — through arcing — cause direct or indirect particulate contamination on the wafer.

Thermal stability: High thermal stability in the target material is needed to withstand high-power sputtering applications.

Target grain size: Fine grain size provides higher strength and contributes to superior film uniformity. Consistent grain structure throughout the target provides stable uniformity through target life.

Target strength: Sufficient yield strength is required to prevent target warping, which can contribute to film non-uniformity and arcing.

Key solutions to those challenges include:

Alloying or doping is an extremely common way to add strength, increase thermal stability and promote grain refinement in all metals. Unfortunately, in semiconductor applications it is usually not desirable for alloys or doping elements to become part of the thin film itself, so it is rarely an option. The exception is when the alloying element improves the thin film properties.

The use of high strength backing plates bonded to high purity targets to add strength to the entire target assembly. This is a very common and acceptable practice, but it introduces several risks and manufacturing challenges, such as a failed bond, arcing at the bond line and deflection in the assembly. Coefficient of thermal expansion (CTE) mismatches between the target and the backing plate can also pose serious challenges to target manufacturing, especially for brittle materials. Furthermore, the use of high-temper- ature bonding methods can cause grain growth and destroy desirable target metallurgical properties. This necessitates trade-offs between grain size, bond type and bond strength.

Improvements in TMP to improve the micro- structure, as described in the next section.

TMP fabrication overview

The choice of fabrication method has an impact on sputtering performance because the more defor- mation applied to the metal, the smaller the grain size. Two types of TMP, shown schematically in FIGURE 1, are described below.

Sputtering Fig 1

Conventional TMP. This uses a combination of forging, rolling and heat treatment steps to obtain finer microstructures. It delivers good results and has been the industry standard. It is, however, restricted in terms of the amount of strain and deformation it can impart on the material. The amount of deformation, often expressed as a percent reduction of billet height, is limited to about 90% (equivalent strain of 2.3) in practice for targets. Higher reductions of greater than 90% require excessive tonnage and initial billet height, and impose severe requirements on conventional TMP equipment (stroke, daylight and tonnage capability). The maximum attainable strain of approximately 2.3 is not optimal for refinement of grain size. This, combined with the need for a backing plate to add strength, may not meet the needs of high-performance IC applications.

ECAE. This is a state-of-the-art extrusion process that is specifically designed to deliver the next level of microstructure performance. A billet is extruded through two intersecting channels of equal cross-sections – allowing attainable strains of 4.6-7, equivalent to greater than 99.9% reduction. As shown in FIGURE 1, the channels meet at a 90-degree angle and severe plastic deformation is realized uniformly by simple shear, in multiple passes, without changing the size or shape of the starting material. ECAE also has the flexibility to manipulate the metal in multiple directions. Together, these features enable submicron and homogenous microstructures.

 

Performance comparisons

Finer grain structures result in improved yield strength and ultimate tensile strength, as described below:

Sputtering Table 1

Grain Sizes The attainable grain sizes for ECAE versus conventional TMP methods are shown in TABLE 1. As shown, the extreme deformation of ECAE results in finer microstructures, and thus improved strength. Grain sizes from 0.2-0.8 m can be achieved for monolithic targets, a refinement in grain size by a factor of up to 100 times depending on the material.

Strength The ability of ECAE grain refinement to improve yield strength (YS) and ultimate tensile strength (UTS) is dramatic. YS, in particular, is critical for target applications because it governs the onset of permanent plastic deformation that leads to target warping. As shown in FIGURE 2, the yield strength of several ECAE submicron grained, high purity materials – including Al-0.5 wt% Cu, Cu, Cu-0.11 wt% Al, and Cu-1% Mn – is four to six times higher than a conventional TMP material.

Sputtering Fig 2

Thermal Stability Thermal stability in terms of a material’s resistance to grain growth during sputtering is critical for consistent thin-film uniformity. The grain structures in Table 1 for both ECAE and conventional TMP materials are stable under high power sputtering conditions.

Metallurgical Defects Any heat treatment can be performed prior to ECAE because the level of grain refinement during ECAE does not depend on initial grain size. Therefore, traditional heat treatment such as solutionizing used in conven- tional TMP can be completely replaced or combined optimally with ECAE to remove or refine second phase precipitates. For example, as shown in FIGURE 3 in the optical micrograph, a conventional TMP Al0.5Cu exhibits 1-7 m (AlCu) second phases. However, during the multi-pass ECAE process at room temperature, repetitive shearing, elongation, breakage and homogenization of second phases leads to their refinement to less than 100 nm as displayed in the TEM image of submicron ECAE Al0.5Cu. This is a dramatic refinement of second phases by a factor of over 100 compared to conventional TMP targets. ECAE has a similar effect on refinement and reduction of other material defects such as voids, inclusions or dendrites.

Sputtering Fig 3

ECAE cost-performance benefits

The properties of ECAE targets described above provide important cost-performance benefits over conventional TMP techniques, allowing users to lower their total CoO. A few key examples are described below.

Monolithic Design Improves Target Life and Productivity

With ECAE, previously bonded planar Al and Cu alloy targets can be designed as single-piece, monolithic targets. This translates into a longer target life versus their bonded counterparts produced via conventional TMP. As shown in FIGURE 4, sputtering is not limited by the bond line and therefore, the erosion groove can extend much deeper for optimum material utilization. In fact, monolithic ECAE submicron Al and Cu alloy targets (200 mm and 300 mm) show a 20-100% increase in target life.

Sputtering Fig 4

This longer target life equates to cost savings by:

  • Reducing downtime associated with target changes for greater tool utilization.
  • Reducing the cost per kWh of the sputtering target.
  • Eliminating risks associated with backing plates such as de-bonding or deflection.

Improved Wafer Yield Due To Improved

Performance An even greater cost savings for users is the increase in wafer yield associated with better performing sputtering targets. Second- phase precipitates, inclusions and voids all contribute to arcing and subsequent wafer-killing defects. Minimizing these defects drastically reduces potential sources for arcing. Additionally, submicron microstructures are more resistive, which increases the threshold voltage for arcing and enhances plasma stability. Put simply, when arcing is reduced, wafer particles are reduced and wafer yield is increased. Increasing wafer yield has the single most dramatic impact on device cost.

Summary

Sputtering targets produced via TMP – both conventional and ECAE – are designed to meet thin film deposition needs. ECAE, however, has the added ability to meet more challenging IC geometries and performance. Because it can achieve extreme deformation, ECAE can deliver submicron, high strength and uniform microstructures.

The resulting improvements in strength allow for monolithic targets with a longer target life of 20-100%, depending on design. Added to this is the ability of ECAE to minimize arcing, and to reduce the size of precipitates and inclusions and other metallurgical defects, while meeting needs for chemical purity and thermal stability.

Manufacturers can reduce their CoO through improvements in thin film uniformity, greater productivity, higher wafer yield, lower production costs and less downtime.

STEPHANE FERRASSE, SUSAN STROTHERS and CHRISTIE HAUSMAN are with Honeywell Electronic Materials, Spokane, WA.

Applied Materials, Inc. today announced a next-generation etch tool, the Applied Centris Sym3 Etch system, featuring an entirely new chamber for atomic-level precision manufacturing. To overcome within-chip feature variations, the Centris Sym3 system leapfrogs current tools to provide chipmakers with the control and precision needed to pattern and create densely packed 3D structures in advanced memory and logic chips.

“Drawing on over 20 years of etch learning and our expertise in precision materials removal, the Sym3 system represents a brand new design, built from the ground up, that solves persistent and impending industry challenges,” said Dr. Raman Achutharaman, vice president and general manager of Applied’s Etch business unit. “Customer traction has been remarkable, resulting in the fastest adoption rate we’ve seen for an etch tool in the company’s history, with record ramp to production at leading-edge fabs.”

The Centris Sym3 etch chamber employs Applied’s True Symmetry technology with multiple tuning controls for optimizing global process uniformity to the atomic level. Key to the design is a focus on controlling and removing etch byproducts, which are increasingly hampering within-chip patterning uniformity. The system mitigates byproduct re-deposition to overcome the challenges of line edge roughness, pattern loading and defects – issues that are becoming more limiting for each successive technology node. Combined with an advanced RF technology that controls ion energy and angular distributions, the Sym3 system delivers unsurpassed vertical profiles for high aspect ratio 3D structures.

The Centris Sym3 platform’s six etch and two plasma clean process chambers feature system intelligence software to ensure that every process in every chamber matches precisely, enabling repeatability and high productivity for high-volume manufacturing. 

Applied Materials, Inc. develops engineering solutions for the semiconductor, flat panel display and solar photovoltaic industries.