Tag Archives: letter-wafer-tech

Nano-electronics research center imec announced today at Intersolar Europe, a new efficiency record for its large area n-type PERT (passivated emitter, rear totally diffused) crystalline silicon (Cz-Si) solar cell, now reaching 22.5 percent (calibrated at ISE CalLab). It is the highest efficiency achieved for a two-side-contacted solar cell processed on six inch commercially available n-type Cz-Si wafers without the use of passivated contacts.

N-type silicon solar cells are considered as promising alternatives to p-type solar cells for next generation highly efficient solar cells thanks to their ability to withstand light-induced degradation and to their higher tolerance to common metal impurities.

Aiming to increase the conversion efficiency of n-type silicon solar cells, imec is exploring material and architectural improvements to extend its n-PERT solar cell concept. The cells feature Ni/Cu/Ag front contacts, rear local contacts, a diffused front surface field (FSF) and a rear emitter. The cells achieved an independently confirmed open-circuit voltage (Voc) of 689mV, a short-circuit current (Jsc) of 40.3 mA/cm2, and 80.9 percent fill factor (FF).

Imec has also been exploring n-type PERT cells with a rear side p-type emitter using epitaxial growth or heterojunction processes. These advanced architectures have reached promising conversion efficiencies approaching 22 percent. We are confident that these advanced concepts will help us to further push the conversion efficiency and decrease the cost of n-PERT solar cells.

Filip Duerinckx, manager of imec’s n-PERT technology platform stated: “This new record is a testimony of our technology leadership in developing next-generation silicon photovoltaics solutions. We have a strong commitment to continue increasing the efficiency our n-PERT technology, and are very optimistic that these achievements will further pave the way to industrialization in the near term.”

The presented results have been achieved in the framework of imec’s industrial affiliation program on advanced silicon solar cells, dedicated to developing high performance and low cost Si PV-technologies. In this program, imec works closely together with industrial and academic partners along the solar cell value chain. Through participation and contribution to this program, these partners support imec’s developments and obtain early access to new technology solutions thereby accelerating their own product development.

A team of IBM researchers in Zurich, Switzerland with support from colleagues in Yorktown Heights, New York has developed a relatively simple, robust and versatile process for growing crystals made from compound semiconductor materials that will allow them be integrated onto silicon wafers — an important step toward making future computer chips that will allow integrated circuits to continue shrinking in size and cost even as they increase in performance.

Appearing this week on the cover of the journal Applied Physics Letters, from AIP Publishing, the work may allow an extension to Moore’s Law, the famous observation by Gordon Moore that the number of transistors on an integrated circuit double about every two years. In recent years some in the industry have speculated that our ability to keep pace with Moore’s Law may become exhausted eventually unless new technologies come along that will lend it leash.

“The whole semiconductor industry wants to keep Moore’s Law going. We need better performing transistors as we continue down-scaling, and transistors based on silicon won’t give us improvements anymore,” said Heinz Schmid, a researcher with IBM Research GmbH at Zurich Research Laboratory in Switzerland and the lead author on the paper.

For consumers, extending Moore’s Law will mean continuing the trend of new computer devices having increasing speed and bandwidth at reduced power consumption and cost. The new technique may also impact photonics on silicon, with active photonic components integrated seamlessly with electronics for greater functionality.

How the work was done

The IBM team fabricated single crystal nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3-D stacked nanowires, made with so-called III-V materials. Made from alloys of indium, gallium and arsenide, III-V semiconductors are seen as a possible future material for computer chips, but only if they can be successfully integrated onto silicon. So far efforts at integration have not been very successful.

The new crystals were grown using an approach called template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition, which basically starts from a small area and evolves into a much larger, defect-free crystal. This approach allowed them to lithographically define oxide templates and fill them via epitaxy, in the end making nanowires, cross junctions, nanostructures containing constrictions and 3-D stacked nanowires using the already established scaled processes of Si technology.

“What sets this work apart from other methods is that the compound semiconductor does not contain detrimental defects, and that the process is fully compatible with current chip fabrication technology,” said Schmid. “Importantly the method is also economically viable.”

He added that more development will be required to achieve the same control over performance in III-V devices as currently exists for silicon. But the new method is the key to actually integrating the stacked materials on the silicon platform, Schmid said.

Imec researchers have developed a novel technique – termed conductive atomic force microscopy tomography (or scalpel C-AFM) – that enables a three-dimensional characterization of emerging logic and memory devices.

BY UMBERTO CELANO, imec, Leuven, Belgium

Umberto Celano, using the novel scalpel C-AFM tool.

Umberto Celano, using the novel scalpel C-AFM tool.

With the introduction of three-dimensional devices (such as FinFETs) and stackable architectures (such as vertical NAND Flash memories), there is a growing need for 3D characterization techniques. These techniques should not only be capable of probing in three dimensions and examining the topological properties. They should also enable an analysis of the electrical properties of the 3D nano-sized volumes.

A shining example illustrating the need for this technique are conductive bridging random access memory (or CBRAM) devices. These devices belong to the emerging class of resistive RAM (or RRAM) memories which exhibit a fast operation, low power consumption, high endurance and high scalability. They are currently seen as a candidate memory technology for application in storage class memories and embedded non-volatile memories. Their operation basically relies on the formation of a highly conductive path, the conductive filament, in a poorly conductive medium. But the formation of this filament in an integrated device has so far never been observed with the techniques available today. A full 3D characterization of the conductive filament would considerably enhance our understanding of the filament growth dynamics and the underlying physical mechanisms. And it would enable a further optimization of the memory device.

Scalpel C-AFM, extending the 2D capabilities of C-AFM

A well-known characterization technique for advanced logic and memory devices is scanning probe microscopy (or SPM), where a sharp tip slides on a flat surface.

The 2D-maps of electrical properties provided by this technique have for many years enabled the understanding and development of advanced planar technologies at the nanoscale. SPM comes in several flavors, such as scanning tunnel microscopy (STM), atomic force microscopy (AFM), and a whole range of secondary analysis modes such as conductive AFM (or C-AFM). C-AFM is based on contact-mode AFM using a (biased) conductive tip. The topography is measured in contact-mode, while the current flowing between the biased sample and the tip is recorded simultaneously.

Researchers at imec have now evolved the C-AFM technique into a 3D characterization tool, suited to probe very confined volumes at the nanoscale. The new method consists in collecting the C-AFM images of the sample at different depths. The sectioning is induced by a controlled material removal. This is done by applying a strong pressure (GPa) between the (biased) conductive-diamond tip and the sample during the C-AFM scan. This way, sub-nm vertical removal rates are obtained. Since the diamond tip acts as a scalpel, the new method is referred to as scalpel C-AFM. The technique can be used for a wide variety of materials, and can be extended to other contact-mode AFM methods such as scanning spreading resistance microscopy.

Case: CBRAM memory devices

The imec researchers have used the scalpel C-AFM technique for studying the conductive filament formation in CBRAM memory devices. In these devices, an abrupt change in electrical resistance occurs when the device is subjected to a voltage pulse. The different resistance states are induced by the formation or dissolution of a highly conductive filament into a poorly conductive medium.

The heart of the CBRAM memory cell is a thin dielectric (e.g., Al2O3) that is sandwiched between the active electrode (Cu or Ag) and an inert counter electrode (e.g., TiN). When a positive voltage is applied to the active electrode, a field-assisted injection and transport of cations begins. This leads to the creation of the conductive filament inside the Al2O3 oxide layer. The presence of this filament dramatically lowers the resistance of the device, leaving it in a low resistive state (LRS). The conductive filament can be dissolved by applying a negative voltage to the active electrode and thus restoring a high resistance state (HRS). The two different resistance states are used as the logic values 1 or 0 for data storage applications. The overall performance of the device is highly related to the properties of the conductive filament, which has so far not been observed in 3D on scaled devices.

Observation of the conductive filament

The memory device under investigation is a Cu/5nm Al2O3/TiN-based memory, integrated in a one-transistor-one-resistor configuration. The device is placed at the cross-point between the bottom and top electrode. The scalpel C-AFM technique was applied to memory devices programmed in both the low and high resistive state. An in-house fabricated conductive- diamond tip was used for probing and removing the material.

By using the scalpel C-AFM technique, the researchers were able to observe, for the first time ever, the conductive filament formation which is responsible for the resistive switching behavior in CBRAM devices (FIGURE 1). The observed conductive filament, embedded in the Al2O3 oxide, shows a conical shape: it shrinks moving from the active electrode (Cu) towards the inert electrode (TiN). The low resistive state is created when the conductive filament eventually shorts the two electrodes.

Filaments 1-1 Filaments 1-2

 

FIGURE 1. CBRAM device: Cross-section transmission electron microscopy (TEM) image of the CBRAM memory device (left) and the device stack (middle), and AFM image of the cross-point area (right).

The experiments suggest that the dynamics of the conduction filament growth are limited by the mobility of the Cu cations in the electrolyte (FIGURE 2). When the bias is reversed, a Joule-heating assisted electro-chemical reaction is responsible for the rupture of the conductive filament (the high resistive state).

The study also demonstrates the close correlation between the programming current, the physical volume of the conductive filament and the resistance. A larger programming current induces a larger physical volume and a lower resistance value of the conductive filament. Hence, by controlling the programming current, the resistance can be modulated. This opens the possibility of creating multiple resistance sates in one single memory cell, which can considerably enhance the memory density of non-volatile CBRAM devices.

Scalpel C-AFM will rapidly find applications in other emerging technologies as well. At imec, the technique is currently being used for investigating vertical NAND Flash memory devices and oxide-based RRAM memory devices.

FIGURE 2. filament growth model: Illustration of the eletrochemical processes during resistive switching. (1) First, the Cu oxidizes and Cu+ ions are injected in the Al2O3. Second, the high electric field might lead
to the formation of oxygen vacancies in the dielectric layers (white balls in the cartoon). (2) The slow
migration of Cu+ ions in the switching layer implies
that a reduction reaction occurs before the Cu+ reaches the inert-electrode. (3) The conductive filament (CF) growth continues and the CF eventually shorts the two electrodes thereby creating the low resistive state. (4) When the bias is reversed, a Joule-heating assisted electrochemical reaction is responsible for the rupture of the CF in the point of max power dissipation, that is, CF constriction.

FIGURE 2. filament growth model: Illustration of the eletrochemical processes during resistive switching. (1) First, the Cu oxidizes and Cu+ ions are injected in the Al2O3. Second, the high electric field might lead
to the formation of oxygen vacancies in the dielectric layers (white balls in the cartoon). (2) The slow
migration of Cu+ ions in the switching layer implies
that a reduction reaction occurs before the Cu+ reaches the inert-electrode. (3) The conductive filament (CF) growth continues and the CF eventually shorts the two electrodes thereby creating the low resistive state. (4) When the bias is reversed, a Joule-heating assisted electrochemical reaction is responsible for the rupture of the CF in the point of max power dissipation, that is, CF constriction.

Suggested additional reading

‘Three-dimensional observation of the conductive filament in nanoscaled resistive memory devices’, U. Celano et al., Nano Letters, 2014. http://pubs.acs.org/ doi/abs/10.1021/nl500049g.

‘The memory roadmap, a paradigm shift from 2D to 3D’, interview with imec’s Jan Van Houdt in imec magazine, March issue. http://magazine.imec.be/ data/57/reader/reader.html#preferred/1/package/57/ pub/63/page/4.

UMBERTO CELANO is PhD student in the Material and Component Analysis (MCA) group at imec, Leuven, Belgium.

A team of researchers from Universite de Montreal, Polytechnique Montreal and the Centre national de la recherche scientifique (CNRS) in France is the first to succeed in preventing two-dimensional layers of black phosphorus from oxidating. In so doing, they have opened the doors to exploiting their striking properties in a number of electronic and optoelectronic devices. The study’s results were published in Nature Materials.

Black phosphorus: future key player in new technologies

Black phosphorus, a stable allotrope of phosphorus that presents a lamellar structure similar to that of graphite, has recently begun to capture the attention of physicists and materials researchers. It is possible to obtain single atomic layers from it, which researchers call 2D phosphane. A cousin of the widely publicized graphene, 2D phosphane brings together two very sought-after properties for device design.

First, 2D phosphane is a semiconductor material that provides the necessary characteristics for making transistors and processors. With its high-mobility, it is estimated that 2D phosphane could form the basis for electronics that is both high-performance and low-cost.

Furthermore, this new material features a second, even more distinctive, characteristic: its interaction with light depends on the number of atomic layers used. One monolayer will emit red light, whereas a thicker sample will emit into the infrared. This variation makes it possible to manufacture a wide range of optoelectronic devices, such as lasers or detectors, in a strategic fraction of the electromagnetic spectrum.

A scientific first: preserving single-atom layers of 2D phosphane from degrading

Until now, the study of 2D phosphane’s properties was slowed by a major problem: in ambient conditions, very thin layers of the material would degrade, to the point of compromising its future in the industry despite its promising potential.

As such, the research team has made a major step forward by succeeding in determining the physical mechanisms at play in this degradation, and in identifying the key elements that lead to the layers’ oxidation.

“We have demonstrated that 2D phosphane undergoes oxidation under ambient conditions, caused jointly by the presence of oxygen, water and light. We have also characterized the phenomenon’s evolution over time by using electron beam spectroscopy and Raman spectroscopy,” reports Professor Richard Martel of Universite de Montreal’s Department of Chemistry.

Next, the researchers developed an efficient procedure for producing these very fragile single-atom layers and keeping them intact.

“We were able to study the vibration modes of the atoms in this new material. Since earlier studies had been carried out on heavily degraded materials, we revealed the as-yet-unsuspected effects of quantum confinement on atoms’ vibration modes,” notes Professor Sebastien Francoeur of Polytechnique’s Department of Engineering Physics.

The study’s results will help the world scientific community develop 2D phosphane’s very special properties with the aim of developing new nanotechnologies that could give rise to high-performance microprocessors, lasers, solar cells and more.

A summary of OASIS standard advantages and weaknesses is presented, based on six years of experience with customer databases.

By Dr PHILIPPE MOREY-CHAISEMARTIN, FREDERIC BRAULT, XYALIS, Grenoble, France

Six years ago, as OASIS was introduced, we published an article highlighting why it was a positive replacement for GDSII [3]. Since then, users have started adopting OASIS in their flows, with benefits and disadvantages. One of OASIS strengths is its flexibility (unlimited coordinate precision, unlimited number of layers, etc.). But this flexibility puts unnecessary stress on layout database processing tools, in terms of memory consumption and computing times.

A new standard, OASIS.MASK, is being introduced to address the requirements specific to photomask layout representation. This new standard, a subset of OASIS, and as such fully compliant with it, introduces constraints that reflect the real-world limitations of mask manufacturing (such as a limited number of masks per process) that make the interpretation and exploitation of the OASIS.MASK databases more efficient and reliable.

Based on six years of experience with customer databases, this paper presents a summary of OASIS standard advantages and weaknesses. It reviews the constraints introduced in OASIS.MASK and highlights the benefits of using the new format. Some critical points related to too restrictive limitations are pointed out for consideration in future versions of the standard, and suggestions to improve its usability are detailed. Finally the white paper explains how the global flow from design to mask can be improved by the introduction of this format.

OASIS: a review

GDSII was introduced by Calma in 1978 as a successor of GDS format created in 1971. For 30 years, no major change has been made to this de-facto standard while chips complexity has been multiplied by 105 to 106. As a result, numerical values required to describe geometries of nanoscale structures on 300mm wafers have reached the 32 bits limits of GDSII format. The size of GDSII files is also becoming a problem, and compression is not always the best solution.

To address such issues, the OASIS format (officially SEMI P39) was developed and its first official specification was released in 2004 [6]. 

GDSII was originally created for sequential file access. It is still called a “stream format” and has been designed for magnetic tapes, which were the only media at the time able to store big amount of data. Designers still call the release milestone a “Tape Out,” even though most people have forgotten (or never known!) what an actual tape was.

Nowadays, sequential access is not an interesting property anymore and one of the new features offered by OASIS was to give direct access to parts of the file. To allow this, OASIS offers the possibility to store indexes in reference tables either at the beginning or the end of file.

In addition to faster random access, OASIS goals were to reduce file size and remove some critical limitations such as numerical precision. To meet this second requirement, the original restriction of 32 bits for all integer values has been removed. In the same way, the original limitation of GDSII to 256 layers and 256 datatypes has been cancelled.

To reduce file size, many different optimization methods have been implemented. The main idea is to avoid information repetition. For example, when reading a record in an OASIS file, a simple flag can tell the parser that the required information (cell name, layer, coordinate, etc.) is the same as for the previous record.

Another optimization is to provide a large number of different record types and then to reduce the amount of information contained in the record itself. For example, in GDSII all shapes are identified by the same record type: BOUNDARY. It is then mandatory to list the coordinates of all vertices to fully describe the shape. In OASIS, a square is not defined as a generic BOUNDARY record, but as a special type. The only required information are the coordinate of the lower left corner and the size of the square. This is true for most common configurations, which have their own record type: there are 26 different types of trapezoids (including the square) and 11 types of repetitions (including standard arrays). Defining a displacement between 2 coordinates is also declined in different types: pure horizontal displacement, pure vertical displacement, diagonal, etc. So, in most cases, only 1 value is required instead of a delta-X and delta-Y.

This makes OASIS files really compact. Considering that compression algorithms are based on the factorization of repetitions in a file, it is easy to understand that the compression ratio of an OASIS file with standard tools like gzip or bzip is not very high. OASIS files are compressed by construction and it is usually a bad idea to zip them again as you would then lose the first benefit of the format: random access.

How has it been used?

In OASIS, reference to an object can most of the time be made either by its name or by a reference number. For example, a PLACEMENT record can call a cell by its cell name, or directly by a reference number. When thousands of cells are declared and instantiated, using reference numbers can really reduce the size of the resulting OASIS file. When reference numbers are used (for cell names, strings, properties, etc.), the file must contain declarations that associate a reference number with a character string. According to the OASIS specification, these declarations can appear anywhere in the file. This implies that, in general, OASIS files cannot be properly handled until they have been fully parsed by the reader.

To improve access times, OASIS also allows these declarations to be written contiguously in “tables”. The START record of the file then contains the offset of these tables, which can be directly accessed by the reader. As a convenience for OASIS writers, the offsets can also be put in the END record: this way, the file can be written sequentially, without having to “patch” the START record afterwards (which is hard to do when writing a compressed stream).

In the latter case, the reader now has to seek to the end of the file to know the table offsets. This becomes a problem when using an external tool to compress the file (such as zip), as most compression schemes do not allow random access.

Strict mode

OASIS strict mode is a way to take advantage of reference tables by enforcing their use. For each reference table (cell name, layer name, property names, etc.), when strict mode is defined, then all references made to an object must be made by reference number. Also, the specification guarantees that all declarations that associate a reference number with a name must be made in a contiguous table, which offset is provided in either the START or END record.

The goal of strict mode is to allow fast random access in an OASIS file. A reader that takes advantage of it can start working on a file before having read it all, and can access some portions of the file directly, without having to read it sequentially. However, strict mode is optional, and, according to the specification, readers can choose not to take advantage of it, in which case they are not required to raise errors related to strict mode violation. This leads to situations where a file can appear valid to one reader, and invalid to another. More problematic are some databases we have seen, where the same reference number was associated to different names, at different places in the file. A reader taking advantage of strict mode would only see one declaration and continue working, although the file was ambiguous and invalid.

OASIS CBLOCK records provide a way to embed compressed data within an OASIS file. Contrary to using an external tool on the whole file, they allow both compression and efficient access. As of today, the only compression method supported is the lossless DEFLATE format (also found in zip). Since design files are getting larger and now routinely weight tens of Gigabytes, OASIS should probably consider including newer and more efficient compression algorithms. 

OASIS allows three different validation schemes: no validation, a CRC checksum or a byte sum. If selected, the validation writes 32 bits in END record of the file. As its name implies, the goal of the validation scheme is to detect errors or corruptions (due to file system conversion, transfers, etc.). The byte sum is a simple sum of all the bytes contained in the file, truncated to 32 bits. It is easy to implement but, as the OASIS specification itself admits, it is not very efficient for detecting errors. The CRC checksum is a common 32 bits polynomial Cyclic Redundancy Check. It is the only validation scheme that really detects error, but it comes at the cost of being byte-order dependent: the file must be written and read sequentially.

Unlike MD5 or the now recommended SHA cryptographic functions, it is worth noting that none of the OASIS validation schemes offer real “tamper-proof” checksums. It is really easy to create two OASIS files with the same checksums, but different content.

Sadly, it seems that many tools turn off validation by default. Users then have to resort to external tools for error detection (such as Unix cksum).

Advantages and weakness

The OASIS specification defines a format for integers that support unlimited precision: numbers can be arbitrarily long.

To fully implement unlimited precision, OASIS compliant software should use specialized math libraries that are able to perform operations of arbitrary precision. However, the cost of these algorithms becomes an issue for compute intensive code running on big databases.

In practice, many implementations choose to use the computer’s native precision (usually 64 bits nowadays). To prevent divergence in interpretation, the OASIS format should probably evolve to restrain the precision of integers to 64 bits. A precision of 32 bits was definitively not enough, but overpassing 64 bits may not be useful. As an example, the cube size of an elementary silicon crystal cell is 0.543nm. A value of 64 bits allows to give the exact coordinate with this precision, on a wafer of more than 10000km, almost earth diameter!

For floating point numbers, OASIS specifies 8 different formats. Some can express exact mathematical values. It is thus possible to represent the exact value of the fraction 1/3 in OASIS, even though a computer cannot use it natively. For practical purposes, it seems that OASIS could use only two of these formats: the ones based on IEEE 754 floating point representation, already used by all software and implemented natively by most processors.

Choosing a description methodology

A big advantage of OASIS is that there is a lot of choice. 8 formats to choose from when expressing a floating point value, 11 repetition types for PLACEMENT records, reference by name or by number for cells, text, properties, etc.

Most of the time, the OASIS specification does not impose or even recommend any of the different options. In the end, all this freedom becomes a problem, and most tools stick to a small subset that they use all the time.

Our recommendation would be to use the following subset of OASIS, which has proven to be the most robust in our experience:

  • Use strict mode whenever possible, and make all references by reference number (and not by name).
  • Use CBlocks rather than compressing the whole file.
  • Use CRC checksum to detect errors.
  • Never write numbers that cannot be represented as 64 bits integers.
  • Use type 6 or 7 for floating point numbers (IEEE 754 single or double precision).
  • When in doubt, use type 8 repetitions (for arrays), or type 10 (for random repetitions) : these are the most generic.
  • Try to use rotations that are multiples of 90 degrees. A rotation of 12.34 degree does not make much sense in a real mask!

To further optimize the OASIS file, one can take advantage of modal variables. According to the specification, these modal variables implicitly store the state of the preceding element. For example, they are used to instantiate a polygon in the same layer as the polygon, which was previously instantiated. When instantiating one thousand polygons in the same layer, we omit repeating one thousand times the layer number. At the scale of a complete database, this can lead to real gains in file size.

In order to fully take advantage of modal variables, the OASIS writer should sort the elements as efficiently as possible to form groups that share common parameters.

OASIS.MASK: the missing link

On one hand, OASIS has been a big step forward for the physical design description compared to GDSII, but on the other hand, photomasks description is still using an old format called MEBES. This format was created in the early seventies by ETEC, and has been updated a few times since the beginning, starting from Mode-1 to current Mode-5 version. The original Mode-1 format was definitively not suitable for describing larges chips with a precision of 1nm or even less.

Most of the foundries and mask-shops worldwide are using MEBES files, but some other formats like JEOL, VSB, MIC, HL, DXF or Gerber are also available. These formats are proprietary and are not “official” maintained standards. So, as for GDSII replacement, the basic idea was to set up a new standard for mask layout description. Mask layout and design layout are luckily not so far from each others, and the other great idea was to use the same format: OASIS. But, even if the final physical representation should be the same, photomasks description have some particularities and a straight forward usage of OASIS for this type of application was not really possible. So, SEMI P44, also known as OASIS.MASK was born [7].

It is important to notice that OASIS.MASK is not really a new format. It is a formal subset of OASIS, and as such, an OASIS.MASK file can be read by any standard OASIS parser. It mostly adds some constraints compared to the initial format, but also provides several extensions to simplify its manipulation by mask data preparation tools. 

While a design database is a hierarchical description based on the functions used in a chip, an OASIS.MASK file is a description of the layout based on the topology. It still keeps a hierarchy, but limits it to 3 levels. The first level is the top cell, the second level is made of so called localization areas and the third and last level is made of small cells named common cells. Localization areas do not have any relationship with the original functional hierarchy. They are just rectangular areas at a given place of the full layout. OASIS.MASK may then be seen as a flattened view of the chip just divided in windows.

This is more or less what is done in a MEBES file in which the original hierarchy has completely vanished. In such formats as MEBES, the hierarchy is purely topological: the first level is made of columns (the segments) and the second level is made of rows (the stripes). But as all the stripes and the segments are different, it is not possible to share any cell declaration, so the file is a fully flat description and is thus very big, nowadays sometimes exceeding a terabyte.

In all large chips, there is an intensive usage of library cells. All basic gates or memory points are called millions of times but only need to be described once. This has been taken into account in OASIS.MASK in which only the upper level cells of the functional hierarchy need to be flattened. All “small” cells may remain unchanged and are called from the intermediate level of the hierarchy. These small cells are called common cells. Their usage drastically reduces the final file size.

FIGURE 1 represents the functional hierarchy of a chip as described in a standard OASIS file. FIGURE 2 represents the same chip with the topological hierarchy in OASIS.MASK format. We can see that all small (common) repeated cells are described the same number of times in both representations, while large cells have been flattened. Flattening big functional blocks has no major impact on the final size as these cells usually appear at most a few times in the chip.

FIGURE 1. Functional hierarchical description of a chip.

FIGURE 1. Functional hierarchical description of a chip.

FIGURE 2. Topological hierarchical description of a chip.

FIGURE 2. Topological hierarchical description of a chip.

Restrictions

Being a subset of OASIS, OASIS.MASK introduces some restrictions on the original format. Most of them are to be expected, but some are more surprising. Although they might change in the future, here is a list of the current restrictions imposed by the specification :

  • Cell names and properties can only include ASCII letters, numbers and underscore (63 characters to choose from)
  • File names cannot be more that 64 bytes long (256 including directory), and must be composed of only these 63 characters (plus the period)
  • Hierarchy is limited to 3 levels
  • Strict mode is mandatory (all references are made by numbers, encoded as 32 bits integers)
  • Validation checksum is mandatory (but sadly, byte sum is allowed, although ineffective)
  • Names cannot be longer than 256 bytes (cell name, layer name, property name, …)
  • Coordinate values for PLACEMENT records are limited to 32 bits signed integers
  • Only repetitions 0-3 (regular 2D arrays) are allowed (and sadly not the more generic type 8 and 10)
  • Magnification, mirroring or rotation are disabled
  • There can only be one layer per file
  • Layer numbers are limited to 256, and datatypes are ignored.
  • Only rectangles and trapezoids are allowed (no paths or generic polygons)
  • The bounding box for all cells must be described (using OASIS S_BOUNDING_BOX property)
  • A cell cannot be larger that 1 square millimeter (except Top Cell)
  • The file offset of all cells must be given (using the S_CELL_OFSET property, encoded as a 64 bits integer)

As stated in the OASIS.MASK specification, these constraints may be relaxed in the future. For example, given the pace at which mask complexity evolves, we wouldn’t be surprised to see 32 bits integers get promoted to 64 bits in the years to come. 

Extensions

OASIS.MASK extensions are implemented as plain OASIS properties, or remain compatible with the regular OASIS format. To make them easily identifiable, all OASIS.MASK related properties are prefixed with the SEMI standard’s number: P44.

As already discussed, the major improvement of OASIS.MASK over OASIS is the introduction of localization areas. They are implemented with the P44_LOCALIZATION and P44_LOCALIZATION_AREA properties.

As its name implies, the P44_COMMON_CELL property is used to declare common cells.

The P44_GEOMETRY_OFFSET_AVAILABLE and P44_GEOMETRY_OFFSET properties allow fast access to the geometry records of every cells (one can directly jump to the declaration of rectangles and trapezoids, skipping all PLACEMENT records).

The P44_TOP_CELL_NUMBER property declares the reference number of the top cell. Since the P44_LOCALIZATION property also contains the top cell record offset in the file, finding the top cell in an OASIS.MASK files becomes very easy (and very fast), contrary to a generic OASIS file where in the worst case the entire file must be read and analyzed before being able to compute the top cell.

Other properties are also defined in the OASIS.MASK specification (such as P44_FILE_SIZE, P44_CHIP_WINDOW, P44_BOUNDING_BOX_MAX, etc.).

Most of these properties are mandatory and, when correctly used, they drastically speed up file access and topological extraction of mask areas.

Applications

In almost all design flows, the designer runs a final Design Rule Check and a final LVS (Layout vs. Schematic) on his database before sending it for mask making. This mandatory step is considered as fully reliable. But, unfortunately, it appears that some types of description are subject to interpretation. We have identified a couple of configurations for which the result may vary depending on the tool. We can’t say that one tool is better than another, we can just observe that their interpretations are different for things which are not fully specified in the standard. A typical example is a path with a segment smaller than the width. See FIGURE 3.

FIGURE 3. How should the upper right corner of the path be filled?

FIGURE 3. How should the upper right corner of the path be filled?

The good news is that such issues are much less frequent in OASIS, when compared to the former GDSII standard. But some ambiguities still remain, and a database certified as correct by a DRC, may lead to an error on the silicon because the mask data preparation tool and the layout tool have different interpretations for such corner cases.

It is thus of utmost importance to perform the verification at the last possible step in the flow and on a format without any ambiguity. OASIS.MASK is an OASIS subset, so any tool able to read OASIS files is able to read an OASIS.MASK database. This means that a design rule check can be executed on an OASIS.MASK file.

The OASIS.MASK file will be used for post layout data processing and it will be the result of a conversion from the designer database. It is important to be able to run a verification on the converted file. Additionally, there is no risk of misinterpretation since all the geometries contained in an OASIS.MASK file are simple trapezoids.

But at the current state of OASIS.MASK specification, we are facing different problems. The first one is related to layers: an OASIS.MASK file should not contain more than one layer. This makes the full verification much more complex. It is possible to verify the design rules for each layer, one after the other, but to check the inter layer rules, different layers must be seen at the same time. To perform the DRC, we must load multiple OASIS.MASK files at the same time, each of them containing a single layer. Additionally, data types usage is not clear: they are widely used in OASIS files, but are notified as ignored in OASIS.MASK. This should only involves the mask writing equipment, and we may consider that, as present in the file, the data types may still be usable by other applications. These limitations and differences of layers and data types between both formats, imply that we can’t use the same DRC deck to verify the design database and its converted version in OASIS.MASK format.

In practice there are also different lists of layers/datatypes: CAD layers and datatypes used by designers, and mask layers used for mask making and wafer processing. There is of course a relationship between both and mask layers can always be deduced from CAD layers and datatypes, while the opposite is not necessarily true. Designers do not draw all the layers and datatypes. Some process layers are computed from others by boolean operation (AND, OR, XOR, NOT). Design engineers also use some recognition layers or datatypes which are not processed, but still defined to simplify device identification. The DRC or LVS decks may need to take these differences into account in order to work on the OASIS.MASK file.

Adding more complexity by restricting files to a single layer and no datatypes seems like an unnecessary burden, especially if we consider that allowing multiple layers and datatypes per file comes at almost no cost in terms of implementation.

The Second issue is related to the hierarchy. As mentioned before, a design database has most of the time a functional hierarchy. This hierarchy should follow the schematic hierarchy and the layout vs. schematic verification is performed hierarchically. Each cell in the schematic should match a cell in the layout, and the interconnections between them should match the connections drawn at a higher level of the hierarchy. Working on the hierarchy speeds up the process, and makes it easier to identify and localize errors.

In an OASIS.MASK file, the functional hierarchy is replaced by a topological hierarchy, which makes it completely different from the schematic. Only “small” cells may remain. This means that a hierarchical LVS will be able to identify all gates and library cells, and have them matching schematic, but all the interconnections at a higher level will be processed flat. This is, of course, possible, but it will lead to a dramatic increase in processing time.

Post layout

With advanced process nodes, layout requires some post processing to meet manufacturing constraints. The two major operations to be performed are “dummification” and OPC (Optical Proximity Correction). Dummification consists in inserting small geometries in empty areas of some layers in order to guarantee an homogenous density across the whole chip. The goal is to obtain an optimal flatness during chemo-mechanical planarization steps (See [1]). Usually the inserted “dummies” are simple polygons that can be described by a single or at most a few trapezoids. The insertion is made flat at the top level of the design as it depends on the global topology of the layout. So dummification can easily be performed on an OASIS.MASK file.

Additionally, the insertion of dummy geometries is based on a density analysis of the layer. This analysis is made on a window basis and requires to have a flat view of the top level of the layout. When using a regular OASIS file, flattening a full chip requires a huge amount of memory, although only one small part of the drawing (the window) is processed at a time. The OASIS.MASK format, which is topological by design, is definitively more convenient for such an operation. The physical representation of the chip has already been flattened and split in small areas. Computing the density on pre-defined windows will require to load only a few localization areas. It will then be very easy to insert the expected trapezoids in these areas to reach the expected density. This will be performed locally without any impact neither in others areas nor in common cells. This also means that the process can easily be parallelized.

Unfortunately, one of the restriction of OASIS.MASK compared to OASIS leads to a big degradation in terms of file size. In order to have a better distribution of parasitics introduced by all the dummy geometries, they are often placed in a non-orthogonal way as explained in[4], see FIGURE 4. A full chip may contain millions of dummy geometries and it is important to have them instantiated in arrays instead of having millions of individual instantiations.

FIGURE 4. Example of non-orthogonal dummies requiring type 8 repetitions.

FIGURE 4. Example of non-orthogonal dummies requiring type 8 repetitions.

In GDSII, it was only possible to have orthogonal arrays, and the apparition of such dummies in the designs has lead to a dramatic increase of the file size. One of the interesting features of OASIS was the possibility to describe non-orthogonal arrays of cells or geometries. This is known as type 8 repetition. Thanks to this feature, it has been possible to reduce file size. But OASIS.MASK does not allow repetition of other types than 0-3, i.e. a regular orthogonal arrays. This has a very negative impact on the output file size.

The second critical operation to be done on final design layout is OPC. This consists in slightly modifying all existing geometries to compensate light diffraction and interference phenomena through the photo-mask. This is also a time consuming operation that requires a flat view of the layout. As their name implies, these optical corrections are only related to proximity effects. So a window based analysis is well adapted to this processing and OASIS.MASK format meets all requirements. 

Mask making

All geometries in an OASIS.MASK are split in basic trapezoids. This means that the fracturing step is mostly done, even if some work might still remain, like boolean operations, clipping or sizing (bias adjustment). It is also important to point out that OASIS.MASK doesn’t allow any rotation. Any cell with a rotation should be flattened and all its geometries converted to basic trapezoids which type will not change. Performing computation on trapezoids is quite easy and very fast and always results in simple shapes easily fractured in trapezoids. For example, clipping a trapezoid by a rectangle will never result in more than one convex polygon. See FIGURE 5. In the same way, applying a sizing on a trapezoid will always result in a trapezoid of the same type.

FIGURE 5. Clipping a trapezoid with a rectangular area will always generate a convex polygon that can be fractured in never more than 3 trapezoids.

FIGURE 5. Clipping a trapezoid with a rectangular area will always generate a convex polygon that can be fractured in never more than 3 trapezoids.

Display

As stated in [2], OASIS.MASK is well suited for efficient reading, especially for a viewer that usually displays a small area of the whole mask. To allow for fast random access based on the topology (e.g., display the top left corner of the mask), the OASIS.MASK file must use localization areas efficiently. For example, in FIGURE 6, only the localization area matrix will permit fast access.

FIGURE 6. Different localization-area usage.

FIGURE 6. Different localization-area usage.

When building the matrix, there is a tradeoff between access time and file size: small localization areas will allow for faster access, but will also increase file size. On the contrary, larger localization areas slow down read access but keep the file smaller. The extreme case is to use only one localization area: we are back to a regular OASIS file, very compact but without topological information.

Another thing to take into account is the amount of cells that will be put in common between all the localization areas. Putting many cells in common will reduce the file size, but will also increase access time. Note that if file size becomes an issue, one can also use CBLOCKs (one per localization area) to compress data.

Also note that localization areas are not declared in a regular array, but just as a list of statements in the top cell record. Hence they do not have to share common dimensions. For some files, it can thus be more efficient to build an “adaptive” matrix. For example, the localization area width and height can vary based on the cell density of the mask.

All these parameters need to be taken into account in the OASIS.MASK writer to strike a good balance between file size and random-access speed.

Conclusion

During the last few years, we have seen all the benefits of the OASIS format, as well as some of its weaknesses. OASIS is a complex format that provides many options, and it seems like everybody uses it in a different, sometimes suboptimal, way.

OASIS.MASK fixes some of these issues while at the same time offering a topological view of the database, which is required by some tools in the layout flow. And its compatibility with OASIS allows for a smooth transition between the design world and the process world. As such, OASIS.MASK is an important step towards standardizing the various file formats used in microelectronics.

OASIS.MASK still has some shortcomings, and we have pointed out some of the limitations which today prevent integrating this format in some steps of the flow. But OASIS.MASK is still young, and, as its specification mentions, “part of restrictions on OASIS.MASK may be relaxed, and OASIS.MASK specification may be extended”. We are confident that this format will be able to evolve and become a standard used across the whole design and layout flow. Our industry has much to gain from it in terms of robustness and usability.

References

1. Karmarkar, Aditya P. and Xu, Xiaopeng and Moroz, Victor and Rollins, Greg and Lin, Xiao, “Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology”, IEEE Computer Society (2009), 185–189.

2. Morales Domingo , Pablo Canepa Juan , Cohen Daniel, “Efficient OASIS.MASK reader”, SPIE (2010).

3. P. Morey, “Going from GDSII to Oasis”, EEtimes (2008).

4. Philippe Morey-Chaisemartin, “Layout finishing of a 28nm, 3 billions transistors, multi-core processor” (2013).

5. SEMI International Standards, “SEMI P45-0211 SPECIFICATION FOR JOB DECK DATA FORMAT FOR MASK TOOLS”.

6. SEMI International Standards, “SEMI P39-0308 – OASIS (TM) – Open Artwork System Interchange Standard” (2008).

7. SEMI International Standards, “SEMI P44-0211 – Specification for Open Artwork System Interchange Standard (OASIS ®) Specific to Mask Tools” (2010).

Dr PHILIPPE MOREY-CHAISEMARTIN, FREDERIC BRAULT, XYALIS, Grenoble, France. Email: [email protected], [email protected]

Portable electronics – typically made of non-renewable, non-biodegradable and potentially toxic materials – are discarded at an alarming rate in consumers’ pursuit of the next best electronic gadget.

In an effort to alleviate the environmental burden of electronic devices, a team of University of Wisconsin-Madison researchers has collaborated with researchers in the Madison-based U.S. Department of Agriculture Forest Products Laboratory (FPL) to develop a surprising solution: a semiconductor chip made almost entirely of wood.

The research team, led by UW-Madison electrical and computer engineering professor Zhenqiang “Jack” Ma, described the new device in a paper published today (May 26, 2015) by the journal Nature Communications. The paper demonstrates the feasibility of replacing the substrate, or support layer, of a computer chip, with cellulose nanofibril (CNF), a flexible, biodegradable material made from wood.

“The majority of material in a chip is support. We only use less than a couple of micrometers for everything else,” Ma says. “Now the chips are so safe you can put them in the forest and fungus will degrade it. They become as safe as fertilizer.”

Zhiyong Cai, project leader for an engineering composite science research group at FPL, has been developing sustainable nanomaterials since 2009.

“If you take a big tree and cut it down to the individual fiber, the most common product is paper. The dimension of the fiber is in the micron stage,” Cai says. “But what if we could break it down further to the nano scale? At that scale you can make this material, very strong and transparent CNF paper.”

Working with Shaoqin “Sarah” Gong, a UW-Madison professor of biomedical engineering, Cai’s group addressed two key barriers to using wood-derived materials in an electronics setting: surface smoothness and thermal expansion.

“You don’t want it to expand or shrink too much. Wood is a natural hydroscopic material and could attract moisture from the air and expand,” Cai says. “With an epoxy coating on the surface of the CNF, we solved both the surface smoothness and the moisture barrier.”

Gong and her students also have been studying bio-based polymers for more than a decade. CNF offers many benefits over current chip substrates, she says.

“The advantage of CNF over other polymers is that it’s a bio-based material and most other polymers are petroleum-based polymers. Bio-based materials are sustainable, bio-compatible and biodegradable,” Gong says. “And, compared to other polymers, CNF actually has a relatively low thermal expansion coefficient.”

The group’s work also demonstrates a more environmentally friendly process that showed performance similar to existing chips. The majority of today’s wireless devices use gallium arsenide-based microwave chips due to their superior high-frequency operation and power handling capabilities. However, gallium arsenide can be environmentally toxic, particularly in the massive quantities of discarded wireless electronics.

Yei Hwan Jung, a graduate student in electrical and computer engineering and a co-author of the paper, says the new process greatly reduces the use of such expensive and potentially toxic material.

“I’ve made 1,500 gallium arsenide transistors in a 5-by-6 millimeter chip. Typically for a microwave chip that size, there are only eight to 40 transistors. The rest of the area is just wasted,” he says. “We take our design and put it on CNF using deterministic assembly technique, then we can put it wherever we want and make a completely functional circuit with performance comparable to existing chips.”

While the biodegradability of these materials will have a positive impact on the environment, Ma says the flexibility of the technology can lead to widespread adoption of these electronic chips.

“Mass-producing current semiconductor chips is so cheap, and it may take time for the industry to adapt to our design,” he says. “But flexible electronics are the future, and we think we’re going to be well ahead of the curve.”

United Microelectronics Corporation, a global semiconductor foundry, today unveiled its UMC Auto technology platform to target IC companies designing chips for automotive applications. UMC Auto is a comprehensive platform that consists of a broad portfolio of automotive AEC-Q100 qualified technology solutions ranging from 0.5um to 28nm nodes, backed by robust manufacturing processes that comply with rigorous ISO TS-16949 automotive quality standards for all UMC fabs. In addition, UMC is selectively developing certified design models, IP, and Foundry Design Kits specific to the UMC Auto platform in order to fulfill the increasing pace of evolvement of the auto industry supply chain, helping chip designers capture new market opportunities as Internet of Things (IoT) and increased use of sensors permeate into auto applications.

“With the rapid rise in silicon content within each new vehicle, many believe the automotive IC sector will experience the highest CAGR compared with other semiconductor segments,” said Po Wen Yen, CEO of UMC. “UMC has a successful history as an automotive IC supplier, being the first foundry to receive ISO 22301 certification for our business continuity management system and implementing a comprehensive “Automotive Service Package” that incorporates zero-defect practices within our manufacturing procedures. We look forward to enabling more customers to realize the opportunities within the automotive IC market through our innovative UMC Auto solutions platform.”

UMC is currently producing various key electronic components used in vehicles, including Advanced Driver Assistance Systems (ADAS), safety, body control, infotainment and under-hood applications. These ICs manufactured at UMC have been widely adopted by the world’s most well-known carmakers in Japan, Europe, Asia and the United States.

UMC’s auto IC manufacturing lines meet or exceed the automotive industry’s most stringent quality and reliability criteria, including the highest rated AEC-Q100 Grade-0 certification for its fab manufacturing. UMC was also the first foundry in Taiwan to provide IC manufacturing services that comply with ISO 15408 Common Criteria, joining the 1 percent of all companies and products worldwide to be certified ISO 15408 EAL6 or above. This security qualification signifies UMC’s ability to provide rigorous security protection during the manufacturing process, which is required by the majority of IC products deployed in sensitive applications that need to be highly secure such as automotive sensors for door locks, navigation, etc.

GaN Systems, a developer of gallium nitride power switching semiconductors, today confirmed the world’s smallest 650V, 15A gallium nitride transistor. With a footprint of just 5.0 x 6.5mm, the GS66504B – one of a family of 650V devices that spans 7A to 200A – is 50 percent smaller than competing devices.

Comments Jim Witham, CEO GaN Systems: “We were somewhat surprised to see announcements at last week’s PCIM power electronics exhibition and conference that trumpeted gallium nitride 600V, 15A devices in 8x8mm dual-flat no-lead (DFN) packaging as the ‘industry’s smallest’ enhancement mode devices – our part is clearly much smaller. But I suppose this is just an indication of how quickly the GaN market is moving, and a positive indication that silicon has reached its limits.”

He continued: “Our message to designers in applications as diverse as flat screen TVs, games consoles, washing machines, inverters, electric vehicles, motors and wider is the same: if you are not on-board with GaN, you will be left behind by your competitors.”

GaN Systems is the first company to have developed and brought a comprehensive product range of devices with current ratings from 7A to 250A to the global market – its Island Technology die design, combined with its extremely low inductance and thermally efficient GaNPX packaging and Drive Assist technology means the company’s GaN transistors offer a 40-fold improvement in switching and conduction performance over traditional silicon MOSFETs and IGBTs. Devices are available now through its worldwide distribution network.

Infinitesima announced today that its groundbreaking probe microscope has been integrated into the ZEISS MeRiT neXT photomask repair tool. Masks have to be defect-free, and therefore defects have to be repaired. Traditionally Scanning Electron Microscopes (SEM) have been used to image defects that have been identified through optical inspection tools. Infinitesima’s Rapid Probe Microscope (RPM) extends the measurement capability of the SEM to provide additional 3D information. The topographical information provided by the RPM is used in the repair process.

The RPM technology is an enabler for applications such as repair verification, 3D feature analysis, repair of Chromeless Phase Shifting Lithography (CPL) masks, and buried multilayer defect repair on EUV masks.

“The RPM was designed from the start for the rigorous environment of high volume manufacturing and full automation,” said Dr. Andy Humphris, CTO of Infinitesima and inventor of the RPM. “The RPM’s throughput is 10-100 times faster than the existing Atomic Force Microscope (AFM) technology,” he said. “In combination with its sub-nanometre resolution, this has been one of the key factors to be selected by ZEISS.”

Recently appointed CEO, Dr Paul May, added “with EUV lithography imminently entering the semiconductor manufacturing process, the RPM will find important applications in repair, critical dimension measurement, and review for photomask reticles as well as for wafer.. In these applications, it will complement current Scanning Electron Microscope (SEM) technology.”

“Andy Humphris and his team have worked tirelessly and with remarkable creativity to bring this exciting technology to market,” said Andrew Dixon, Chairman of Infinitesima. “For many years we have felt there is a role for probe microscopy in the semiconductor manufacturing process and we are delighted to work alongside ZEISS.”

Dow Corning, a developer of silicones, silicon-based technology and innovation, today unveiled new Dow Corning TC-3040 Thermally Conductive Gel, a next-generation thermal interface material (TIM 1). Developed through the help of IBM, this cutting-edge new material offers more effective and reliable thermal management, reduced stress and excellent under-die coverage for demanding flip chip applications. Dow Corning unveiled the new product technology here at the IEEE Electronic Components and Technology Conference (ECTC 2015). 

TIM-1 solutions are a class of high-purity, thermal interface materials that are applied between the chip surface and a heat spreader to help dissipate damaging heat to the exterior of a semiconductor package. However, as applications from data centers to consumer devices to automotive electronics all demand higher functioning integrated semiconductor devices with increasing processing power, the temperatures within chip packages are rapidly increasing and testing the limits of conventional TIM-1 solutions.

“A long-time member of IBM’s ecosystem, Dow Corning brought decades of expertise in advanced silicone technology to help formulate this break-through TIM-1 material for high-end chip packaging,” said Andrew Ho, global market segment leader, Semiconductor Packaging Materials at Dow Corning. “It is only the latest innovation on the ambitious roadmap of thermal management solutions that Dow Corning has planned for this rapidly evolving global market.”

The successful efforts of IBM and Dow Corning scientists have raised the bar for TIM-1 performance. Dow Corning TC-3040 Thermally Conductive Gel delivers nearly two times the thermal performance of other industry standard TIMs, as well as high thermal conductivity targeting 4W/mK with robust reliability. As a result, it offers chip-makers broader design options for high-performing yet more reliable ICs with improved thermal management.”