Tag Archives: letter-wafer-tech

Semiconductor test equipment supplier Advantest Corporation announced today that it has developed a technology utilizing short-pulse terahertz waves for analysis of electrical circuits. The technology has 2 major applications – analysis of the transmission characteristics (S parameters) of devices using the sub-terahertz band (100GHz~1THz), and characterization and location of failures in chip circuits (TDT/TDR). The new technology overcomes the technical obstacles and prohibitive cost of existing technologies, and will contribute significantly to the development and wider adoption of these leading-edge devices.

Sub-terahertz transmission characteristics analysis technology

The popularity of smartphones and other mobile devices has driven enormous increases in wireless communications traffic, which now threatens to overwhelm the capacity of currently assigned frequencies. Hence, worldwide R&D efforts have begun to focus on the sub-terahertz band, a higher frequency range which has not been used for wireless communications to date.

In high-frequency device development, it is crucial to evaluate the frequency characteristics of the overall system, including active device gain and input and output impedance, as well as the board and connectors. Part of this process is measurement of the reflection and transmission characteristics of the amplitude and phase of signals emitted, known as S-parameters or scattering parameters. However, existing network analyzers can only measure frequency ranges up to 100GHz wide at one time, so when the signal characteristics of broader ranges must be evaluated, engineers have to repeatedly change the configuration of their equipment and measure again. This causes extra work, longer measurement times, and discontinuities in measured data. Measurement costs also rise proportionately to these drawbacks.

Advantest’s new technology promises to reduce these burdens significantly. It employs femtosecond optical pulsed laser as a signal source, enabling one-pass measurement of S-parameters up to 1.5THz with a broadband optical/electrical switching probe. The benefits of these efficiency gains will accrue to users in terms of time, labor, and cost savings.

High spatial resolution chip wiring quality analysis technology

Although continued shrinks of semiconductor circuits have facilitated generations of smaller, faster consumer electronics, Moore’s law is in danger of hitting a technological wall. To circumvent the physical limits of miniaturization, chipmakers are developing 3D semiconductors with multiple layers of circuits in a single package. However, wiring failure analysis is a major challenge in 3D chip development. With multiple boards stacked on top of each other, it is difficult to identify where wiring failures (open circuits, short-circuits, impedance mismatching) have occurred with X-ray inspection and other existing technologies. Generally, oscilloscope TDR (time domain reflectometry) and/or TDT (time domain transmissometry) is used to pinpoint these failures, but at these tiny geometries, extremely high spatial resolution is a must.

Because Advantest’s new technology uses a femtosecond optical pulsed laser as a signal source, it achieves superior spatial resolution of less than 5μm and a maximum measurement range of 300mm. With a successful track record of usage in the company’s terahertz spectroscopic and imaging systems, Advantest’s femtosecond optical pulsed laser boasts extremely high resolution. Moreover, the new technology provides a mapping function which can pinpoint the location of wiring failures on the device’s CAD data, making it an optimal tool for finding flaws in extremely complex, high-density circuits.

Advantest is planning to commercialize the new technology within its fiscal year 2015 (by the end of March, 2016).

Semiconductor Research Corporation (SRC), a university-research consortium for semiconductor technologies, announced today that it has received funding from the National Institute of Standards and Technology (NIST) Advanced Manufacturing Technology (AMTech) program to create a Semiconductor Synthetic Biology (SemiSynBio) consortium whose mission is to develop a SemiSynBio roadmap.

SemiSynBio lies at the intersection of semiconductor technology and leading edge biology — a convergence that has the potential for new energy efficient computing and information technologies. Advances in SemiSynBio may provide leap-ahead changes in the way that information technology and computational circuits and systems are designed and manufactured.

SRC launched a SemiSynBio research program in 2013 investigating topics such as cell-based sensors and DNA-templated interconnects, among others, at six U.S. universities: MIT, University of Massachusetts-Amherst, Yale, Georgia Tech, Brigham Young and University of Washington.

Companies that have supported the roadmap effort include Agilent, Autodesk, GLOBALFOUNDRIES, IBM, Intel Corporation, Mentor Graphics, Micron Technology, Raytheon BBN, Novati Technologies, Ginkgo Bioworks and Twist Biosciences. A number of government agencies including the Office of Naval Research, the National Science Foundation and NIST have also expressed interest in being involved. The consortium is open to any interested party — from industry, academia or government.

With $500,000 in NIST AMTech funding, the SemiSynBio consortium intends to drive research forward by developing a roadmap to bring together the semiconductor and biology/biotech communities that are critical to realizing SemiSynBio advances. The consortium will also work to identify priority technical challenges and research needs that must be addressed.

“SemiSynBio builds on advances in areas including DNA sequencing and synthetic biology,” said Victor Zhirnov, SRC Chief Scientist and Director, SemiSynBio Roadmap Consortium. “This consortium led by SRC aims to provide a 15-year roadmap that will accelerate research along the critical path to commercialization.”

The ultimate goal of the program is to create novel solutions for the design and manufacture of energy efficient computing that leverages advances in understanding of biological systems. AMTech seeks to support industry-driven consortia that address high-priority research challenges impeding the growth of advanced manufacturing in the United States.

Today, at the IEEE IITC conference, nano-electronics research center imec and Tokyo Electron Limited (TEL) presented a direct Cu etch scheme for patterning Cu interconnects. The new scheme has great potential to overcome resistivity and reliability issues that occur while scaling conventional Cu damascene interconnects for advanced nodes.

Aggressive scaling of damascene Cu interconnects leads to a drastic increase in the resistivity of the Cu wires, due to the fact that grain size is limited by the damascene trenches, which results in increased grain boundary and surface scattering. Additionally, the grain boundary negatively influences electromigration. When scaling damascene Cu interconnects, reliability issues occur because the overall copper volume is reduced and interfaces become dominant. Imec and TEL have demonstrated the feasibility of a direct Cu etch scheme to replace the conventional Cu damascene process. A key advantage of the direct Cu etch process is that it systematically results in larger grain sizes. Moreover, electromigration performance is preserved by applying an in-situ SiN cap layer that protects the Cu wires from oxidation and serves as the Cu interface.

Figure TEM section of copper etched lines encapsulated by SiN cap layer

Figure TEM section of copper etched lines encapsulated by SiN cap layer

The results were achieved in cooperation with imec’s key partners in its core CMOS programs GLOBALFOUNDRIES, Inc., Intel Corp, Micron Technology, Inc., Panasonic Corporation, Samsung Electronics Co., Ltd.,, Taiwan Semiconductor Manufacturing Co., Ltd., SK hynix Inc., Fujitsu Semiconductor Ltd., and SonyCorporation.

GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, today announced it is offering a 28nm High-k Metal Gate (HKMG) radio frequency (RF) process technology that will provide power-efficient solutions for highly integrated mobile applications and connected devices. Based on GLOBALFOUNDRIES’ 28nm Super Low Power (SLP)technology with HKMG, the 28nm-SLP-RF process includes a comprehensive set of design capabilities enabling chip designers to integrate critical RF system-on-chip (SoC) functionality into their products.

“The proliferation of connected devices and IoT consumer applications has created an opportunity and demand for RF-enabled chips,” said Mike Mendicino, senior director of product management at GLOBALFOUNDRIES. “GLOBALFOUNDRIES’ RF-enabled 28nm process lowers design barriers and enables a broader range of customers to accelerate time-to-volume of leading-edge RF SoCs.”

The 28nm-SLP-RF process is built on the 28nm-SLP HKMG process. Silicon results have demonstrated high-frequency performance (Ft ~ 310GHz) and low flicker/thermal noise providing chip designers flexibility in optimizing core RF performance and functionality in a cost-effective logic platform. The 28nm-SLP-RF process technology is designed for the next generation of connected devices that require low standby power and long battery life integrated with RF/wireless functionality.  The technology is enabled with key RF features, including core and I/O (1.5V/1.8V) transistor RF models along with 5V LDMOS devices, which simplifies RF SoC design. For passive RF devices, 28nm-SLP-RF offers alternate polarity metal-oxide-metal (APMOM) capacitors up to 5V, deep n-well devices, diffusion, poly and precision resistors, inductors and an ultra-thick metal (UTM) layer.  All RF-enabled devices are scalable, hardware verified across the entire operating range, and have met industry standard reliability qualification requirements.  Volume production of the 28nm-SLP platform started in 2012.

GLOBALFOUNDRIES’ 28nm-SLP-RF technology utilizes the companies’ production-proven, 28nm-SLP silicon-validated design flows, which include a complete set of libraries, compilers, and complex IP. The company has collaborated with leading companies in the EDA/IP ecosystem to deliver an optimized process design kit (PDK) that supports highly accurate RF SPICE models and comprehensive technology files that are integral to RF designs. GLOBALFOUNDRIES’ enhanced 28nm-SLP-RF PDK and verification method is available now.

Semiconductor test equipment supplier Advantest Corporation has introduced its new 28G OPM (28-gigabit Optical Port Module), the company’s first solution designed specifically for testing optical transceivers — advanced semiconductor devices that transmit and receive data through optical fibers. By using fiber optics, these devices enable data transmissions over longer distances at faster speeds and lower power consumption than wire cables. This technology is used extensively in applications such as data centers, which manage the extremely high volumes of data transmissions used in mobile communications and cloud computing.

“With our new 28G OPM module, we are well positioned to serve the rapidly growing market for optical transceivers, which Infonetics Research has projected to reach $3.3 billion by 2016,” said Dr. Toshiyuki Okayasu, executive officer and executive vice president of the SoC Test Business Group at Advantest Corporation. The required target price of next-generation optical transceivers is as low as one U.S. dollar for each gigabit per second (Gbps) of data-transfer speed.

The semiconductor industry roadmap for optical transceivers calls for boosting speeds from today’s 40-Gbps interconnections to 100-Gbps by 2017 and possibly 400-Gbps by 2020. Advantest’s new solution is among the first integrated solutions capable of cost-efficiently testing these high-speed devices.

By mounting the new module on Advantest’s T2000 platform, this solution can simultaneously test up to eight 100-Gbps transceivers. To test each 100-Gbps transceiver, four lanes of both optical and electrical 28-Gbps ports are used. This integrated automated test equipment (ATE) solution enables faster cycle times and greater operating efficiency at a lower cost of test while also offering the benefit of being fully supported by Advantest’s global customer service network.

“As the Internet of Things (IoT) grows, data centers need greater bandwidth,” Dr. Okayasu explained. “This requires a much higher volume of high-speed, low-cost transceivers. Our 28G OPM solution can reduce transceivers’ test costs and increase their productivity, advances that could have far-reaching effects on data center designs and the IoT.”

Freescale Semiconductor today introduced its first gallium nitride (GaN) RF power transistor for cellular base stations. The new A2G22S160-01S delivers exceptional performance in 30 W and 40 W amplifiers for wireless infrastructure applications, and represents the first of what is planned to become a broad portfolio of Airfast family GaN transistors for the cellular market.

Freescale’s addition of GaN RF solutions provides its customers an expanded portfolio of world-class products for wireless infrastructure markets. The announcement comes only a few months following the company’s introduction of the MMRF5014H – Freescale’s first GaN RF power transistor for military and industrial applications, which continues to lead the industry in thermal and wideband RF performance for 100 W-class GaN transistors.

“Freescale is driving the transition of GaN from niche markets to mainstream applications like cellular infrastructure,” said Paul Hart, senior vice president and general manager of Freescale’s RF business. “The time is right to deliver GaN solutions to our extremely broad base of telecommunications customers. In addition to utilizing the A2G22S160-01S’ excellent performance, our cellular customers can look forward to leveraging Freescale’s high-volume production capability and worldwide customer support.”

GaN delivers higher power conversion efficiencies, faster switching speeds and greater power densities than silicon, enabling the creation of power transistors that are much smaller in size and that outperform traditional devices. This is made possible due to the wider band gap, higher critical electric field and very high electron mobility characteristics that GaN provides. While GaN migration has been cost prohibitive in the past, recent commercial and technological advances are driving manufacturing costs lower.

Freescale’s Airfast family of RF power products covers the entire range of wireless cellular spectrum from 600 MHz to 3.8 GHz, with multiple semiconductor technology options. The A2G22S160-01S offers state-of-the-art performance in the frequency range between 1800 MHz and 2200 MHz. For example, in a 40 W Doherty two-way asymmetrical amplifier employing one A2G22S160-01S in the carrier path and two in the peaking path, maximum output power is 56.2 dBm. With 8dB output back-off (OBO), gain is 15.4 dB and efficiency is 56.7 percent. Adjacent-channel power (ACP) is -55 dBc with digital predistortion (DPD) when driven by two 20 MHz LTE carriers with an aggregate 40 MHz carrier bandwidth.

University of Utah engineers have taken a step forward in creating the next generation of computers and mobile devices capable of speeds millions of times faster than current machines.

The Utah engineers have developed an ultracompact beamsplitter — the smallest on record — for dividing light waves into two separate channels of information. The device brings researchers closer to producing silicon photonic chips that compute and shuttle data with light instead of electrons. Electrical and computer engineering associate professor Rajesh Menon and colleagues describe their invention today in the journal Nature Photonics.

The overhead view of a new beamsplitter for silicon photonics chips that is the size of one-fiftieth the width of a human hair. Credit: Dan Hixson/University of Utah College of Engineering

The overhead view of a new beamsplitter for silicon photonics chips that is the size of one-fiftieth the width of a human hair. Credit: Dan Hixson/University of Utah College of Engineering

Silicon photonics could significantly increase the power and speed of machines such as supercomputers, data center servers and the specialized computers that direct autonomous cars and drones with collision detection. Eventually, the technology could reach home computers and mobile devices and improve applications from gaming to video streaming.

“Light is the fastest thing you can use to transmit information,” says Menon. “But that information has to be converted to electrons when it comes into your laptop. In that conversion, you’re slowing things down. The vision is to do everything in light.”

Photons of light carry information over the Internet through fiber-optic networks. But once a data stream reaches a home or office destination, the photons of light must be converted to electrons before a router or computer can handle the information. That bottleneck could be eliminated if the data stream remained as light within computer processors.

“With all light, computing can eventually be millions of times faster,” says Menon.

To help do that, the U engineers created a much smaller form of a polarization beamsplitter (which looks somewhat like a barcode) on top of a silicon chip that can split guided incoming light into its two components. Before, such a beamsplitter was over 100 by 100 microns. Thanks to a new algorithm for designing the splitter, Menon’s team has shrunk it to 2.4 by 2.4 microns, or one-fiftieth the width of a human hair and close to the limit of what is physically possible.

The beamsplitter would be just one of a multitude of passive devices placed on a silicon chip to direct light waves in different ways. By shrinking them down in size, researchers will be able to cram millions of these devices on a single chip.

Potential advantages go beyond processing speed. The Utah team’s design would be cheap to produce because it uses existing fabrication techniques for creating silicon chips. And because photonic chips shuttle photons instead of electrons, mobile devices such as smartphones or tablets built with this technology would consume less power, have longer battery life and generate less heat than existing mobile devices.

The first supercomputers using silicon photonics — already under development at companies such as Intel and IBM — will use hybrid processors that remain partly electronic. Menon believes his beamsplitter could be used in those computers in about three years. Data centers that require faster connections between computers also could implement the technology soon, he says.

During the IEEE IITC conference in Grenoble, the nanoelectronics research center imec and Lam Research Corporation today presented a novel bottom-up prefill technique for vias and contacts. The technique, based on Electroless Deposition (ELD) of Cobalt (Co) is a highly selective method resulting in void-free filling of via and contact holes. Potentially increasing the circuit performance, it is a promising path to scaling advanced interconnects and enabling future logic and DRAM nodes at the 7nm node and below.

As logic and memory nodes scale, performance of these advanced interconnects is negatively impacted by increasing interconnect resistance. Furthermore, voids that occur in heavily scaled vias severely impact yield. imec’s industrial affiliation program on advanced interconnects is exploring novel metallization methods to solve these issues. One way to solve the problem is to identify integration and metallization alternatives that provide resistance benefits over conventional technology without compromising reliability and yield. Together with Lam Research, a Co ELD technique was demonstrated as a feasible method for highly selective bottom-up contact fill and via prefill with Cobalt (Co) as an alternative metal to Copper (Cu). Moreover, the high selectivity of the ELD process, at lower cost compared to Chemical Vapor Deposition (CVD), intrinsically ensures a good metal-to-metal interface and paves the way to void-free via filling and increased yield. Trench fill yield and line resistance may also benefit from the de-coupling of line and via aspect ratios, permitting the design of each for optimum Resistance/Capacitance (RC). Therefore, Co prefill ELD has the potential to enable future scaling of advanced logic and memory technologies.

Figure: Co ELD on Palladium/Tungsten (Pd/W) for different timed stops to yield an (i) under fill, (ii) potential ideal stop or an (iii) overburden in 28nm holes (Aspect Ratio (AR) 4.5)

Figure: Co ELD on Palladium/Tungsten (Pd/W) for different timed stops to yield an (i) under fill, (ii) potential ideal stop or an (iii) overburden in 28nm holes (Aspect Ratio (AR) 4.5)

The results were achieved in cooperation with imec’s key partners as part of its core CMOS programs: GlobalFoundries, Intel, Samsung, SK hynix, Sony, TSMC, Amkor, Micron, Utac, Qualcomm, Altera, Fujitsu, Panasonic, and Xilinx.

Applied Materials, Inc. today announced its Applied Endura Cirrus  HTX PVD system with breakthrough technology for patterning copper interconnects at 10nm and beyond. As chip features continue to shrink, innovations in hardmask are required to preserve the pattern integrity of tightly packed, tiny interconnect structures.With the introduction of this technology, Applied enables scaling of the TiN metal hardmask – the industry’s material of choice – to meet the patterning needs of copper interconnects in advanced microchips.

“Precision engineering of metal hardmask films is key to addressing the patterning challenges for advanced interconnects,” said Dr. Sundar Ramamurthy, vice president and general manager of Applied’s Metal Deposition Products business unit. “The Cirrus HTX TiN product represents Applied’s decades of expertise in applying PVD technology for engineering TiN film properties. Incorporating our unique VHF-based technology offers customers the flexibility of tuning stress in TiN films from compressive to tensile to overcome their specific integration challenges.”

Today’s advanced microchips can pack 20 kilometers of copper wiring in a 100 square millimeter area, stacked in 10 layers with up to 10 billion vias or vertical connections between layers. The role of the metal hardmask is to preserve the integrity of these patterned lines and vias in soft ULK dielectrics. However, with scaling, the compressive stress from conventional TiN hardmask layers can cause the narrow lines patterned in ULK films to deform or collapse. The tunable Cirrus HTX TiN hardmask with high etch selectivity delivers superior CD line width control and via overlay alignment resulting in yield improvement.

This breakthrough in TiN hardmask is made possible by precision materials engineering at the wafer level to produce a high density, low-stress film. Combining exceptional film thickness uniformity with low defectivity on a proven Endura platform, the Cirrus HTX system addresses the stringent high volume manufacturing needs of patterning multiple interconnect layers.

Applied Materials, Inc. is a developer precision materials engineering solutions for the semiconductor, flat panel display and solar photovoltaic industries.

Researchers at Lehigh University have identified for the first time that a performance gain in the electrical conductivity of random metal nanowire networks can be achieved by slightly restricting nanowire orientation. The most surprising result of the study is that heavily ordered configurations do not outperform configurations with some degree of randomness; randomness in the case of metal nanowire orientations acts to increase conductivity.

The study, Conductivity of Nanowire Arrays under Random and Ordered Orientation Configurations, is published in the current issue of Nature‘s journal Scientific Reports. The research was carried out by Nelson Tansu, Daniel E. ’39 and Patricia M. Smith Endowed Chair Professor in Lehigh’s Center for Photonics and Nanoelectronics and Department of Electrical and Computer Engineering, and lead author Milind Jagota, a Bethlehem-area high school student.

Transparent conductors are needed widely for flat screen displays, touch screens, solar cells, and light-emitting diodes, among many other technologies. Currently, Indium Tin Oxide (ITO) is the most widely used material for transparent conductors due to its high conductivity and high transparency. However, ITO-based technology has several issues. The material is scarce, expensive to manufacture and brittle, a particularly undesirable characteristic for anything being used in this modern age of flexible electronics.

Researchers searching for a replacement for ITO are increasingly employing random networks of metal nanowires to match ITO in both transparency and conductivity. Metal nanowire-based technologies display better flexibility and are more compatible with manufacturing processes than ITO films. The technology, however, is still in an early phase of development and performance must be improved. Current research is focused on the effect of rod orientation on conductivity of networks to improve performance.

In this work, Lehigh researchers developed a computational model for simulation of metal nanowire networks, which should speed the process towards idealizing the configuration of nanowires. The model predicts existing experimental results and previously published computational results.

The researchers then used this model to extract results for the first time on how conductivity of random metal nanowire networks is affected by different orientation restrictions of varying randomness. Two different orientation configurations are reported.

In the first, a uniform distribution of orientations over the range (?θ, θ) with respect to a horizontal line is used. In the second, a distribution of orientations over the range [?θ] _ [θ] is used, also with respect to a horizontal line. In each case θ is gradually decreased from 90° to 0°. Conductivity is measured both in directions parallel and perpendicular to alignment.

Researchers found that a significant improvement in conductivity parallel to direction of alignment can be obtained by slightly restricting orientation of the uniform distribution. This improvement, however, comes at the expense of a larger drop in perpendicular conductivity. The general form of these results matches that demonstrated by researchers experimenting with carbon nanotube films. Surprisingly, it was found that the highly ordered second case is unable to outperform isotropic networks for any value of θ; thus demonstrating that continuous orientation configurations with some degree of randomness are preferable to highly ordered configurations.

Prior research in this field has studied the effects of orientation on conductivity of 3D carbon nanotube composites, finding that a slight degree of alignment improves conductivity. Computational models have been used to study how percolation probability of 2D random rod dispersions is affected by rod orientation. Others have developed a more sophisticated computational model capable of calculating conductivity of 3D rod dispersions, again finding that a slight degree of axial alignment improves conductivity.

“Metal nanowire networks show great potential for application in various forms of technology,” said Jagota. “This computational model, which has proven itself accurate through its good fit with previously published data, has demonstrated quantitatively how different orientation configurations can impact conductivity of metal nanowire networks.”

“Restriction of orientation can improve conductivity in a single direction by significant amounts, which can be relevant in a variety of technologies where current flow is only required in one direction,” said Tansu. “Surprisingly, heavily controlled orientation configurations do not exhibit superior conductivity; some degree of randomness in orientation in fact acts to improve conductivity of the networks. This approach may have tremendous impacts on improving current spreading in optoelectronics devices, specifically on deep ultraviolet emitter with poor p-type contact layer.”