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Freescale Semiconductor today introduced its Intelligent Sensing Framework (ISF) 2.1, which now includes integration with Freescale’s Processor Expert tool to help create, configure, and generate embedded sensor-based applications for Freescale microcontrollers (MCUs). This integration, together with the framework’s sensor fusion functionality and expanded support for additional sensor types, speeds and simplifies the development of sensor-based solutions for the Internet of Tomorrow – from the connected home and wearables to new medical and connected industrial applications.

A large portion of new, sensor-based Internet of Things (IoT) solutions originate from startup organizations often unfamiliar with the complex process of abstracting, combining and using sensor data. As sensors become increasingly critical to the success of IoT applications, embedded developers need to find ways to quickly and easily integrate multiple streams of sensor data with the MCUs powering their applications.

To address this dynamic, the integration of Freescale’s ISF with Processor Expert development technology provides an easy-to-use tool that streamlines and simplifies the process of abstracting and incorporating multiple sensor data streams into a device or application based on Freescale’s popular families of Kinetis MCUs. Developers can then focus on how the sensor data is used, rather than how it is abstracted and combined.

“The growth of the IoT is enabling services to be created around products that were previously unconnected and unaware of the environments within which they operate,” said James Bates, SVP and GM for Freescale’s Analog and Sensors group. “At the heart of this transformation are intelligent sensor clusters that can deliver information wirelessly and securely. ISF, combined with Processor Expert technology, allows developers to create embedded applications using sensor clusters much more quickly. By removing the burden of abstracting and gathering sensor data, developers can focus on adding their own functionality and IP, driving new innovation for the IoT faster than ever before.”

Leveraging Freescale’s Kinetis MCUs, connectivity solutions, IoT protocols, and security solutions, ISF 2.1 can dramatically reduce time-to-market for sensor-based IoT applications. The framework can be deployed across a wide range of Freescale Kinetis MCUs, provides out-of-box support for the majority of Freescale’s intelligent sensors, and complements Freescale’s broad MCU enablement ecosystem to provide developers a seamless, integrated design environment for incorporating Freescale MCUs and sensors into customers’ embedded system designs.

ISF 2.1 is designed to grow with the Freescale sensor portfolio, and now integrates Freescale’s Sensor Fusion library as a drop-in Processor Expert orientation sensor component. This component enables full configuration of the underlying sensors and fusion algorithms. The framework can deliver sensor data in common engineering units which allow developers to switch between sensors without additional coding to support different device-specific formats. ISF is a key aspect for easily obtaining data to be used in Freescale’s Sensor Data Analytics workflow as demonstrated by the company’s embedded data logger for analytics.

By combining 3D holographic lithography and 2D photolithography, researchers from the University of Illinois at Urbana-Champaign have demonstrated a high-performance 3D microbattery suitable for large-scale on-chip integration with microelectronic devices.

“This 3D microbattery has exceptional performance and scalability, and we think it will be of importance for many applications,” explained Paul Braun, a professor of materials science and engineering at Illinois. “Micro-scale devices typically utilize power supplied off-chip because of difficulties in miniaturizing energy storage technologies. A miniaturized high-energy and high-power on-chip battery would be highly desirable for applications including autonomous microscale actuators, distributed wireless sensors and transmitters, monitors, and portable and implantable medical devices.”

CREDIT: University of Illinois

CREDIT: University of Illinois

“Due to the complexity of 3D electrodes, it is generally difficult to realize such batteries, let alone the possibility of on-chip integration and scaling. In this project, we developed an effective method to make high-performance 3D lithium-ion microbatteries using processes that are highly compatible with the fabrication of microelectronics,” stated Hailong Ning, a graduate student in the Department of Materials Science and Engineering and first author of the article, “Holographic Patterning of High Performance on-chip 3D Lithium-ion Microbatteries,” appearing in Proceedings of the National Academy of Sciences.

“We utilized 3D holographic lithography to define the interior structure of electrodes and 2D photolithography to create the desired electrode shape.” Ning added. “This work merges important concepts in fabrication, characterization, and modeling, showing that the energy and power of the microbattery are strongly related to the structural parameters of the electrodes such as size, shape, surface area, porosity, and tortuosity. A significant strength of this new method is that these parameters can be easily controlled during lithography steps, which offers unique flexibility for designing next-generation on-chip energy storage devices.”

Enabled by a 3D holographic patterning technique–where multiple optical beams interfere inside the photoresist creating a desirable 3D structure–the battery possesses well-defined, periodically structured porous electrodes, that facilitates the fast transports of electrons and ions inside the battery, offering supercapacitor-like power.

“Although accurate control on the interfering optical beams is required to construct 3D holographic lithography, recent advances have significantly simplified the required optics, enabling creation of structures via a single incident beam and standard photoresist processing. This makes it highly scalable and compatible with microfabrication,” stated John Rogers, a professor of materials science and engineering, who has worked with Braun and his team to develop the technology.

“Micro-engineered battery architectures, combined with high energy material such as tin, offer exciting new battery features including high energy capacity and good cycle lives, which provide the ability to power practical devices,” stated William King, a professor of mechanical science and engineering, who is a co-author of this work.

To the list of potential applications of graphene – a two-dimensional semiconductor of pure carbon that is stronger and much faster than silicon – we can now add valleytronics, the coding of data in the wavelike motion of electrons as they speed through a conductor. Berkeley Lab researchers have discovered topologically protected one-dimensional electron conducting channels at the domain walls of bilayer graphene. These conducting channels are “valley polarized,” which means they can serve as filters for electron valley polarization in future devices such as quantum computers.

“Combining near-field infrared nanometer-scale microscopy and low-temperature electrical transport measurements, we have recorded the first experimental observations of 1D ballistic electron conducting channels at bilayer graphene domain walls,” says Feng Wang, a condensed matter physicist with Berkeley Lab’s Materials Sciences Division, who led this work. “These 1D valley-polarized conducting channels featured a ballistic length of about 400 nanometers at 4 kelvin. Their existence opens up opportunities for exploring unique topological phases and valley physics in graphene.”

Wang, who also holds an appointment with the University of California (UC) Berkeley Physics Department and is a member of the Kavli Energy NanoScience Institute (Kavli-ENSI), is the corresponding author of a paper describing this research in the journal Nature. The lead authors of the paper are Long Ju and Zhiwen Shi, members of Wang’s research group. (See here for full list of authors.)

Valleytronics is generating a lot of excitement in the high-tech industry as a potential avenue to quantum computing. Like spintronics, valleytronics offers a tremendous advantage in data processing speeds over the electrical charge used in classical electronics.

“In valleytronics, electrons move through the lattice of a 2D semiconductor as a wave with two energy valleys, each valley being characterized by a distinct momentum and quantum valley number,” Wang says. “This quantum valley number can be used to encode information when the electrons are in a minimum energy valley.”

Recent theoretical work suggested that domain walls between AB- and BA-stacked bilayer graphene could provide an attractive place to realize one-dimensional electron conducting channels for valleytronics because the smoothness of the domain walls preserves electron valleys, unlike the atomic defects at graphene edges that result in valley-mixing. Until now, however, there has been no experimental evidence of these channels.

Working at Berkeley Lab’s Advanced Light Source (ALS), a DOE Office of Science User Facility, Wang, Ju, Shi and their colleagues used tightly focused beams of infrared light to image in situ bilayer graphene layer-stacking domain walls on device substrates. Field effect devices fabricated over these domain walls revealed the 1D conducting channels.

In the bilayer graphene imaging work by Feng Wang and his group, IR light (yellow) is focused onto the apex of a metal-coated AFM tip and the backscattered infrared radiation is collected and measured.

“The infrared measurements were carried out at ALS beamline 5.4,” says Shi. “The near-field infrared capabilities of this beamline enable optical spectroscopy with spatial resolutions that are way beyond the diffraction limit, allowing us to image the nanometer-wide domain walls in bilayer graphene.”

Adds Ju, “That we were able to image the domain walls with a technique that is compatible with device fabrication was key to our work. With near-field IR spectroscopy, we could directly fabricate field effect devices over the domain walls and detect the 1D conducting channels.”

To date, most valleytronics research has focused on the 2D semiconductors known as MX2 materials, which consist of a single layer of transition metal atoms, such as molybdenum or tungsten, sandwiched between two layers of chalcogen atoms, such as sulfur. The results of this study demonstrate that protected topological phases can also be realized in bilayer graphene, which is a tunable semiconductor, making the 2D carbon sheets useful for valleytronic applications.

“Our next step is to increase the ballistic length of these 1D channels so we can utilize them as electron valley filters, as well as for other manipulations of electron valleys in graphene,” Wang says.

New tests show in real-time that cracks can run on top of and through metal layers.

BY K. VANSTREELS, I. DE WOLF, H. ZAHEDMANESH, H. BENDER, M. GONZALEZ, J. LEFEBVRE, AND S. BHOWMICK, imec, Leuven, Belgium

Imec, with the help of equipment supplier Hysitron, developed a new test method to study crack formation in Cu/low-k back-end-of-line (BEOL) stacks. By combining a PicoIndenter, a scanning electron microscope (SEM) and unique sample preparation using a focused ion beam (FIB), it becomes possible to visualize in real-time crack initiation and propagation (See video). Insight into this reliability issue allows to optimize BEOL design, material choices and process steps to strengthen the BEOL.

Porosity of low-k materials affects the BEOL’s mechanical strength

Porous low-k materials are introduced in the BEOL of chips to improve its performance. More specifically, low-k materials prevent leakage between metal interconnections of the circuitry and minimize the time delay. In research, low-k materials with k-values lower than 2.0 are tested. These are very porous and reduce the mechanical strength of the BEOL stack.

SEM picture of crack formation in the back-end-of-line.

SEM picture of crack formation in the back-end-of-line.

Due to the reduced mechanical strength of Cu/ low-k BEOL stacks, cracks can be formed when local mechanical stresses become too high. This can occur during chip processing, during packaging, and during use of the end products. The stresses can be caused by temperature fluctuations, due to thermal mismatch of materials; or by shrinkage of materials during curing; by local forces during bonding; or even due to external mechanical impact caused by drop or shock. Since this crack formation is an important reliability issue for future technology nodes, tests are being developed to gain insight into this problem. For example, there is the four-point bending test and the BABSI test which measure the force at which cracking starts. However, with these tests it is not possible to follow in-situ and in real-time how the crack initiates and propagates through the BEOL stack. With the new test method, this hidden world reveals itself.

The new test

FIGURE 1. Schematic overview of the sample preparation. Using a Focus Ion Beam, a double clamped BEOL beam sample is made.

FIGURE 1. Schematic overview of the sample preparation. Using a Focus Ion Beam, a double clamped BEOL beam sample is made.

For the new test, a PicoIndenter is integrated into a SEM microscope. The sample has to be prepared in such a way that a beam is formed out of the back-end- of-line stack (see FIGURE 1). Imec was able to make such BEOL beams with the Focused Ion Beam (FIB) technique. This involved several steps as depicted in FIGURE 1. The sample is then placed in the SEM. With the PicoIndenter, a gradual force is applied on top of the beam while the SEM continuously images the cross-section of the BEOL (side view of the beam). In this way, a movie can be made revealing the crack initiation and propagation, while at the same time measuring the force that is applied (FIGURE 2).

FIGURE 2. Force-displacement curve and corresponding SEM pictures, as measured with the new test method. The pictures reveal beam bending (a to c), crack initiation (d) and crack growth (e to h).

FIGURE 2. Force-displacement curve and corresponding SEM pictures, as measured with the new test method. The pictures reveal beam bending (a to c), crack initiation (d) and crack growth (e to h).

Conclusions and future work

This new test has proven to be very relevant for further development of Cu/low-k BEOL stacks. In this phase, only a few BEOL beams – with different dimensions – were tested and measured. From these initial results it can be concluded that cracks run on top of metal layers in this device, and even through metal layers. This can point out that the interface at the top of metal layers should be strengthened for the studied technology, either by BEOL design, material choices or optimization of process steps (such as cleaning).

By setting up more experiments, a model can be made (FEM) to predict crack formation in specific BEOL stacks. The experiments will allow to validate the model. In this way, this new test method is an important tool in the development of reliable chips made in future technology nodes with copper and low-k materials in the back-end-of-line.

This article is based on the paper “In-situ scanning electron microscopy study of fracture events during back-end-of-line microbeam bending tests” which was published in Applied Physics Letters 105, 213102 (2014). AUTHORS: K. VANSTREELS, I. DE WOLF, H. ZAHEDMANESH, H. BENDER, M. GONZALEZ, J. LEFEBVRE, AND S. BHOWMICK

A JEOL e-beam lithography system will soon be a new resource for quantum information science researchers that utilize the cutting-edge facilities at the University of Waterloo Quantum NanoFab in Waterloo, Ontario. The JEOL JBX-6300FS e-beam system will be used to write circuitry patterns at very high resolution and linewidths as small as 8nm. With accelerating voltage capability to 100kV, high resolution patterns can be written on substrates coated in thick resist.

“We’re very excited to obtain this 100kV system.” said Vito Logiudice, Director of Operations for the Quantum NanoFab.  “This opens the lab up for certain types of research where people need to use thick resist all while pushing the limits on minimum feature size.”  The new system will be an integral part of the Quantum Nanofab’s goal of providing the tools needed for next-generation quantum devices.

The challenge of creating ever more powerful microchips, which continue to shrink in size, demands new technologies on the scale of individual atoms, or the quantum scale.  Through the work being done in the Quantum Nanofab, which serves the Institute for Quantum Computing (IQC) and the Waterloo Institute for Nanotechnology (WIN), the University of Waterloo is poised to make that leap. Researchers will be able to “corral” single electrons through the lithography patterns they will write using the JEOL JBX-6300FS.

“This new e-beam system is going to be extremely helpful in that regard. They will be able to further advance their work on gate defined quantum dots with metal gates < 20nm wide and metal-to-metal spacing of less than 40nm,” Logiudice explains.

The e-beam will also write both large and very fine features in the same layer on the substrate, using high resolution as well as coarse writing modes, which can be programmed into a batch process run overnight.

“This will be of great benefit for the writing of superconducting Josephson junction qubits and the microwave circuits that are used to manipulate their states.” adds Nathan Nelson-Fitzpatrick, Nanofabrication Process Engineer on the Quantum NanoFab team.

JBX 6300FS Offers Flexible User Experience

An attractive aspect of the JBX 6300FS is the wide spectrum of user experience the system can now accommodate.  The University of Waterloo is teaming up with JEOL and Cornell University’s Nanofabrication Facility to showcase the system’s dual interfaces, both a traditional GUI/Graphical User Interface and a powerful Python-based scripting language.  With scripting, power users can manipulate incoming data and perform exposures based on non-periodic arrays or logarithmic dose arrays, for example.  However, that same scripting power allows the creation of new GUI’s based on the comfort or training level of the user.

“The 6300FS hardware is as flexible as the software, a core strength that comes from being one of the founding EBL solutions providers in the industry that has continually provided the latest in technology for advances in research,” said JEOL EBL product manager, Zane Marek. “Though the University of Waterloo continues to grow, their substrates might actually start to shrink. As research on exotic materials continues – and those substrate prices remain ‘exotic’ – JEOL has secured the ability to confidently load and expose them.”

Marek added, “We have the best customers in the world. They work with us and their peers at other facilities to discover novel ways to load and expose the smallest of these exotic materials. We really are in this together.”

Technology Hub in Waterloo

Known as the Quantum Valley, the Waterloo Region is home to the Institute for Quantum Computing (IQC) and the Waterloo Institute for Nanotechnology (WIN) at the University of Waterloo. The Quantum NanoFab serves both institutes in its location in the 280,000 sq. ft. Mike & Ophelia Lazaridis Quantum-Nano Centre. Since its opening in September 2014, the Quantum NanoFab has been host to some 90 new users under the direction of 25 different faculty members at the university. Plans are in place to allow more users from outside the university in the near future.

The University of Waterloo boasts a unique Intellectual Property policy where IP is inventor owned. “This policy attracts entrepreneurs and researchers to the University of Waterloo,” says Loguidice. “Coupled with the largest co-op program in North America, Waterloo gives our students a definite edge for their future endeavors both in the private and public sectors.”

JEOL EBL Expertise

JEOL has a long history of e-beam innovation and expertise, with more than 45 years of design, production, and support of the company’s lithography tools, which include photomask writing and direct write systems. The JBX-6300FS can easily write patterns down to 8nm or less using an electron optics system that automatically adjusts a 2.1nm electron beam at 100kV accelerating voltage. It also achieves high field-stitching and overlay accuracy of 9nm or less, providing high cost performance. An automatic correction function developed by JEOL enables high-precision pattern writing. The JBX-6300FS can write highly precise patterns even at field corners and boundaries by the use of its powerful electron optical system that automatically corrects distortions generated by beam deflection.

The company’s serves the Americas with both sales and support through its main USA office in Peabody, Massachusetts, and with offices in Canada, Mexico, and Brasil.

By Pete Singer, Editor-in-Chief

Although the Xpedition was announced last week, it has been used in production for over two years. says five companies have been using it, two of which are extremely large semiconductor companies. “It’s a pretty mature technology,” he said.

Traditionally, chip, package and board designers have used relatively archaic means of communicating, including spreadsheets, whiteboard drawings and Microsoft’s VISIO (a diagramming and vector graphics application). Each group often uses different naming conventions as well, which further complicates co-design efforts.

“They try to use non-EDA technology to figure out an EDA problem,” said John Park, Methodology Architect, Systems Design Division at Mentor Graphics (Longmont, CO).

A new product from Mentor Graphics called Xpedition® Package Integrator provides a new methodology and platform in addition to a new suite of EDA tools. The platform enables chip, package and board designers to easily see how changing various design elements impact adjacent designs, an industry first.

Xpedition allows designers to pull in existing data in whatever form they’re presently using and examine different design considerations such as connectivity across all three design domains. “We’re aggregating people’s existing flow. We’re not replacing them,” Park said.

Park said the development of Xpedition was driven by the general need to simplify co-design, but also to address news challenges created by the Internet of Things (IoT) and new technology such as 2.5 and 3D integration and through-silicon-vias (TSVs). “You’re talking fairly sophis- ticated connectivity management when dealing with multiple die, the interposer and modeling that connec- tivity all the way up to the boards,” Park said. “It’s a pretty challenging problem for most people who have historically tried to use spreadsheets to manage that cross-domain connectivity.”

The Xpedition Package Integrator product also provides the industry’s first formal flow for ball grid array (BGA) ball-map planning and optimization based on an “intelligent pin” concept, defined by user rules. In addition, a new multi-mode connectivity management system (incorporating hardware description language (HDL), spreadsheet and graphical schematic) provides cross-domain pin-mapping and system level cross-domain logical verification (FIGURE 1).

FIGURE 1. With Mentor Graphics Xpedition Package Integrator solution, users manage connectivity in the design environment in which they are most comfortable.

FIGURE 1. With Mentor Graphics Xpedition Package Integrator solution, users manage connectivity in
the design environment in which they are most comfortable.

A modern day CPU or GPU has three of four packaging options, such as package-on-package, micro-BGA, or package-on-package (PiP). People are also targeting multiple end form factors. “It’s not a single board anymore,” Park said. “A lot of customers want to look at the device in the context of smartphone platform, a tablet platform or a set-top box platform, for example.”

One of the main advantages of the new platform is cost reduction by efficient layer reduction, optimized interconnect paths, and streamlined/automated control of the design process. “What’s really changing with IoT and with TSVs and expensive packages is people now want to do cross-domain exploration or path finding,” Park said. People evaluate options largely based on cost, performance and reliability. For example, designers want to look at the pros and cons if they take DRAM off the board and move them into the package.

Researchers from North Carolina State University and China’s Suzhou Institute of Nano-Science and Nano-Biotics have developed an inexpensive technique called “microcombing” to align carbon nanotubes (CNTs), which can be used to create large, pure CNT films that are stronger than any previous such films. The technique also improves the electrical conductivity that makes these films attractive for use in electronic and aerospace applications.

“It’s a simple process and can create a lightweight CNT film, or ‘bucky paper,’ that is a meter wide and twice as strong as previous such films – it’s even stronger than CNT fibers,” says Yuntian Zhu, Distinguished Professor of Materials Science and Engineering at NC State and corresponding author of a paper describing the work.

The researchers begin by growing the CNTs on a conventional substrate in a closely packed array. The CNTs are tangled together, so when researchers pull on one end of the array the CNTs form a continuous ribbon that is only nanometers thick. This ribbon is attached to a spool, which begins winding the ribbon up.

As the spool pulls, the CNT ribbon is dragged between two surgical blades. While the blades appear straight to the naked eye, they actually have micrometer-scale fissures on their cutting edge. These fissures create a kind of “microcomb” that pulls the CNTs into alignment – just as a regular comb sorts through tangled hair.

When the ribbon of aligned CNTs is being wound onto the spool, the researchers apply an alcohol solution. This pulls the CNTs closer together, strengthening the bonds between CNTs.

The CNT ribbon wraps around itself as it winds around the spool, creating a layered film of pure CNTs. Researchers can control the thickness of the film by controlling the number of layers.

The CNT films made using the microcombing technique had more than twice the tensile strength of the uncombed CNT films – greater than 3 gigapascals for the microcombed material, versus less than 1.5 gigapascals for the uncombed material.

The microcombed CNT film also had 80 percent higher electrical conductivity than the uncombed film.

“This is a significant advance, but we want to find ways to make CNT alignment even straighter,” Zhu says. “It’s still not perfect.

“In addition, the technique would theoretically be easy to scale up for large-scale production. We’d like to find an industry partner to help us scale this up and create a material for the marketplace.”

Researchers at the University of Rochester have shown that defects on an atomically thin semiconductor can produce light-emitting quantum dots. The quantum dots serve as a source of single photons and could be useful for the integration of quantum photonics with solid-state electronics – a combination known as integrated photonics.

Scientists have become interested in integrated solid-state devices for quantum information processing uses. Quantum dots in atomically thin semiconductors could not only provide a framework to explore the fundamental physics of how they interact, but also enable nanophotonics applications, the researchers say.

Quantum dots are often referred to as artificial atoms. They are artificially engineered or naturally occurring defects in solids that are being studied for a wide range of applications. Nick Vamivakas, assistant professor of optics at the University of Rochester and senior author on the paper, adds that atomically thin, 2D materials, such as graphene, have also generated interest among scientists who want to explore their potential for optoelectronics. However, until now, optically active quantum dots have not been observed in 2D materials.

In a paper published in Nature Nanotechnology this week, the Rochester researchers show how tungsten diselenide (WSe2) can be fashioned into an atomically thin semiconductor that serves as a platform for solid-state quantum dots. Perhaps most importantly the defects that create the dots do not inhibit the electrical or optical performance of the semiconductor and they can be controlled by applying electric and magnetic fields.

Vamivakas explains that the brightness of the quantum dot emission can be controlled by applying the voltage. He adds that the next step is to use voltage to “tune the color” of the emitted photons, which can make it possible to integrate these quantum dots with nanophotonic devices.

A key advantage is how much easier it is to create quantum dots in atomically thin tungsten diselenide compared to producing quantum dots in more traditional materials like indium arsenide.

“We start with a black crystal and then we peel layers of it off until we have an extremely thin later left, an atomically thin sheet of tungsten diselenide,” said Vamivakas.

The researchers take two of these atomically thin sheets and lay one over the other one. At the point where they overlap, a quantum dot is created. The overlap creates a defect in the otherwise smooth 2D sheet of semiconductor material. The extremely thin semiconductors are much easier to integrate with other electronics.

The quantum dots in tungsten diselenide also possess an intrinsic quantum degree of freedom – the electron spin. This is a desirable property as the spin can both act as a store of quantum information as well as provide a probe of the local quantum dot environment.

“What makes tungsten diselenide extremely versatile is that the color of the single photons emitted by the quantum dots is correlated with the quantum dot spin,” said first author Chitraleema Chakraborty. Chakraborty added that the ease with which the spins and photons interact with one another should make these systems ideal for quantum information applications as well as nanoscale metrology.

A revolution is coming in flexible electronic technologies as cheaper, more flexible, organic transistors come on the scene to replace expensive, rigid, silicone-based semiconductors, but not enough is known about how bending in these new thin-film electronic devices will affect their performance, say materials scientists at the University of Massachusetts Amherst.

Writing in the current issue of Nature Communications, polymer scientists Alejandro Briseño and Alfred Crosby at UMass Amherst, with their doctoral student Marcos Reyes-Martinez, now a postdoctoral researcher at Princeton, report results of their recent investigation of how micro-scale wrinkling affects electrical performance in carbon-based, single-crystal semiconductors.

They are the first to apply inhomogeneous deformations, that is strain, to the conducting channel of an organic transistor and to understand the observed effects, says Reyes-Martinez, who conducted the series of experiments as part of his doctoral work.

As he explains, “This is relevant to today’s tech industry because transistors drive the logic of all the consumer electronics we use. In the screen on your smart phone, for example, every little pixel that makes up the image is turned on and off by hundreds of thousands or even millions of miniaturized transistors.”

“Traditionally, the transistors are rigid, made of an inorganic material such as silicon,” he adds. “We’re working with a crystalline semiconductor called rubrene, which is an organic, carbon-based material that has performance factors, such as charge-carrier mobility, surpassing those measured in amorphous silicon. Organic semiconductors are an interesting alternative to silicon because their properties can be tuned to make them easily processed, allowing them to coat a variety of surfaces, including soft substrates at relatively low temperatures. As a result, devices based on organic semiconductors are projected to be cheaper since they do not require high temperatures, clean rooms and expensive processing steps like silicon does.”

Until now, Reyes-Martinez notes, most researchers have focused on controlling the detrimental effects of mechanical deformation to a transistor’s electrical properties. But in their series of systematic experiments, the UMass Amherst team discovered that mechanical deformations only decrease performance under certain conditions, and actually can enhance or have no effect in other instances.

“Our goal was not only to show these effects, but to explain and understand them. What we’ve done is take advantage of the ordered structure of ultra-thin organic single crystals of rubrene to fabricate high-perfomance, thin-film transistors,” he says. “This is the first time that anyone has carried out detailed fundamental work at these length scales with a single crystal.”

Though single crystals were once thought to be too fragile for flexible applications, the UMass Amherst team found that crystals ranging in thickness from about 150 nanometers to 1 micrometer were thin enough to be wrinkled and applied to any elastomer substrate. Reyes-Martinez also notes, “Our experiments are especially important because they help scientists working on flexible electronic devices to determine performance limitations of new materials under extreme mechanical deformations, such as when electronic devices conform to skin.”

They developed an analytical model based on plate bending theory to quantify the different local strains imposed on the transistor structure by the wrinkle deformations. Using their model they are able to predict how different deformations modulate charge mobility, which no one had quantified before, Reyes-Martinez notes.

Schematic of wrinkled rubrene single-crystal field-effect transistor. Wrinkles are obtained when in-plane compressive strain is applied on the elastomeric substrate. Electric current between gold (Au) electrodes is modulated by the deformation imposed by the wrinkles. Credit: UMass Amherst

These contributions “represent a significant step forward in structure-function relationships in organic semiconductors, critical for the development of the next generation of flexible electronic devices,” the authors point out.

Dow Electronic Materials, a business unit of The Dow Chemical Company, today announced that its SOLDERON BP TS 6000 Tin-Silver Plating Chemistry was honored as a Bronze 2015 Edison Award winner in the Material Science: Manufacturing category.

Removing lead from solders used in electronics is a difficult technical challenge because it has unique properties that ensure device performance and reliability. SOLDERON BP TS 6000 Tin-Silver delivers a lead-free chemistry that not only creates critical connections in electronic devices, but also doubles the productivity with the market’s highest plating speed. The award recognizes Dow Electronic Materials for its development of this novel plating chemistry designed to provide advanced semiconductor packaging customers with a balance of performance and cost to enable the next generation of high-performance electronic devices, without the use of lead.

“This award showcases Dow’s ability to develop game-changing chemistry that advances the microelectronics industry while meeting customer and industry requirements for high-volume manufacturing,” said Cathie Markham, chief technology officer, Dow Electronic Materials. “The scientists who contributed to making these advances possible have collaborated closely with our customers and industry partners to understand their challenges and requirements. It is truly an honor to have our scientists and their innovations recognized by the Edison Awards.”

Dow is proud to recognize its scientists, engineers and marketers who contributed to the development of SOLDERON BP TS 6000 Tin-Silver: Jeff Calvert, Regina Cho, Jin-Sil Choi, Lou Grippo, Masaaki Imanari, Yoon-Joo Kim, Inho Lee, Yil-Hak Lee, Won-Hyun Lee, Sang-Min Park, Jonathan Prange, Yi Qin, Alex Saniuk, Taylor Wang, Julia Woertink, Ju-Mi Yun, Sam Epstein, Scott Shpunt, Kristen Finnemore, Yung-Rai Lee, Jim MacDuff, Willis Martin, Jeff Weber, Brianna Gagnon and Jianwei Dong.

The Edison Awards ceremony took place on April 23, 2015 at the Edison Awards Annual Gala in New York City. Inspired by Thomas Edison’s persistence and inventiveness, this distinguished award recognizes innovation, creativity, and ingenuity in the global economy.

SOLDERON BP TS 6000 Tin-Silver was one of five Dow products to receive a 2015 Edison Award at the gala event. Dow’s other recognized products include BETAMATE Structural Adhesives, PacXpert Packaging Technology, POLYOX Water-Soluble Polymers and AFFINISOL HPMC HME. For more information regarding Dow’s innovations in science and sustainability, visit dow.com.