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Researchers from the Georgia Institute of Technology have developed a novel cellular sensing platform that promises to expand the use of semiconductor technology in the development of next-generation bioscience and biotech applications.

The research is part of the Semiconductor Synthetic Biology (SSB) program sponsored and managed by Semiconductor Research Corporation (SRC). Launched in 2013, the SSB program concentrates on synergies between synthetic biology and semiconductor technology that can foster exploratory, multi-disciplinary, longer-term university research leading to novel, breakthrough solutions for a wide range of industries.

The Georgia Tech research proposes and demonstrates the world’s first multi-modality cellular sensor arranged in a standard low-cost CMOS process. Each sensor pixel can concurrently monitor multiple different physiological parameters of the same cell and tissue samples to achieve holistic and real-time physiological characterizations.

“Our research is intended to fundamentally revolutionize how biologists and bioengineers can interface with living cells and tissues and obtain useful information,” said Hua Wang, an assistant professor in the School of Electrical and Computer Engineering (ECE) at Georgia Tech. “Fully understanding the physiological behaviors of living cells or tissues is a prerequisite to further advance the frontiers of bioscience and biotechnology.”

Wang explains that the Georgia Tech research can have positive impact on semiconductors being used in the development of healthcare applications including the more cost-effective development of pharmaceuticals and point-of-care devices and low-cost home-based diagnostics and drug testing systems. The research could also benefit defense and environmental monitoring applications for low-cost field-deployable sensors for hazard detections.

Specifically, in the case of the more cost-effective development of pharmaceuticals, the increasing cost of new medicine is largely due to the high risks involved in the drug development. As a major sector of the healthcare market, the global pharmaceutical industry is expected to reach more than $1.2 trillion this year. However, on average, only one out of every ten thousand tested chemical compounds eventually become an approved drug product.

In the early phases of drug development (when thousands of chemical candidates are screened), in vitro cultured cells and tissues are widely used to identify and quantify the efficacy and potency of drug candidates by recording their cellular physiology responses to the tested compounds, according to the research.

Moreover, patient-to-patient variations often exist even under the administration of the same type of drugs at the same dosage. If the cell samples are derived from a particular patient, patient-specific drug responses then can be tested, which opens the door to future personalized medicine.

“Therefore, there is a tremendous need for low-cost sensing platforms to perform fast, efficient and massively parallel screening of in vitro cells and tissues, so that the promising chemical candidates can be selected efficiently,” said Wang, who also holds the Demetrius T. Paris Junior Professorship in the Georgia Tech School of ECE. “This existing need can be addressed directly by our CMOS multi-modality cellular sensor array research.”

Among the benefits enabled by the CMOS sensor array chips are that they provide built-in computation circuits for in-situ signal processing and sensor fusion on multi-modality sensor data. The chips also eliminate the need of external electronic equipment and allow their use in general biology labs without dedicated electronic or optical setups.

Additionally, thousands of sensor array chips can operate in parallel to achieve high-throughput scanning of chemicals or drug candidates and real-time monitoring of their efficacy and toxicity. Compared with sequential scanning through limited fluorescent scanners, this parallel scanning approach can achieve more than 1,000 times throughput enhancement.

The Georgia Tech research team just wrapped its first year of research under the 3-year project, with the sensor array being demonstrated at the close of 2014 and presented at the IEEE International Solid-State Circuits Conference (ISSCC) in February 2015. In the next year, the team plans to further increase the sensor array pixel density while helping improve packaging solutions compatible with existing drug testing solutions. 

“Georgia Tech’s research combines semiconductor integrated circuits and living cells to create an electronics-biology hybrid platform, which has tremendous societal and technological implications that can potentially lead to better and cheaper healthcare solutions,” said Victor Zhirnov, director of Cross-Disciplinary Research and Special Projects at SRC.

In 2013 James Hone, Wang Fong-Jen Professor of Mechanical Engineering at Columbia Engineering, and colleagues at Columbia demonstrated that they could dramatically improve the performance of graphene–highly conducting two-dimensional (2D) carbon–by encapsulating it in boron nitride (BN), an insulating material with a similar layered structure. In work published this week in the Advance Online Publication on Nature Nanotechnology‘s website, researchers at Columbia Engineering, Harvard, Cornell, University of Minnesota, Yonsei University in Korea, Danish Technical University, and the Japanese National Institute of Materials Science have shown that the performance of another 2D material–molybdenum disulfide (MoS2)–can be similarly improved by BN-encapsulation.

“These findings provide a demonstration of how to study all 2D materials,” says Hone, leader of this new study and director of Columbia’s NSF-funded Materials Research Science and Engineering Center. “Our combination of BN and graphene electrodes is like a ‘socket’ into which we can place many other materials and study them in an extremely clean environment to understand their true properties and potential. This holds great promise for a broad range of applications including high-performance electronics, detection and emission of light, and chemical/bio-sensing.”

Two-dimensional (2D) materials created by “peeling'” atomically thin layers from bulk crystals are extremely stretchable, optically transparent, and can be combined with each other and with conventional electronics in entirely new ways. But these materials–in which all atoms are at the surface–are by their nature extremely sensitive to their environment, and their performance often falls far short of theoretical limits due to contamination and trapped charges in surrounding insulating layers. The BN-encapsulated graphene that Hone’s group produced last year has 50× improved electronic mobility–an important measure of electronic performance–and lower disorder that enables the study of rich new phenomena at low temperature and high magnetic fields.

“We wanted to see what we could do with MoS2–it’s the best-studied 2D semiconductor, and, unlike graphene, it can form a transistor that can be switched fully ‘off’, a property crucial for digital circuits,” notes Gwan-Hyoung Lee, co-lead author on the paper and assistant professor of materials science at Yonsei. In the past, MoS2 devices made on common insulating substrates such as silicon dioxide have shown mobility that falls below theoretical predictions, varies from sample to sample, and remains low upon cooling to low temperatures, all indications of a disordered material. Researchers have not known whether the disorder was due to the substrate, as in the case of graphene, or due to imperfections in the material itself.

In the new work, Hone’s team created heterostructures, or layered stacks, of MoS2 encapsulated in BN, with small flakes of graphene overlapping the edge of the MoS2 to act as electrical contacts. They found that the room-temperature mobility was improved by a factor of about 2, approaching the intrinsic limit. Upon cooling to low temperature, the mobility increased dramatically, reaching values 5-50× that those measured previously (depending on the number of atomic layers). As a further sign of low disorder, these high-mobility samples also showed strong oscillations in resistance with magnetic field, which had not been previously seen in any 2D semiconductor.

“This new device structure enables us to study quantum transport behavior in this material at low temperature for the first time,” added Columbia Engineering PhD student Xu Cui, the first author of the paper.

By analyzing the low-temperature resistance and quantum oscillations, the team was able to conclude that the main source of disorder remains contamination at the interfaces, indicating that further improvements are possible.

“This work motivates us to further improve our device assembly techniques, since we have not yet reached the intrinsic limit for this material,” Hone says. “With further progress, we hope to establish 2D semiconductors as a new family of electronic materials that rival the performance of conventional semiconductor heterostructures–but are created using scotch tape on a lab-bench instead of expensive high-vacuum systems.”

The ability of materials to conduct heat is a concept that we are all familiar with from everyday life. The modern story of thermal transport dates back to 1822 when the brilliant French physicist Jean-Baptiste Joseph Fourier published his book “Théorie analytique de la chaleur” (The Analytic Theory of Heat), which became a corner stone of heat transport. He pointed out that the thermal conductivity, i.e., ratio of the heat flux to the temperature gradient is an intrinsic property of the material itself.

The advent of nanotechnology, where the rules of classical physics gradually fail as the dimensions shrink, is challenging Fourier’s theory of heat in several ways. A paper published in ACS Nano and led by researchers from the Max Planck Institute for Polymer Research (Germany), the Catalan Institute of Nanoscience and Nanotechnology (ICN2) at the campus of the Universitat Autònoma de Barcelona (UAB) (Spain) and the VTT Technical Research Centre of Finland (Finland) describes how the nanometre-scale topology and the chemical composition of the surface control the thermal conductivity of ultrathin silicon membranes. The work was funded by the European Project Membrane-based phonon engineering for energy harvesting (MERGING).

The results show that the thermal conductivity of silicon membranes thinner than 10 nm is 25 times lower than that of bulk crystalline silicon and is controlled to a large extent by the structure and the chemical composition of their surface. Combining state-of-the-art realistic atomistic modelling, sophisticated fabrication techniques, new measurement approaches and state-of-the-art parameter-free modelling, researchers unravelled the role of surface oxidation in determining the scattering of quantized lattice vibrations (phonons), which are the main heat carriers in silicon.

Both experiments and modelling showed that removing the native oxide improves the thermal conductivity of silicon nanostructures by almost a factor of two, while successive partial re-oxidation lowers it again. Large-scale molecular dynamics simulations with up to 1,000,000 atoms allowed the researchers to quantify the relative contributions to the reduction of the thermal conductivity arising from the presence of native SiO2 and from the dimensionality reduction evaluated for a model with perfectly specular surfaces.

Silicon is the material of choice for almost all electronic-related applications, where characteristic dimensions below 10nm have been reached, e.g. in FinFET transistors, and heat dissipation control becomes essential for their optimum performance. While the lowering of thermal conductivity induced by oxide layers is detrimental to heat spread in nanoelectronic devices, it will turn useful for thermoelectric energy harvesting, where efficiency relies on avoiding heat exchange across the active part of the device.

The chemical nature of surfaces, therefore, emerges as a new key parameter for improving the performance of Si-based electronic and thermoelectric nanodevices, as well as of that of nanomechanical resonators (NEMS). This work opens new possibilities for novel thermal experiments and designs directed to manipulate heat at such scales.

New work from Carnegie’s Russell Hemley and Ivan Naumov hones in on the physics underlying the recently discovered fact that some metals stop being metallic under pressure. Their work is published in Physical Review Letters.

Metals are compounds that are capable of conducting the flow of electrons that make up an electric current. Other materials, called insulators, are not capable of conducting an electric current. At low temperatures, all materials can be classified as either insulators or metals.

Insulators can be pushed across the divide from insulator to metal by tuning their surrounding conditions, particularly by placing them under pressure. It was long believed that once such a material was converted into a metal under pressure, it would stay that way forever as the pressure was increased. This idea goes back to the birth of quantum mechanics in the early decades of the last century.

But it was recently discovered that certain groups of metals become insulating under pressure-a remarkable finding that was not previously thought possible.

For example, lithium goes from being a metallic conductor to a somewhat resistant semiconductor under around 790,000 times normal atmospheric pressure (80 gigapascals) and then becomes fully metallic again under around 1.2 million times normal atmospheric pressure (120 gigapascals). Sodium enters an insulating state at pressures of around 1.8 million times normal atmospheric pressure (180 gigapascals). Calcium and nickel are predicted to have similar insulating states before reverting to being metallic.

Hemley and Naumov wanted to determine the unifying physics framework underlying these unexpected metal-to-insulator-to-metal transitions.

“The principles we developed will allow for predictions of when metals will become insulators under pressure, as well as the reverse, the when-insulators-can-become-metals transition,” Naumov said.

The onsets of these transitions can be determined by the positions of electrons within the basic structure of the material. Insulators typically become metallic by a reduction in the spacing between atoms in the material. Hemley and Naumov demonstrated that for a metal to become an insulator, these reduced-spacing overlaps must be organized in a specific kind of asymmetry that was not previously recognized. Under these conditions, electrons localize between the atoms and do not freely flow as they do in the metallic form.

“This is yet another example of how extreme pressure is an important tool for advancing our understanding principles of the nature of materials at a fundamental level. The work will have implications for the search for new energy materials.” Hemley said.

Synopsys, Inc. today announced new extensions to its open-source Interconnect Technology Format (ITF) which enable modeling of complex device and interconnect parasitic effects at the advanced 10-nanometer (nm) process node. The new extensions include modeling of variation effects due to multi-patterning technology (MPT). Synopsys collaborated with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) (member list available at www.imtab.org), an IEEE-ISTO Federation Member Program, to define and ratify these new extensions. They will be available in the upcoming open-source ITF version 2015.06.

“Enabling productive design and analysis for a colored layout flow, while also providing a solution to model increased parasitic variation due to MPT approaches, is critical at 10nm,” said Bari Biswas, vice president of engineering for extraction solutions at Synopsys and chair of IMTAB. “Through our collaboration with IMTAB members and leading foundries, Synopsys developed an innovative solution that extended the existing variation models in ITF to become intrinsically color-aware to more accurately model mask dependency while fitting seamlessly into a designer’s existing flow.”

“ITF continues to be the cornerstone of parasitic modeling in the semiconductor industry,” said Marco Migliaro, President, IEEE-ISTO. “The new 10nm models represent the fourth successive generation of model extensions fostered by the IMTAB consortium.  IEEE-ISTO looks forward to continuing our support of the IMTAB mission to drive increased tool interoperability through the ITF common open-source modeling format.”

MPT is an evolution of the double patterning technology (DPT) first introduced by foundries at the 20nm process node, and it further extends the use of immersion lithography to 10nm and below. However, MPT imposes tighter requirements on design implementation and analysis to support layout decomposition into different masks (coloring) and manage increased variation due to misalignment of the multiple masks. Synopsys’ advanced MPT solution ratified by IMTAB for 10 nm includes color-aware models that cover all leading foundry manufacturing techniques including sequential litho-etch patterning, for example, triple patterning (LELELE) and quadruple patterning (LELELELE), as well as spacer-assisted/self-aligned patterning, for example, self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP).

In addition to MPT modeling, Synopsys has introduced other ITF extensions approved by IMTAB for more accurate via resistance and device capacitance extraction at advanced FinFET process nodes. At 10nm, via resistivity has increased significantly with growing conductor environment context, so the existing self-aligned via resistance variation model has been extended to include coverage from top and bottom conductors. In addition, new ITF models have been added to accurately extract the floating gate to diffusion contact capacitance for polycide on diffusion edge (PODE) devices and spacer dielectric between gate polycide and contact, both of which are critical to regulating device performance.

More information on the new ITF extensions for 10nm can be found in the ITF specifications version 2015.06, targeted for release in June 2015.

Additional proposals for 10nm and below process modeling are planned for review in the next IMTAB meeting scheduled for Tuesday, June 9, 2015 in San Francisco, CA, USA.

MagnaChip Semiconductor Corporation, a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products announced today that it has kicked-off an Internet of Things (IoT) task force and will offer diversified products with ultra-low power technology in anticipation of the fast growing IoT market. Gartner estimates that the processing, sensing and communications segments of the IoT market will grow at a compound annual growth rate (CAGR) of 29.2 percent from $7B in 2013 to $43B by 2020. This rapid growth rate outpaces the rest of the semiconductor industry which is predicted to grow at a rate of 4.6 percent over the same period.

MagnaChip offers a 0.18 micron ultra-low power technology that enables System-on-a-Chip (SoC) applications with low active and low stand-by power consumption. This new process features very low start-up voltage and enables DC-DC Boost Converters to be suitable for IoT applications. Another important technology feature is operational efficiency. This process allows for low electrical current draw, which is suitable for IoT devices such as solar cells, thermoelectric generators, vibration energy harvesters and electromagnetic harvesters.

Based on its already developed 0.18 micron ultra-low power technology, MagnaChip also plans to provide a diversified portfolio within the ultra-low power sector. This includes 0.13 micron ultra-low power EEPROM, Bipolar-CMOS-DMOS (BCD) and mixed-signal technologies. Ultra-low power technology is a key element for conserving energy usage within IoT devices. IoT applications demand an always on, low-power energy source and long battery life which are requirements that MagnaChip’s ultra-low power technology enables.

MagnaChip also offers 0.18 micron and plans to offer 0.13 micron Silicon on Insulator (SOI) RF-CMOS technologies, which is suitable for use in antenna switching, tuner and Power Amplifier (PA) applications. Switches and tuners are core components of wireless Front-End-Modules (FEMs) for cellular and Wi-Fi connectivity in IoT devices. MagnaChip’s CMOS based FEMs reduce manufacturing cost and time to market while providing competitive performance for multiband and multimode smartphones, tablets and other IoT devices.

Furthermore, MagnaChip’s 0.13 and 0.18 micron BCD technologies support high-voltage (up to 100V) and high-efficiency power ICs such as voltage regulators and converters, Power-over-Ethernet and smart LED Lighting solutions, which are essential power elements in IoT applications. With the combination of power devices with lower Specific On-Resistance (Rsp, defined as drain-source resistance times device area, Rds*A), improved isolation and higher reliability, MagnaChip’s 0.13 and 0.18 micron BCD processes will help our foundry customers to design IoT products with smaller and more power efficient characteristics.

“We believe there is tremendous growth opportunity in the IoT market and our participation is part of our overall strategy to broaden our product portfolio in new markets,” said YJ Kim, MagnaChip’s interim Chief Executive Officer. “MagnaChip’s IoT task force and business consortium with key business partners will reinforce our position as a key manufacturing service provider in the expanding IoT market.”

Applied Materials today announced the Applied Centura Tetra Z Photomask Etch system for etching next-generation optical lithographic photomasks needed by the industry to continue multiple patterning scaling to the 10nm node and beyond. The new tool extends the capabilities of Applied’s Tetra platform, delivering angstrom-level photomask accuracy for critical dimension (CD) parameters required to meet stringent patterning specifications for future logic and memory devices.

“Our Tetra Z system represents the state of the art in photomask etch technology, employing advances in precision materials engineering and plasma reaction kinetics to extend the use of 193nm lithography,” said Rao Yalamanchili, general manager of Applied’s Mask Etch product division. “Using the 193nm wavelength to produce 10nm or 7nm patterns requires a range of optimization techniques, including immersion and multiple patterning, which rely heavily on photomasks. Etch technology is key for photomask fabrication; the Tetra Z system is unique in delivering the accuracy required to etch next-generation optical photomasks for patterning advanced node designs.”

Applied developed the Tetra Z tool for advanced chrome, molybdenum silicon oxynitride (MoSi), hard mask and quartz (fused silica) etch applications used to fabricate advanced binary and phase-shift masks (PSMs). Offering continuous technical innovations and unprecedented CD performance, the system extends immersion lithography for quadruple patterning and cutting-edge resolution enhancement techniques. Vital capabilities ensuring pattern transfer fidelity include uniform, linear precision etching across all feature sizes and pattern densities with virtually zero defectivity.

Excellent CD performance combined with high etch selectivity enable the use of thinner resist films for achieving smaller photomask CD patterns on critical device layers. Controllable CD bias capability expands the system’s flexibility to meet customer specific requirements. Unique quartz etch depth control ensures precision phase angle and aids integrated circuit scaling by providing customers the capability to use alternating aperture PSMs and chromeless phase lithography. These key advances derive from a variety of system improvements in chamber design, plasma stability, ion and radical control, flow and pressure control, and real-time process monitoring and control.

Applied’s Tetra systems have been selected by a majority of mask makers worldwide to etch high-end photomasks over the past decade.

Applied Materials, Inc. is a developer of precision materials engineering solutions for the semiconductor, flat panel display and solar photovoltaic industries.

centura tetra z

Duke University researchers are working to advance the tools and methodologies used to test 3D integrated circuits (ICs), which promise to help ensure the ongoing development of higher performance, lower power semiconductor chips.

Sponsored by Semiconductor Research Corporation (SRC), the Duke research focuses on testing of 3D integration since testing remains an obstacle that hinders mainstream adoption and mass manufacturing of 3D technology.

“Even though manufacturing processes for 3D integration are nearly mature, a barrier to technology adoption is our insufficient understanding of 3D testing issues and the need for design-for-testability (DFT) solutions,” said Krishnendu Chakrabarty, professor of Electrical and Computer Engineering at Duke. “Test challenges for 3D ICs must be addressed before high-volume production can be practical. Breakthroughs in  test technology will allow higher levels of silicon integration, fewer defect escapes, and commercial exploitation.”

The Duke research has introduced probing solutions that may enable pre-bond and post-bond testing of Through Silicon Vias (TSVs) and logic dies used in manufacturing semiconductor components. The Duke team has also introduced design-for-test (DFT) innovations for 3D stacked chip technologies.

Specifically, it is paramount to stack “known good dies” to ensure a high manfufacturing yield with stacked technology. However, due to the small feature sizes of TSVs and micro-bumps, it is extremely difficulty to probe wafers at a pre-bond stage. The Duke team has presented an innovative solution to this problem by probing multiple micro-bumps at the same time, thereby shorting TSVs and forming a TSV network. Aggregated measurements from TSV networks can then be used to detect defects in TSVs as well as in the die logic.

Furthermore, by developing the DFT structures that must be included on the die and the measurement infrastructure needed on the probe cards, the research demonstrates that the proposed approach is robust to process variations as well variations in contact resistance to the potentially non-uniform nature of probe contacts.

Next, in the area of post-bond testing, the Duke team developed a test-architecture optimization and test scheduling solution that minimizes test time by considering various stages of 3D assembly. The research included formal models based on integer linear programming as well as fast heuristic solutions. An especially innovative aspect of this research is its solution for recovering the delay overhead introduced by the DFT that is added for 3D stack testing.

“We have shown that retiming can be used to redistribute the slack on critical paths, whereby the delay overhead due to 3D DFT can be reduced to zero. This is a remarkable research breakthrough, which shows that there is something called a ‘free lunch’ after all,” said Brandon Noia, a Ph.D. student who was part of the Duke team and a recipient of the SRC Ph.D. Fellowship. Now graduated and part of SRC member company, AMD, Noia also received the European Design and Automation Association 2014 Outstanding Dissertation Award for this research.

The Duke research has already led to three U.S. patents being granted in 2014, and multiple semiconductor and electronic design automation (EDA) companies are collaborating with the Duke team on incorporating the research into their test processes—with at least one company prepared to have measurement data on chips available this fall.

“Among all EDA challenges for 3D designs, tools and methodologies for 3D stacked IC testing are critical, and this research from Duke goes a long way toward removing these obstacles,” said William Joyner, SRC director of Computer-Aided Design and Test.

A team of researchers from the University of Cambridge have unravelled one of the mysteries of electromagnetism, which could enable the design of antennas small enough to be integrated into an electronic chip. These ultra-small antennas – the so-called ‘last frontier’ of semiconductor design – would be a massive leap forward for wireless communications.

In new results published in the journal Physical Review Letters, the researchers have proposed that electromagnetic waves are generated not only from the acceleration of electrons, but also from a phenomenon known as symmetry breaking. In addition to the implications for wireless communications, the discovery could help identify the points where theories of classical electromagnetism and quantum mechanics overlap.

The phenomenon of radiation due to electron acceleration, first identified more than a century ago, has no counterpart in quantum mechanics, where electrons are assumed to jump from higher to lower energy states. These new observations of radiation resulting from broken symmetry of the electric field may provide some link between the two fields.

The purpose of any antenna, whether in a communications tower or a mobile phone, is to launch energy into free space in the form of electromagnetic or radio waves, and to collect energy from free space to feed into the device. One of the biggest problems in modern electronics, however, is that antennas are still quite big and incompatible with electronic circuits – which are ultra-small and getting smaller all the time.

“Antennas, or aerials, are one of the limiting factors when trying to make smaller and smaller systems, since below a certain size, the losses become too great,” said Professor Gehan Amaratunga of Cambridge’s Department of Engineering, who led the research. “An aerial’s size is determined by the wavelength associated with the transmission frequency of the application, and in most cases it’s a matter of finding a compromise between aerial size and the characteristics required for that application.”

Another challenge with aerials is that certain physical variables associated with radiation of energy are not well understood. For example, there is still no well-defined mathematical model related to the operation of a practical aerial. Most of what we know about electromagnetic radiation comes from theories first proposed by James Clerk Maxwell in the 19th century, which state that electromagnetic radiation is generated by accelerating electrons.

However, this theory becomes problematic when dealing with radio wave emission from a dielectric solid, a material which normally acts as an insulator, meaning that electrons are not free to move around. Despite this, dielectric resonators are already used as antennas in mobile phones, for example.

“In dielectric aerials, the medium has high permittivity, meaning that the velocity of the radio wave decreases as it enters the medium,” said Dr Dhiraj Sinha, the paper’s lead author. “What hasn’t been known is how the dielectric medium results in emission of electromagnetic waves. This mystery has puzzled scientists and engineers for more than 60 years.”

Working with researchers from the National Physical Laboratory and Cambridge-based dielectric antenna company Antenova Ltd, the Cambridge team used thin films of piezoelectric materials, a type of insulator which is deformed or vibrated when voltage is applied. They found that at a certain frequency, these materials become not only efficient resonators, but efficient radiators as well, meaning that they can be used as aerials.

The researchers determined that the reason for this phenomenon is due to symmetry breaking of the electric field associated with the electron acceleration. In physics, symmetry is an indication of a constant feature of a particular aspect in a given system. When electronic charges are not in motion, there is symmetry of the electric field.

Symmetry breaking can also apply in cases such as a pair of parallel wires in which electrons can be accelerated by applying an oscillating electric field. “In aerials, the symmetry of the electric field is broken ‘explicitly’ which leads to a pattern of electric field lines radiating out from a transmitter, such as a two wire system in which the parallel geometry is ‘broken’,” said Sinha.

The researchers found that by subjecting the piezoelectric thin films to an asymmetric excitation, the symmetry of the system is similarly broken, resulting in a corresponding symmetry breaking of the electric field, and the generation of electromagnetic radiation.

The electromagnetic radiation emitted from dielectric materials is due to accelerating electrons on the metallic electrodes attached to them, as Maxwell predicted, coupled with explicit symmetry breaking of the electric field.

“If you want to use these materials to transmit energy, you have to break the symmetry as well as have accelerating electrons – this is the missing piece of the puzzle of electromagnetic theory,” said Amaratunga. “I’m not suggesting we’ve come up with some grand unified theory, but these results will aid understanding of how electromagnetism and quantum mechanics cross over and join up. It opens up a whole set of possibilities to explore.”

The future applications for this discovery are important, not just for the mobile technology we use every day, but will also aid in the development and implementation of the Internet of Things: ubiquitous computing where almost everything in our homes and offices, from toasters to thermostats, is connected to the internet. For these applications, billions of devices are required, and the ability to fit an ultra-small aerial on an electronic chip would be a massive leap forward.

Piezoelectric materials can be made in thin film forms using materials such as lithium niobate, gallium nitride and gallium arsenide. Gallium arsenide-based amplifiers and filters are already available on the market and this new discovery opens up new ways of integrating antennas on a chip along with other components.

“It’s actually a very simple thing, when you boil it down,” said Sinha. “We’ve achieved a real application breakthrough, having gained an understanding of how these devices work.”

Researchers at Chalmers University of Technology have discovered that large area graphene is able to preserve electron spin over an extended period, and communicate it over greater distances than had previously been known. This has opened the door for the development of spintronics, with an aim to manufacturing faster and more energy-efficient memory and processors in computers.

“We believe that these results will attract a lot of attention in the research community and put graphene on the map for applications in spintronic components,” says Saroj Dash, who leads the research group at Chalmers University of Technology.

Spintronics is based on the quantum state of the electrons, and the technology is already being used in advanced hard drives for data storage and magnetic random accesses memory. But here the spin-based information only needs to move a few nanometers, or millionths of a millimetre. Which is lucky, because spin is a property in electrons that in most materials is extremely short-lived and fragile.

However, there are major advantages in exploiting spin as an information carrier, instead of, or in addition to electric charges. Spintronics could make processors significantly faster and less energy consuming than they are today.

Graphene is a promising candidate for extending the use of spintronics in the electronics industry. The thin carbon film is not only an excellent electrical conductor, but also theoretically has the rare ability to maintain the electrons with the spin intact.

“In future spin-based components, it is expected that the electrons must be able to travel several tens of micrometers with their spins kept aligned. Metals, such as aluminium or copper, do not have the capacity to handle this. Graphene appears to be the only possible material at the moment,” says Saroj Dash.

Today, graphene is produced commercially by a few companies using a number of different methods, all of which are in an early phase of development.

Put simply, you could say that high-quality graphene can only be obtained in very small pieces, while larger graphene is produced in a way that the quality is either too low or has other drawbacks from the perspective of the electronics industry.

But that general assumption is now being seriously questioned by the findings presented by the research group at Chalmers. They have conducted their experiments using CVD graphene, which is produced through chemical vapour deposition. The method gives the graphene a lot of wrinkles, roughness and other defects.

But it also has advantages: There are good prospects for the production of large area graphene on an industrial scale. The CVD graphene can also be easily removed from the copper foil on which it grows and is lifted onto a silicon wafer, which is the semiconductor industry’s standard material.

Although the quality of the material is far from perfect, the research group can now show parameters of spin that are up to six times higher than those previously reported for CVD graphene on a similar substrate.

“Our measurements show that the spin signal is preserved in graphene channels that are up to 16 micrometers long. The duration over which the spins stay aligned has been measured to be over a nanosecond,” says Chalmers researcher Venkata Kamalakar who is the article’s first author.

“This is promising because it suggests that the spin parameters can be further improved as we develop the method of manufacturing.

That researchers are focusing on how far the spin current can be communicated should not be thought of as just being about sending information in a new material or replacing metals or semiconductors with graphene. The goal instead is a completely new way of performing logical operations and storing information. A concept that, if successful, would take digital technology a step beyond the current dependence on semiconductors.

“Graphene is a good conductor and has no band gaps. But in spintronics there is no need for band gaps to switch between on and off, one and zero. This is controlled instead by the electron’s up or down spin orientations,” Saroj Dash explains.

A short-term goal now is to construct a logical component that, not unlike a transistor, is made up of graphene and magnetic materials.

Whether spintronics can eventually fully replace semiconductor technology is an open question, a lot of research remains. But graphene, with its excellent spin conduction abilities, is highly likely to feature in this context.

Facts/This is spin:

Spin is a quantum mechanical property of elementary particles, which among other things gives rise to the phenomenon of magnetism. The spin can be directed either up or down. For the electrons in a normal electric current, the spin is randomly distributed, and the stream carries no spin signal. But with the help of magnets, electrons that are fed into a conductor can be polarised, which means they all have their spin directed up or down. You could liken the electrons to a series of small compass needles, all pointing towards north or south. The challenge is to maintain this state long enough and over sufficiently long distances.

Facts/Why spin works in graphene:

The spin of electrons can easily be disturbed by environmental factors. Atoms and their crystal structures in the conductive material have an electric field, which is perceived as a magnetic field by the electrons rushing by. But as carbon is such a light atom with only six protons arranged in a symmetrical hexagonal structure, this magnetic interference will be very limited.

The internal spin in an atomic nucleus is also a potential source of interference. But the net spin from the nucleus is negligible, as the majority of the carbon atoms are of the C12 isotope, with as many neutrons as protons.

Facts/Three ways of producing graphene:

The Nobel Laureates Geim and Novoselov manufactured graphene from graphite using ordinary household tape. Similar methods are used today to produce high quality graphene. But the pieces are small. The Graphensic company, created by researchers at Swedish Linköping University, manufactures large area graphene that is “cultivated” from a substrate of silicon carbide.

At Chalmers University of Technology, large area graphene is produced using the chemical vapour deposition method (CVD). For the study in Nature Communications, the researchers have used CVD graphene purchased from the company Graphenea in Spain.