Tag Archives: letter-wafer-tech

Rudolph Technologies, Inc. (NYSE: RTEC) today announced the availability of its NovusEdge™ system for edge, notch and backside inspection of unpatterned wafers. The company plans to ship multiple systems totaling more than $3M by year end to fill existing orders from two customers. The new system is the result of a multi-year collaboration with bare wafer manufacturing partners that require one inspection tool capable of detecting defects near the wafer’s edge, bevel, back-side and notch. The NovusEdge system meets the stringent new requirements for defect control at the edge and backside of wafers being manufactured for 10nm process nodes. The system provides up to 50 percent faster throughput and two orders of magnitude better edge sensitivity than incumbent technology.

“Gartner estimated the unpatterned wafer inspection market at over $400M in 2017,” Tim Kryman, senior director of product marketing explained. “The bulk of this is focused on finding front surface defects as small as 10nm. However, our development partners also required tighter defect control at the wafer bevel and backside, to ensure the stringent quality standards required for these process nodes.  We estimate the NovusEdge system’s addressable market at 15 – 20 percent of the overall unpatterned market.”

The NovusEdge system uses multiple cameras and advanced imaging technologies to build a high-resolution, composite image of the entire wafer bevel then applies sophisticated analytical routines to identify and classify defects as small as the sub-micron level. On the backside it utilizes high-speed laser-scanning to detect particles, scratches, area defects and haze.

In the quest for abundant, renewable alternatives to fossil fuels, scientists have sought to harvest the sun’s energy through “water splitting,” an artificial photosynthesis technique that uses sunlight to generate hydrogen fuel from water. But water-splitting devices have yet to live up to their potential because there still isn’t a design for materials with the right mix of optical, electronic, and chemical properties needed for them to work efficiently.

The HPEV cell’s extra back outlet allows the current to be split into two, so that one part of the current contributes to solar fuels generation, and the rest can be extracted as electrical power. Credit: Credit: Berkeley Lab, JCAP

Now researchers at the U.S. Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) and the Joint Center for Artificial Photosynthesis (JCAP), a DOE Energy Innovation Hub, have come up with a new recipe for renewable fuels that could bypass the limitations in current materials: an artificial photosynthesis device called a “hybrid photoelectrochemical and voltaic (HPEV) cell” that turns sunlight and water into not just one, but two types of energy – hydrogen fuel and electricity. The paper describing this work was published on Oct. 29 in Nature Materials.

Finding a way out for electrons

Most water-splitting devices are made of a stack of light-absorbing materials. Depending on its makeup, each layer absorbs different parts or “wavelengths” of the solar spectrum, ranging from less-energetic wavelengths of infrared light to more-energetic wavelengths of visible or ultraviolet light.

When each layer absorbs light it builds an electrical voltage. These individual voltages combine into one voltage large enough to split water into oxygen and hydrogen fuel. But according to Gideon Segev, a postdoctoral researcher at JCAP in Berkeley Lab’s Chemical Sciences Division and the study’s lead author, the problem with this configuration is that even though silicon solar cells can generate electricity very close to their limit, their high-performance potential is compromised when they are part of a water-splitting device.

The current passing through the device is limited by other materials in the stack that don’t perform as well as silicon, and as a result, the system produces much less current than it could – and the less current it generates, the less solar fuel it can produce.

“It’s like always running a car in first gear,” said Segev. “This is energy that you could harvest, but because silicon isn’t acting at its maximum power point, most of the excited electrons in the silicon have nowhere to go, so they lose their energy before they are utilized to do useful work.”

Getting out of first gear

So Segev and his co-authors – Jeffrey W. Beeman, a JCAP researcher in Berkeley Lab’s Chemical Sciences Division, and former Berkeley Lab and JCAP researchers Jeffery Greenblatt, who now heads the Bay Area-based technology consultancy Emerging Futures LLC, and Ian Sharp, now a professor of experimental semiconductor physics at the Technical University of Munich in Germany – proposed a surprisingly simple solution to a complex problem.

“We thought, ‘What if we just let the electrons out?'” said Segev.

In water-splitting devices, the front surface is usually dedicated to solar fuels production, and the back surface serves as an electrical outlet. To work around the conventional system’s limitations, they added an additional electrical contact to the silicon component’s back surface, resulting in an HPEV device with two contacts in the back instead of just one. The extra back outlet would allow the current to be split into two, so that one part of the current contributes to solar fuels generation, and the rest can be extracted as electrical power.

When what you see is what you get

After running a simulation to predict whether the HPEC would function as designed, they made a prototype to test their theory. “And to our surprise, it worked!” Segev said. “In science, you’re never really sure if everything’s going to work even if your computer simulations say they will. But that’s also what makes it fun. It was great to see our experiments validate our simulations’ predictions.”

According to their calculations, a conventional solar hydrogen generator based on a combination of silicon and bismuth vanadate, a material that is widely studied for solar water splitting, would generate hydrogen at a solar to hydrogen efficiency of 6.8 percent. In other words, out of all of the incident solar energy striking the surface of a cell, 6.8 percent will be stored in the form of hydrogen fuel, and all the rest is lost.

In contrast, the HPEV cells harvest leftover electrons that do not contribute to fuel generation. These residual electrons are instead used to generate electrical power, resulting in a dramatic increase in the overall solar energy conversion efficiency, said Segev. For example, according to the same calculations, the same 6.8 percent of the solar energy can be stored as hydrogen fuel in an HPEV cell made of bismuth vanadate and silicon, and another 13.4 percent of the solar energy can be converted to electricity. This enables a combined efficiency of 20.2 percent, three times better than conventional solar hydrogen cells.

The researchers plan to continue their collaboration so they can look into using the HPEV concept for other applications such as reducing carbon dioxide emissions. “This was truly a group effort where people with a lot of experience were able to contribute,” added Segev. “After a year and a half of working together on a pretty tedious process, it was great to see our experiments finally come together.”

Solar cells are a cost-effective, alternate source of energy. A subtype of these, organic solar cells make use of organic polymers inside the cell. Using these polymers makes the cells light-weight and increases their flexibility. Organic solar cells are produced by two different chemical methods: dry processing and wet processing, with the latter being a faster method. There are several parameters used to assess the efficiency of solar cells with absorption of light and transportation of charge being widely used.

A prevailing problem with the structure of organic cells is that molecules in the active organic layer responsible for light absorption and charge transport tend to face both towards the edges of cells, as well as towards the light absorbing substrate. Maximizing the number of molecules facing the substrate, however, is the key to maximising absorption and conductivity of the cell. Scientists have modified the dry processing method to achieve such an orientation, but it has not been possible with the wet method. The research team led by Tetsuya Taima at Kanazawa University, is the first to successfully do so.

The premise of their method is the introduction of a copper iodide (CuI) layer between the active molecules and the substrate. In their study, the researchers used a film of active molecules called DRCN5T and coated them onto either CuI/PEDOT: PSS (30 nm)/indium tin oxide (ITO) mixed substrates, or substrates without the CuI layer. The ratio of substrate facing to edge facing DRCN5T molecules was then compared between both. Subsequent high-resolution imaging revealed that the CuI containing cells had active molecules with a ten times higher substrate facing orientation, along with enhanced light absorption. The researchers attributed this altered orientation of the molecules to strong chemical interactions between the DRCN5T and CuI atoms. To further confirm this, DRCN5T molecules with bulky side chains that do not interact with CuI were used, and a higher substrate facing ratio was not seen.

This is the first study that effectively demonstrates a method of producing such efficient organic solar cells using the wet processing method. Besides saving time, the wet method also results in larger film areas. “This technique is expected to greatly contribute to the development of organic thin film solar cells fabricated by wet processing in the future”, conclude the authors. Their approach paves the way for producing high-performance solar cells faster.

ClassOne Technology, a supplier of new wet process tools to the 200mm and below semiconductor manufacturing industry, today announced the sale of its flagship Solstice® S8 wet process tool to the Ferdinand-Braun-Institute (FBH) in Berlin, Germany. As a leading research institute in the fabrication of III-V compound semiconductors, FBH specializes in prototyping leading-edge microwave and optoelectronic devices for a diverse range of industries, including communications, energy, health, and mobility.

“Solstice is a perfect fit for the III-V compound semiconductor processes that FBH specializes in,” explains Olaf Krüger, Head of FBH’s Process Technology Department. “The exceptional flexibility of the Solstice platform will allow FBH to efficiently automate a number of distinct processes on a single tool. We expect to retain the fine-grained control needed in our research environment with the added production benefits of complete cassette-to-cassette automation.“

FBH is the latest example of a growing trend in the compound semiconductor industry—the need for integrated plating-related processes as part of a comprehensive plating solution. ClassOne’s eight-chamber Solstice S8 will provide FBH with sophisticated electroplating and wet processing capabilities for a range of processes. In particular, gold plating will be performed by a pair of ClassOne’s class-leading GoldPro™ chambers, and a new high-pressure spray solvent chamber will process highly-efficient Metal Lift-off. ClassOne has dubbed the wide range of plating-related wet processing capabilities on the Solstice platform as Plating-PlusTM.

“The configuration flexibility of Plating-PlusTM and the exceptional quality of our plating chambers are why ClassOne has become the supplier of choice for the compound semiconductor industry,” says Roland Seitz, Director of ClassOne’s European Operations. “Solstice is perfectly suited to the complex processing requirements of compound semiconductors. By placing several related processes on a single tool, FBH will enjoy processing efficiencies and device quality that simply cannot be achieved by any other supplier.”

Scientists from the NUST MISIS Laboratory of Inorganic Nanomaterials together with their international colleagues have proved it possible to change the structural and conductive properties of nanotubes by stretching them. This can potentially expand nanotubes’ application into electronics and high-precision sensors such as microprocessors and high-precision detectors. The research article has been published in Ultramicroscopy.

Carbon nanotubes can be represented as a sheet of graphene rolled in a special way. There are different ways of «folding» it, which leads to the graphene edges interconnecting at different angles, forming either armchair, zigzag or chiral nanotubes (Pic.1).

Nanotubes are considered to be promising materials for use in electronics and sensors because they have high electrical conductivity, which would work well in things like microprocessors and high-precision detectors. However, when producing carbon nanotubes it is hard to control their conductivity. Nanotubes with metallic and semiconducting properties can grow into a single array while microprocessor-based electronics require semiconducting nanotubes that have the same characteristics.

Scientists from the NUST MISIS Laboratory of Inorganic Nanomaterials jointly with a research team from Japan, China and Australia, led by Professor Dmitri Golberg, have proposed a method that allows for the modification of the structure of ready-made nanotubes and thus changes their conductive properties.

«The basis of the nanotube – a folded layer of graphene – is a grid of regular hexagons, the vertices of which are carbon atoms. If one of the carbon bonds in the nanotube is rotated by 90° degrees, a pentagon and a heptagon are formed at this [junction] instead of a hexagon, and a so-called Stone-Wales defect is obtained in this case. Such a defect can occur in the structure under certain conditions. Back in the late 90s, it was predicted that the migration of this defect along the walls of a highly heated nanotube with the application of mechanical stress could lead to a change in its structure – a sequential change in the chirality of the nanotube, which leads to a change in its electronic properties. No experimental evidence for this hypothesis has previously been obtained, but our research paper has presented convincing proof of it», said Associate Professor Pavel Sorokin, Doctor of Physical & Mathematical Sciences and head of the «Theoretical Materials Science of Nanostructures» infrastructure project at the NUST MISIS Laboratory of Inorganic Nanomaterials.

Scientists from the NUST MISIS Laboratory of Inorganic Nanomaterials have conducted simulations of the experiment at the atomic level. At first, the nanotubes were lengthened to form the first structural defect consisting of two pentagons and two heptagons (a Stone-Wales defect, pic.2a), where the prolonged lengthening of the tube began to «spread» to the sides, rearranging other carbon bonds (pic.2b). It was at this stage that the structure of the nanotubes changed. With further stretching, more and more Stone-Wales defects began to form, eventually leading to a change in the nanotubes’ conductivity (Pic. 2).

«We were responsible for the theoretical modeling of the process on a supercomputer in the NUST MISIS Laboratory for Modeling and Development of New Materials for the experimental part of the work. We are glad that the simulation results [support] the experimental data», added Dmitry Kvashnin, co-author of the research work, Candidate of Physical & Mathematical Sciences and a researcher at the NUST MISIS Laboratory of Inorganic Nanomaterials.

The proposed technology is capable of helping in the transformation of «metallic» nanotubes’ structure for their further application in semiconductor electronics and sensors such as microprocessors and ultrasensitive detectors.

Samsung Electronics Co., Ltd. today announced several groundbreaking additions to its comprehensive semiconductor ecosystem that encompass next-generation technologies in foundry as well as NAND flash, SSD (solid state drive) and DRAM. Together, these developments mark a giant step forward for Samsung’s semiconductor business.

Unveiled at its annual Samsung Tech Day include:

  • 7nm EUV process node from Samsung’s Foundry Business, providing significant strides forward in power, performance and area.
  • SmartSSD, a field programmable gate array (FPGA) SSD, that will offer accelerated data processing and the ability to bypass server CPU limits.
  • QLC-SSD for enterprise and datacenters that offer 33-percent more storage per cell than TLC-SSD, consolidating of storage footprints and improving total cost of ownership (TCO).
  • 256-gigabyte (GB) 3DS (3-dimensional stacking) RDIMM (registered dual in-line memory module), based on 10nm-class 16-gigabit (Gb) DDR4 DRAM that will double current maximum capacity to deliver higher performance and lower power consumption.

“Samsung’s technology leadership and product breadth are unparalleled,” said JS Choi, President, Samsung Semiconductor, Inc. “Bringing 7nm EUV into production is an incredible achievement. Also, the announcements of SmartSSD and 256GB 3DS RDIMM represent performance and capacity breakthroughs that will continue to push compute boundaries. Together, these additions to Samsung’s comprehensive technology ecosystem will power the next generation of datacenters, high-performance computing (HPC), enterprise, artificial intelligence (AI) and emerging applications.”

Advanced Foundry Technology

Initial wafer production of Samsung’s 7nm LPP (Low Power Plus) EUV process node represents a major milestone in semiconductor fabrication. The 7LPP EUV process technology provides great advances, including a respective maximum of 40-percent area reduction, 50-percent dynamic power reduction and 20-percent performance increase over 10nm processes. The 7LPP process represents a clear demonstration of the foundry business’ technology roadmap evolution, providing Samsung’s customers a direct path forward to 3nm.

Powering Server-less Computing

Samsung enables the most advanced providers of server-less computing through products including the new SmartSSD, quad-level cell (QLC)-SSD, 256GB 3DS RDIMM as well as High Bandwidth Memory (HBM) 2 Aquabolt. By accelerating data processing, bypassing server CPU limits and reducing power demands, these products will enable datacenter operators to continue to scale at faster speeds while containing costs.

Samsung’s industry-leading flash memory products for future datacenters will also include Key Value (KV)-SSD and Z-SSD. KV-SSD eliminates block storage inefficiency, reducing latency and allowing datacenter performance to scale evenly when CPU architectures max out. The company’s next-generation Z-SSD will be the fastest flash memory ever introduced, with dual port high availability, ultra-low latency and a U.2 form factor, designed to meet the emerging needs of enterprise clients. Z-SSD will also feature a PCIe Gen 4 interface with a blazing-fast 12-gigabytes-per-second (GB/s) sequential read, which is 20 times faster than today’s SATA SSD drives.

Accelerating Application Learning

A range of revolutionary Samsung solutions will enable the development of upcoming machine learning and AI technologies. The Tech Day AI display highlighted astounding data transfer speeds of 16Gb GDDR6 (64GB/s), ultra-low latency of Z-SSD and industry-leading performance of Aquabolt, which is the highest of any DRAM-based memory solution currently in the market. Together, these solutions help Samsung’s enterprise and datacenter clients open new doors to application learning and create the next wave of AI advancements.

Streamlining Data Flow

Samsung’s new solutions will enable not just faster speeds and higher performance but also improved efficiency for its enterprise clients. Enterprise products on display at Tech Day included D1Y 8Gb DDR4 Server DRAM, which incorporates the most advanced DRAM process, resulting in lower power usage. Samsung’s 256GB 3DS RDIMM also helps to improve enterprise performance and enables memory-intensive servers capable up to 16-terabytes (TB).

Additionally, Samsung’s dual-port x4 PCIe Gen 4 32TB SSD offers 10GB/s performance. Samsung’s 1Tb QLC-SSD presents a cutting-edge storage option for enterprise clients with competitive efficiency when compared to hard disk drives (HDD), while KV-SSD allows server performance to scale even as CPU architectures max out, also providing a competitive TCO, write amplification factor (WAF) improvement and scalability.

Breaking Performance Barriers

With their leading-edge specs, Samsung’s QLC-SSD, Z-SSD and 8GB Aquabolt help high-performance computing clients blast through performance barriers and reach new heights. The 8GB Aquabolt provides the fastest data transmission speed and highest performance of any DRAM-based memory solution on the market today at 307GB/s per HBM cube. QLC-SSD and Z-SSD, both powerful on their own, are also offered in a tiered storage solution that results in a 53-percent increase in overall system performance.

Enabling Future Innovation

Emerging tech requires the most innovative and flexible components. Samsung’s SmartSSD will increase speed and efficiency, and lower operating costs by pushing intelligence to where data lives. Movement of data for processing has traditionally caused increased latency and energy consumption while reducing efficiency. Samsung’s new SmartSSDs will overcome these issues by incorporating an FPGA accelerator into the SSD unit. This allows for faster data processing through bypassing server CPU limits. As a result, SmartSSDs will have higher processing performance, improved time-to-insight, more virtual machines (VM), scalable performance, better de-duplication and compression, lower power usage and fewer CPUs per system.

Unparalleled Product Ecosystem

Samsung’s comprehensive product portfolio with state-of-the-art solutions set new standards for data processing speed, capacity, bandwidth and energy conservation. By leveraging such solutions, data centers, enterprise companies, hyper-scalers and emerging tech platforms are able to configure product solutions based on their requirements and develop exciting new tech offerings such as 5G, AI, enterprise and hyperscale data centers, automotive, networking and beyond.

Samsung will continue to push boundaries in tomorrow’s semiconductor technologies through innovations such as its sixth-generation V-NAND built on a single structure, or with ‘1-stack technology,’ and sub-10nm DRAM with EUV for super-high density and performance.

Experts across the industry, including Apple co-founder, Steve Wozniak, were invited at Samsung Tech Day to address the advancements and challenges in today’s semiconductor market, and offer insights for the future of semiconductors. More than 400 customers, partners and industry influencers attended the event.

Graphene Flagship researchers have shown in a paper published in Science Advanceshow heterostructures built from graphene and topological insulators have strong, proximity induced spin-orbit coupling which can form the basis of novel information processing technologies.

Scanning Electron Microscope micrograph of a fabricated device showing the graphene topological insulator heterostructure channel. Credit: Dmitrii Khokhriakov, Chalmers University of Technology

Spin-orbit coupling is at the heart of spintronics. Graphene’s spin-orbit coupling and high electron mobility make it appealing for long spin coherence length at room temperature. Graphene Flagship researchers from Chalmers University of Technology (Sweden), Catalan Institute of Nanoscience and Nanotechnology – ICN2 (Spain), Universitat Autònoma de Barcelona (Spain) and ICREA Institució Catalana de Recerca i Estudis Avançats (Spain) showed a strong tunability and suppression of the spin signal and spin lifetime in heterostructures formed by graphene and topological insulators. This can lead to new graphene spintronic applications, ranging from novel circuits to new non-volatile memories and information processing technologies.

“The advantage of using heterostructures built from two Dirac materials is that, graphene in proximity with topological insulators still supports spin transport, and concurrently acquires a strong spin-orbit coupling,” said Associate Professor Saroj Prasad Dash, from Chalmers University of Technology.

“We do not just want to transport spin we want to manipulate it,” said Professor Stephan Roche from ICN2 and deputy leader of the Graphene Flagship’s spintronics Work-Package, “the use of topological insulators is a new dimension for spintronics, they have a surface state similar to graphene and can combine to create new hybrid states and new spin features. By combining graphene in this way we can use the tuneable density of states to switch on/off – to conduct or not conduct spin. This opens an active spin device playground.”

The Graphene Flagship, from its very beginning, saw the potential of spintronics devices made from graphene and related materials. This paper shows how combining graphene with other materials to make heterostructures opens new possibilities and potential applications.

“This paper combines experiment and theory and this collaboration is one of the strengths of the Spintronics Work-Package within the Graphene Flagship,” said Roche.

“Topological insulators belong to a class of material that generate strong spin currents, of direct relevance for spintronic applications such as spin-orbit torque memories. As reported by this article, the further combination of topological insulators with two-dimensional materials like graphene is ideal for enabling the propagation of spin information with extremely low power over long distances, as well as for exploiting complementary functionalities, key to further design and fabricate spin-logic architectures,” said Kevin Garello from IMEC, Belgium who is leader of the Graphene Flagships Spintronics Work-Package.

Professor Andrea C. Ferrari, Science and Technology Officer of the Graphene Flagship, and Chair of its Management Panel added “This paper brings us closer to building useful spintronic devices. The innovation and technology roadmap of the graphene Flagship recognises the potential of graphene and related materials in this area. This work yet again places the Flagship at the forefront of this field, initiated with pioneering contributions of European researchers.”

Organic semiconductor materials have the potential to be used in innovative applications such as transparent and flexible devices, and their low cost makes their potential use particularly attractive. The properties of organic semiconductor materials can be tuned by controlling their structure at the molecular level through parts of the structure known as electron-accepting units. A group of researchers centered at Osaka University has specifically tailored an electron-accepting unit that was then successfully used in an organic semiconductor applied in solar cell device that showed high photovoltaic performance. Their findings were published in NPG Asia Materials.

Chemical structures and photovoltaic characteristics. Credit: Osaka University

“Electron-accepting units are important elements of organic semiconductors,” study corresponding author Yoshio Aso says. “Through the controlled addition of electronegative fluorine groups to a widely used electron-accepting material, we were able to show precise control of the energy levels within the resulting semiconductor. This ability to tune the band gap translates to selectivity over the injection and transport of holes and/or electrons within the material, which is important in potential applications.”

The fluorinated electron-acceptor unit was used to prepare a thin film solar cell that was compared with a cell based on a non-fluorinated analogue. The researchers found that the fluorinated material showed enhanced power conversion efficiency, up to 3.12%. The morphology of the fluorinated film was also found to be good, which supported the efficient charge generation and transport that is necessary for successful application.

“The more we are able to fine tune organic semiconductor behavior on the molecular level, the more possibilities there will be for demonstrating their macroscopic applications,” co-author Yutaka Ie says. “It is our hope that the band gap control and high photovoltaic performance we have demonstrated will lead to our material being applied in devices such as organic light-emitted diodes, field-effect transistors, and thin film solar cells.”

The straightforward demonstration of the link between high electronegativity, greater electron-accepting tendency, and enhanced semiconductor performance, highlights both the potential and versatility of organic semiconductors. Further elegant solutions such as this one could substantially broaden the range of ƒÎ-conjugated materials, and reinforce the case for organic electronics.

A new approach in Fault Detection and Classification (FDC) allows engineers to uncover issues more thoroughly and accurately by taking advantage of full sensor traces.

By Tom Ho and Stewart Chalmers, BISTel, Santa Clara, CA

Traditional FDC systems collect data from production equipment, summarize it, and compare it to control limits that were previously set up by engineers. Software alarms are triggered when any of the summarized data fall outside of the control limits. While this method has been effective and widely deployed, it does create a few challenges for the engineers:

  • The use of summary data means that (1) subtle changes in the process may not be noticed and (2) the unmonitored section of the process will be overlooked by a typical FDC system. These subtle changes or the missed anomalies in unmonitored section may result in critical problems.
  • Modeling control limits for fault detection is a manual process, prone to human error and process drift. With hundreds of thousandssensors in a complex manufacturing process, the task of modeling control limits is extremely time consuming and requires a deep understanding of the particular manufacturing process on the part of the engineer. Non-optimized control limits result in misdetection: false alarms or missed alarms.
  • As equipment ages, processes change. Meticulously set control limit ranges must be adjusted, requiring engineers to constantly monitor equipment and sensor data to avoid false alarms or missed real alarm.

Full sensor trace detection

A new approach, Dynamic Fault Detection (DFD) was developed to address the shortcomings of traditional FDC systems and save both production time and engineer time. DFD takes advantage of the full trace from each and every sensor to detect any issues during a manufacturing process. By analyzing each trace in its entirety, and running them through intelligent software, the system is able to comprehensively identify potential issues and errors as they occur. As the Adaptive Intelligence behind Dynamic Fault Detection learns each unique production environment, it will be able to identify process anomalies in real time without the need for manual adjustment from engineers. Great savings can be realized by early detection, increased engineer productivity, and containment of malfunctions.

DFD’s strength is its ability to analyze full trace data. As shown in FIGURE 1, there are many subtle details on a trace, such as spikes, shifts, and ramp rate changes, which are typically ignored or go undetected by a traditional FDC systems, because they only examine a segment of the trace- summary data. By analyzing the full trace using DFD, these details can easily be identified to provide a more thorough analysis than ever before.

Figure 1

Dynamic referencing

Unlike traditional FDC deployments, DFD does not require control limit modeling. The novel solution adapts machine learning techniques to take advantage of neighboring traces as references, so control limits are dynamically defined in real time.  Not only does this substantially reduce set up and deployment time of a fault detection system, it also eliminates the need for an engineer to continuously maintain the model. Since the analysis is done in real time, the model evolves and adapts to any process shifts as new reference traces are added.

DFD has multiple reference configurations available for engineers to choose from to fine tune detection accuracy. For example, DFD can 1) use traces within a wafer lot as reference, 2) use traces from the last N wafers as reference, 3) use “golden” traces as reference, or 4) a combination of the above.

As more sensors are added to the Internet of Things network of a production plant, DFD can integrate their data into its decision-making process.

Optimized alarming

Thousands of process alarms inundate engineers each day, only a small percentage of which are valid. In today’s FDC systems, one of the main causes for false alarms is improperly configured Statistical Process Control (SPC) limits. Also, typical FDC may generate one alarm for each limit violation resulting in many alarms for each wafer process. DFD implementations require no control limits, greatly reducing the potential for false alarms.  In addition, DFD is designed to only issues one alarm per wafer, further streamlining the alarming system and providing better focus for the engineers.

Dynamic fault detection use cases

The following examples illustrate actual use cases to show the benefits of utilizing DFD for fault detection.

Use case #1– End Point Abnormal Etching

In this example, both the upper and lower control limits in SPC were not set at the optimum levels, preventing the traditional FDC system from detecting several abnormally etched wafers (FIGURE 2).  No SPC alarms were issued to notify the engineer.

Figure 2

On the other hand, DFD full trace comparison easily detects the abnormality by comparing to neighboring traces (FIGURE 3).  This was accomplished without having to set up any control limits.

Figure 3

Use case #2 – Resist Bake Plate Temperature

The SPC chart in Figure 4 clearly shows that the Resist bake plate temperature pattern changed significantly; however, since the temperature range during the process never exceeded the control limits, SPC did not issue any alarms.

Figure 4

When the same parameter was analyzed using DFD, the temperature profile abnormality was easily identified, and the software notified an engineer (FIGURE 5).

Figure 5

Use case #3 – Full Trace Coverage

Engineers select only a segment of sensor trace data to monitor because setting up SPC limits is so arduous. In this specific case, the SPC system was set up to monitor only the He_Flow parameter in recipe step 3 and step 4.  Since no unusual events occurred during those steps in the process, no SPC alarms were triggered.

However, in that same production run, a DFD alarm was issued for one of the wafers. Upon examination of the trace summary chart shown in FIGURE 6, it is clear that while the parameter behaved normally during recipe step 3 and step 4, there was a noticeable issue from one of the wafers during recipe step 1 and step 2.  The trace in red represents the offending trace versus the rest of the (normal) population in blue. DFD full trace analysis caught the abnormality.

Figure 6

Use case #4 – DFD Alarm Accuracy

When setting up SPC limits in a conventional FDC system, the method of calculation taken by an engineer can yield vastly different results. In this example, the engineer used multiple SPC approaches to monitor parameter Match_LoadCap in an etcher. When the control limits were set using Standard Deviation (FIGURE 7), a large number of false alarms were triggered.  On the other hand, zero alarms were triggered using the Meanapproach (FIGURE 8).

Figure 7

Figure 8

Using DFD full trace detection eliminates the discrepancy between calculation methods. In the above example, DFD was able to identify an issue with one of the wafers in recipe step 3 and trigger only one alarm.

Dynamic fault detection scope of use

DFD is designed to be used in production environments of many types, ranging from semiconductor manufacturing to automotive plants and everything in between. As long as the manufacturing equipment being monitored generates systematic and consistent trace patterns, such as gas flow, temperature, pressure, power etc., proper referencing can be established by the Adaptive Intelligence (AI) to identify abnormalities. Sensor traces from Process of Record (POR) runs may be used as starting references.

Conclusion

The DFD solution reduces risk in manufacturing by protecting against events that impact yield.  It also provides engineers with an innovative new tool that addresses several limitations of today’s traditional FDC systems.  As shown in TABLE 1, the solution greatly reduces the time required for deployment and maintenance, while providing a more thorough and accurate detection of issues.

 

TABLE 1
FDC

(Per Recipe/Tool Type)

 DFD

(Per Recipe/Tool Type)
FDC model creation 1 – 2 weeks < 1 day
FDC model validation and fine tuning 2 – 3 weeks < 1 week
Model Maintenance Ongoing Minimal
Typical Alarm Rate 100-500/chamber-day < 50/chamber-day
% Coverage of Number of Sensors 50-60% 100% as default
Trace Segment Coverage 20-40% 100%
Adaptive to Systematic Behavior Changes No Yes

 

 

TOM HO is President of BISTel America where he leads global product engineer and development efforts for BISTel.  [email protected].   STEWART CHALMERS is President & CEO of Hill + Kincaid, a technical marketing firm. [email protected]. 

When chemists from the Institute of Physical Chemistry of the Polish Academy of Sciences in Warsaw were starting work on yet another material designed for the efficient production of nanocrystalline zinc oxide, they didn’t expect any surprises. They were greatly astonished when the electrical properties of the changing material turned out to be extremely exotic.

The exotic transformations causes that one of the precursors of zinc oxide, initially an insulator, at approx. 300 degrees Celsius goes to a state with electrical properties typical of metals, and at ~400 degrees Celsius it becomes a semiconductor. Credit: IPC PAS

The single source precursor (SSP) approach is widely regarded as one of the most promising of the various strategies employed for the preparation of semiconductor nanocrystalline materials. However, one of the key obstacles hampering both the rational design of SSPs and their controlled transformation to the desired nanomaterials with highly controlled physicochemical properties is the scarcity of mechanistic insights during the transformation process. Scientists from the Institute of Physical Chemistry of the Polish Academy of Sciences (IPC PAS) and the Faculty of Chemistry of Warsaw University of Technology (WUT) have revealed that in the thermal decomposition process of a pre-organized zinc alkoxide precursor the nucleation and growth of the semiconducting zinc oxide (ZnO) phase is preceded by cascade transformations involving the formation of previously unreported intermediate radical zinc oxo-alkoxide clusters with gapless electronic states. Up to now, these types of clusters have not been considered either as intermediate structures on the path to the semiconductor ZnO phase or as a potential species accounting for the various defect states of ZnO nanocrystals.

“We discovered that one of the groups of ZnO precursors that have been studied for decades, zinc alkoxide compounds, undergo previously unobserved physicochemical transformations upon thermal decomposition. Originally, the starting compound is an insulator, when heated it rapidly transforms into a material with conductor-like properties, and a further increase in temperature equally rapidly leads to its conversion into a semiconductor,” says Dr. Kamil Soko?owski (IPC PAS).

The design and preparation of well-defined nanomaterials in a controlled manner remains a tremendous challenge and is acknowledged to be the biggest obstacle for the exploitation of many nanoscale phenomena. Professor Lewiski’s (IPC PAS, PW) group has for many years been engaged in the development of effective methods of producing nanocrystalline forms of zinc oxide, a semiconductor with wide applications in electronics, industrial catalysis, photovoltaics and photocatalysis. One of the studied approaches is based on the single source precursors. The precursor molecules contain all components of the target material in their structure and only temperature is required to trigger the chemical transformation.

“We dealt with a group of chemical compounds with the general formula RZnOR, as single source pre-designed ZnO precursors. A common feature of their structure is the presence of the cubic [Zn4O4] core with alternating zinc and oxygen atoms terminated by organic groups R. When the precursor is heated, the organic parts are degraded, and the inorganic cores self-assemble, forming the final form of the nanomaterial,” explains Dr. Soko?owski.

The tested precursor had the properties of an insulator, with an energy gap of about five electronvolts. When heated, it eventually transformed into a semiconductor with an energy gap of approximately 3 eV.

“An exceptional result of our research was the discovery that at a temperature close to 300 degrees Celsius the compound suddenly transforms into almost gap-less electronic state, showing electrical properties rather more typical of metals. When the temperature rises to approximately 400 degrees, the energy gap suddenly expands to a width characteristic of semiconductor materials. Ultimately, thanks to the combination of advanced synchrotron experiments with quantum-chemical calculations, we have established all the details of these unique transformations,” says Dr. Adam Kubas (IPC PAS), who carried out the quantum-chemical calculations.

The spectroscopic measurements were carried out using methods developed by Dr. Jakub Szlachetko (Institute of Nuclear Physics PAS, Cracow) and Dr. Jacinto Sa (IPC PAS and Uppsala University) at the Swiss Light Source synchrotron facility at the Paul Scherrer Institute in Villigen, Switzerland. The material was heated in a reaction chamber, and then its electron structure was sampled using an X-ray synchrotron beam. The set-up allowed for real-time monitoring of the transformations taking place.

This detailed in situ study of the decomposition process of the zinc alkoxide precursor, supported by computer simulations, revealed that any nucleation or growth of a semiconducting ZnO phase is preceded by cascade transformations involving the formation of previously unreported intermediate radical zinc oxo-alkoxide clusters with gapless electronic states.

“In this process homolytic cleavage of the R-Zn bond is responsible for the initial thermal decomposition process. Computer simulations revealed that the intermediate radical clusters tend to dimerise though an uncommon bimetallic Zn-Zn-bond formation. The following homolytic O-R bond cleavage then leads to sub-nano ZnO clusters which further self-organise to the ZnO nanocrystalline phase,” says Dr. Kubas.

Up to now, the radical zinc oxo clusters formed have not been considered either as intermediate structures on the way to the semiconductor ZnO phase or as potential species accounting for various defect states of ZnO nanocrystals. In a broader context, a deeper understanding of the origin and character of the defects is crucial for structure-property relationships in semiconducting materials.

The research, funded by the National Science Centre and the TEAM grant of the Foundation for Polish Science co-financed by the European Union, will contribute to the development of more precise methods of controlling the properties of nanocrystalline zinc oxide. So far, with greater or lesser success, these properties have been explained with the help of various types of material defects. For obvious reasons, however, the analyses have not taken into account the possibility of forming the specific radical zinc-oxo clusters discovered by the Warsaw-based scientists in the material.