Tag Archives: letter-wafer-tech

Physicists have, for the first time, explored in detail the time evolution of the conductivity, as well as other quantum-level electron transport characteristics, of a graphene device subjected to periodic ultra-short pulses. To date, the majority of graphene studies have considered the dependency of transport properties on the characteristics of the external pulses, such as field strength, period or frequency. The new findings have now been published in EPJ B by Doniyor Babajanov from the Turin Polytechnic University in Tashkent, Uzbekistan, and colleagues. These results may help to develop graphene-based electronic devices that only become conductors when an external ultra-short pulse is applied, and are otherwise insulators.

The authors’ focus is on the transport in graphene nanoribbons driven by laser pulses, which were chosen for their ability to apply periodic kicks to the system. Babajanov and colleagues relied on driven quantum systems and quantum chaos theories to study transport characteristics within the nanoribbon. For a single kicking period, they obtained the exact solution of a mathematical equation, called the time-dependent Dirac equation. Then, by iterating this solution they were able to numerically and precisely compute the arbitrary characteristics of time-dependent quantum transport of electrons within the material.

They found that applying external driving force leads to enhancement of electronic transitions within what are referred to as valence and conduction bands. This study thus demonstrates that such transitions allow a dramatic increase in conductivity within a short time, making it possible to tune the electronic properties using short external pulses.

The next stage could be extending the test to the case of a time-dependent magnetic field, to strain-induced pseudo-magnetic fields, or to external monochromatic fields. Ultimately, this could lead to useful applications such as ultrafast electronic switches.

What does it take to fabricate electronic and medical devices tinier than a fraction of a human hair? Nanoengineers at the University of California, San Diego recently invented a new method of lithography in which nanoscale robots swim over the surface of light-sensitive material to create complex surface patterns that form the sensors and electronics components on nanoscale devices. Their research offers a simpler and more affordable alternative to the high cost and complexity of current state-of-the-art nanofabrication methods such as electron beam writing.

Led by distinguished nanoengineering professor and chair Joseph Wang, the team developed nanorobots, or nanomotors, that are chemically-powered, self-propelled and magnetically controlled. Their proof-of-concept study demonstrates the first nanorobot swimmers able to manipulate light for nanoscale surface patterning. The new strategy combines controlled movement with unique light-focusing or light-blocking abilities of nanoscale robots.

“All we need is these self-propelled nanorobots and UV light,” said Jinxing Li, a doctoral student at the Jacobs School of Engineering and first author. “They work together like minions, moving and writing and are easily controlled by a simple magnet.”

State-of-art lithography methods such as electron beam writing are used to define extremely precise surface patterns on substrates used in the manufacture of microelectronics and medical devices.  These patterns form the functioning sensors and electronic components such as transistors and switches packed on today’s integrated circuits. In the mid-20th century the discovery that electronic circuits could be patterned on a small silicon chip, instead of assembling independent components into a much larger “discrete circuit,” revolutionized the electronics industry and set in motion device miniaturization on a scale previously unthinkable.

Today, as scientists invent devices and machines on the nanoscale, there is new interest in developing unconventional nanoscale manufacturing technologies for mass production.

Li was careful to point out that this nanomotor lithography method cannot completely replace the state-of-the-art resolution offered by an e-beam writer, for example. However, the technology provides a framework for autonomous writing of nanopatterns at a fraction of the cost and difficulty of these more complex systems, which is useful for mass production. Wang’s team also demonstrated that several nanorobots can work together to create parallel surface patterns, a task that e-beam writers cannot perform.

The team developed two types of nanorobots: a spherical nanorobot made of silica that focuses the light like a near-field lens, and a rod-shape nanorobot made of metal that blocks the light. Each is self-propelled by the catalytic decomposition of hydrogen peroxide fuel solution. Two types of features are generated: trenches and ridges. When the photoresist surface is exposed to UV light, the spherical nanorobot harnesses and magnifies the light, moving along to create a trench pattern, while the rod-shape nanorobot blocks the light to build a ridge pattern.

“Like microorganisms, our nanorobots can precisely control their speed and spatial motion, and self-organize to achieve collective goals,” said professor Joe Wang. His group’s nanorobots offer great promise for diverse biomedical, environmental and security applications.

UC San Diego is investing heavily in robotics research while leveraging the partnership opportunities afforded by regional industry expertise in supporting fields such as defense and wireless technology, biotech and manufacturing. The Contextual Robotics Technologies International Forum was hosted by the Jacobs School of Engineering, the Qualcomm Institute and the Department of Cognitive Science.

Joe Wang is the director of the Center for Wearable Sensors at UC San Diego Jacobs School of Engineering and holds the SAIC endowed chair in engineering.

Rice University scientists who want to gain an edge in energy production and storage report they have found it in molybdenum disulfide.

The Rice lab of chemist James Tour has turned molybdenum disulfide’s two-dimensional form into a nanoporous film that can catalyze the production of hydrogen or be used for energy storage.

The versatile chemical compound classified as a dichalcogenide is inert along its flat sides, but previous studies determined the material’s edges are highly efficient catalysts for hydrogen evolution reaction (HER), a process used in fuel cells to pull hydrogen from water.

Tour and his colleagues have found a cost-effective way to create flexible films of the material that maximize the amount of exposed edge and have potential for a variety of energy-oriented applications.

Molybdenum disulfide isn’t quite as flat as graphene, the atom-thick form of pure carbon, because it contains both molybdenum and sulfur atoms. When viewed from above, it looks like graphene, with rows of ordered hexagons. But seen from the side, three distinct layers are revealed, with sulfur atoms in their own planes above and below the molybdenum.

This crystal structure creates a more robust edge, and the more edge, the better for catalytic reactions or storage, Tour said.

“So much of chemistry occurs at the edges of materials,” he said. “A two-dimensional material is like a sheet of paper: a large plain with very little edge. But our material is highly porous. What we see in the images are short, 5- to 6-nanometer planes and a lot of edge, as though the material had bore holes drilled all the way through.”

The new film was created by Tour and lead authors Yang Yang, a postdoctoral researcher; Huilong Fei, a graduate student; and their colleagues. It catalyzes the separation of hydrogen from water when exposed to a current. “Its performance as a HER generator is as good as any molybdenum disulfide structure that has ever been seen, and it’s really easy to make,” Tour said.

While other researchers have proposed arrays of molybdenum disulfide sheets standing on edge, the Rice group took a different approach. First, they grew a porous molybdenum oxide film onto a molybdenum substrate through room-temperature anodization, an electrochemical process with many uses but traditionally employed to thicken natural oxide layers on metals.

The film was then exposed to sulfur vapor at 300 degrees Celsius (572 degrees Fahrenheit) for one hour. This converted the material to molybdenum disulfide without damage to its nano-porous sponge-like structure, they reported.

The films can also serve as supercapacitors, which store energy quickly as static charge and release it in a burst. Though they don’t store as much energy as an electrochemical battery, they have long lifespans and are in wide use because they can deliver far more power than a battery. The Rice lab built supercapacitors with the films; in tests, they retained 90 percent of their capacity after 10,000 charge-discharge cycles and 83 percent after 20,000 cycles.

“We see anodization as a route to materials for multiple platforms in the next generation of alternative energy devices,” Tour said. “These could be fuel cells, supercapacitors and batteries. And we’ve demonstrated two of those three are possible with this new material.”

Co-authors of the paper are Rice graduate students Gedeng Ruan and Changsheng Xiang. Tour is the T.T. and W.F. Chao Chair in Chemistry as well as a professor of materials science and nanoengineering and of computer science.

The Peter M. and Ruth L. Nicholas Postdoctoral Fellowship of Rice’s Smalley Institute for Nanoscale Science and Technology and the Air Force Office of Scientific Research Multidisciplinary University Research program supported the research.

At this week’s VISION 2014 exhibition, imec presents a backside-illuminated (BSI) CMOS image sensor chip featuring a new anti-reflective coating (ARC) optimized for UV light. Targeting imaging solutions in new markets such as life sciences, the achievement is an important addition to imec’s customized 200mm CMOS fab. This 200mm process line enables imec to offer design, prototyping and low volume manufacturing of custom specialty chip solutions such as highly specialized CMOS image sensors.

Known for its superior enhanced light sensitivity compared with image sensors using front side illumination (FSI), BSI sensors are top candidates to further improve the performance of CMOS image sensors. Widely spread today in consumer applications such as smart phones, BSI imagers are expected to enter the higher-end application space of e.g. industrial inspection.

BSI imagers have a clear advantage when it comes to fill factor for the pixel area, angular response, and the complete avoidance of absorption or scattering losses in the metal interconnect layers.  The cost for these light gathering improvement are the extra process complexity for the backside fabrication and possible electrical and optical losses at the new backside silicon interface. Therefore the engineering of the backside layers and interfaces is key to develop high performance BSI devices.

Imec is tackling these challenges to exploit the benefits of BSI imagers for highly specialized customized imagers for space applications, high speed cameras, semiconductor inspection and medical applications. To minimize reflection losses and maximize transmission of light to the sensor, specific anti-reflective coatings (ARC) are developed for various applications targeting different regions of the light spectrum. The coatings are applied at wafer level as part of the BSI process flow.

Imec has already developed an ARC for visible light range (400nm-800nm) with >70% QE over the entire spectral range. Imec’s new ARC, targeting the UV range, shows excellent performance at near UV wavelengths, with Quantum Efficiency (Q.E.) values above 50 percent over the entire spectral range from 260nm to 400nm wavelength.

“This is an important milestone for imec’s customized 200mm CMOS process line, demonstrating our expertise and capability to design, prototype and manufacture high-end CMOS image sensors,” said Rudi Cartuyvels, senior vice president, Smart Systems & Energy Technologies at imec. “The development widens our portfolio towards new markets, offering solutions for both visible and UV imaging in semiconductor equipment applications, such as advance lithography and wafer and mask inspection.”

Kilopass Technology Inc., a provider of semiconductor logic embedded non-volatile memory (eNVM) intellectual property (IP), announced today that it has successfully ported its one-time programmable (OTP) NVM technology to TSMC’s 16 nanometer (nm) FinFET process.

“Embedded non-volatile memories are becoming an increasingly important part of SoC designs created by our key customers,” notes Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Kilopass’ support for this technology at the 16FinFET node enables us to offer our mutual customers a complete solution that saves design time, chip area and power consumption.”

The Kilopass OTP 2T bit cell continues to be easily manufactured and demonstrates the high level of reliability and performance similar to results produced at other process geometries built with planar transistor structures. Kilopass’ OTP 2T bit cell technology can scale easily from 180nm to 28nm and beyond across a wide variety of process technologies including low power, high-voltage, and high-K metal gate.

As TSMC process migrates to FinFET transistor structures, Kilopass’ antifuse OTP NVM was successfully ported to the FinFET process. The solution provided will also cover the methodology that meets the challenges of OTP NVM memory IP design for FinFET technology to enable faster time to market with high quality and reliability for TSMC and Kilopass’ joint customers.

Christophe Chevallier, Kilopass’ vice president of engineering, presented the performance and reliability data of Kilopass OTP 16nm FinFET memory cell at the recent TSMC Open Innovation Platform Forum.

Semiconductor Manufacturing International Corporation and Maxscend Technologies Inc., a RF IP company based in China, announced that Maxscend Bluetooth RF IP has been silicon proven on SMIC’s 55nm low leakage logic process. This IP has now been integrated into one of SMIC customers’ product tape-out.

The silicon proven Bluetooth RF IP is the result of a collaborative effort between SMIC and Maxscend and marks a significant milestone in SMIC RF IP platform setup. It has achieved a leading edge position in the industry and will provide mutual customers an excellent IP solution for the booming IoT market, as well as the prosperous mobile and tablet markets.

Dr. Tianshen Tang, Senior Vice President of SMIC Design Service Center commented, “We are pleased to be working with Maxscend. This important breakthrough will enable SMIC to offer leading 55nm RF IP solutions and secure SMIC’s position in China’s semiconductor foundry industry. We are confident that we can provide top quality solutions and design services for the customer.”

“It is really exciting to see that our Bluetooth and BLE RF IP has been silicon proven on SMIC 55nm platform,” said Zhihan Xu, Chief Executive Officer of Maxscend. “Besides the current huge demand of smart-phones, tablets, Bluetooth Audio and other areas of traditional Bluetooth technologies, there is tremendous interest coming from low-power Bluetooth in the IoT field. With the wide adoption of Bluetooth low energy technology, smart devices will become ubiquitous in everyday life: wearables, smart-home, smart-medical, smart-sports and many more. By partnering with SMIC, we are confident we have the capabilities to support global customers with superior Bluetooth technology and professional technical services.”

Adlyte Inc., a developer of high-brightness extreme light sources for advanced semiconductor inspection and metrology applications, today announced it has reached a key performance benchmark for its extreme ultraviolet (EUV) light source for high-volume manufacturing (HVM)-readiness. Adlyte has demonstrated that its EUV light source has maintained clean operation after intermediate focus while running for hundreds of hours replicating multiple parameters for a production environment—including power, brightness and uptime—established by mask inspection original equipment manufacturers (OEMs).

Adlyte Inc.'s LPP (Laser Produced Plasma) sources produce high-brightness EUV light by focusing a pulsed laser on high frequency droplets of tin.

Adlyte Inc.’s LPP (Laser Produced Plasma) sources produce high-brightness EUV light by focusing a pulsed laser on high frequency droplets of tin.

One of three laser produced plasma (LPP) EUV light-source suppliers in the world, Adlyte is the only one focused on developing light sources for photomask and wafer inspection applications, which are critical for manufacturing future generations of advanced semiconductor devices.

“Mask inspection is a critical part of the EUV lithography infrastructure, and having actinic or ‘at wavelength’ exposure that meets several key criteria, including cleanliness, is the optimal solution for finding the defects that matter on EUV masks,” stated Hidehiro Watanabe, general manager, EUVL Infrastructure Development Center (EIDEC). “We are pleased with the cleanliness we measured on Adlyte’s light source under conditions that replicate a production environment. This meets our requirements for blank mask inspection.”

“Working with our customers and industry partners, Adlyte is committed to advancing the EUV roadmap and helping to enable the production of defect-free EUV masks,” stated Daniel Boehringer, chairman of the board at Adlyte. “We are very encouraged with the latest results we achieved against the cleanliness benchmark established by mask inspection OEM companies. This is testament to the significant investments we’ve made in developing our light-source technology.”

Importance of “clean” EUV light sources

Extremely small nanometer-scale defects on EUV masks and patterned wafers can result in catastrophic yield losses. High-brightness EUV light sources are needed to detect and capture these defects with high throughput and uptime. As with EUV lithography, the clean operation of light sources for EUV mask and wafer inspection/metrology equipment is very important to achieving higher production efficiency and lower cost of ownership.

LPP sources provide a platform that can achieve high brightness and power operation but have historically been challenged in providing the cleanliness needed for HVM applications. Following its previous achievements of meeting the high-source-brightness (250 Watts/mm2 steradian) and power (20 Watts of power into 2 pi) specifications for EUV mask inspection, Adlyte has now demonstrated the required light-source cleanliness needed after the intermediate focus for implementing EUV photomask inspection in HVM.

Adlyte will present these and other EUV light-source technology developments at the 2014 International Workshop on EUV and Soft X-Ray Sources in Dublin, Ireland, November 3-6.

University of Oregon chemists have devised a way to see the internal structures of electronic waves trapped in carbon nanotubes by external electrostatic charges.

Carbon nanotubes have been touted as exceptional materials with unique properties that allow for extremely efficient charge and energy transport, with the potential to open the way for new, more efficient types of electronic and photovoltaic devices. However, these traps, or defects, in ultra-thin nanotubes can compromise their effectiveness.

Using a specially built microscope capable of imaging matter at the atomic scale, the researchers were able to visualize traps, which can adversely affect the flow of electrons and elementary energy packets called excitons.

The study, said George V. Nazin, a professor of physical chemistry, modeled the behavior often observed in carbon nanotube-based electronic devices, where electronic traps are induced by stochastic external charges in the immediate vicinity of the nanotubes. The external charges attract and trap electrons propagating through nanotubes.

“Our visualization should be useful for the development of a more accurate picture of electron propagation through nanotubes in real-world applications, where nanotubes are always subjected to external perturbations that potentially may lead to the creation of these traps,” he said.

The research, detailed in a paper in the Journal of Physical Chemistry Letters, was done with an ultra-high vacuum scanning tunneling microscope coupled to a closed-cycle cryostat — a novel device built for use in Nazin’s lab. The cryostat allowed Nazin and his co-authors Dmitry A. Kislitsyn and Jason D. Hackley, both doctoral students, to lower the temperature to 20 Kelvin to freeze all nanoscale motion, and visualize the internal structures of nanoscale objects.

The device captured the internal structure of electronic waves trapped in short sections, just several nanometers long, of nanotubes partially suspended above an atomically flat gold surface. The properties of the waves, to a large extent, Nazin said, determine electron transmission through such electronic traps. The propagating electrons have to be in resonance with the localized waves for efficient electronic transmission to occur.

“Amazingly, by finely tuning the energies of propagating electrons, we found that, in addition to these resonance transmission channels, other resonances also are possible, with energies matching those of specific vibrations in carbon nanotubes,” he said. “These new transmission channels correspond to ‘vibronic’ resonances, where trapped electronic waves excite vibrations of carbon atoms forming the electronic trap.”

The microscope the team used is detailed separately in a freely available paper (High-stability cryogenic scanning tunneling microscope based on a closed-cycle cryostat) placed online Oct. 7 by the journal Review of Scientific Instruments.

The development of increasingly sophisticated and energy-efficient CMOS technology for mobile, client and cloud computing depends on a continuing stream of advances in the process technologies with which the complex integrated circuits are built. Among the most promising chip technologies are transistors called FinFETs, which have attracted significant R&D investment and have begun to appear in commercial products.

But the technology is complex and the path forward isn’t settled, and in two late-news papers to be given at this December’s IEEE International Electron Devices Meeting (IEDM), Intel and IBM will present dueling approaches to the development of FinFET technology for the 14nm technology node, the semiconductor industry’s next big hurdle.

The IEDM is the forum where top technical experts in micro- and nanoelectronics gather to disclose, discuss and debate breakthrough technologies in the field. The 60th annual IEDM will be held at the Hilton San Francisco Union Square Hotel from December 15-17, 2014, preceded by day-long short courses on Sunday, Dec. 14 and a program of 90-minute tutorials on Saturday, Dec. 13.

All modern transistors have a channel to conduct electricity and one or more gates to turn the current on and off. FinFETs have long, thin fin-like channels (hence the name) surrounded by multiple gates. This design leads to greater performance and enhanced energy efficiency. Both Intel and IBM will present fully integrated 14nm FinFET technologies at the IEDM.

Intel, which began using FinFET transistors commercially in its “Ivy Bridge” and “Haswell” processors at the 22nm node, will detail the second generation of that technology.[i] Made on a standard bulk silicon substrate, the new “Broadwell” 14nm technology has been released commercially and is in production as part of Intel’s latest family of microprocessors.

Among the technical features Intel will discuss at the IEDM are: a novel doping technique to prevent current leakage under the fins and to maintain very low doped fins, resulting in improvement in variation; two levels of air-gap-insulated interconnects (electrical connections) at ultra-narrow 80 and 160nm minimum pitches, yielding a 17% reduction in capacitance delays; eight layers of 52nm pitch interconnects embedded in low-k dielectrics; an embedded 140Mb SRAM memory with a tiny cell size of 0.0588µm2; and saturated drive currents significantly higher than for Intel’s 22nm first-generation FinFETs (improvements of 15% and 41% for NMOS and PMOS transistors, respectively). The transistors operate with a supply voltage of only 0.7 Volts.

The researchers also will discuss how aggressive design rules enabled the production of very high aspect ratio rectangular fins (8nm wide and 42nm high) at unprecedented levels of uniformity.

IBM, meanwhile, will describe a very different approach to 14nm FinFET transistors.[ii] The IBM devices are made not from a standard bulk silicon substrate but from an insulating substrate known as SOI, a more expensive material but one which simplifies manufacturing in terms of device isolation. These devices are more than 35% faster than IBM’s 22nm planar (i.e. standard, non-FinFET) transistors, with an operating voltage of just 0.8 volts.

The IBM technology features what may be the smallest, densest embedded DRAM memory ever demonstrated (a cell size of just 0.0174µm2) for high-speed performance in a fully integrated process flow. IBM also designed an elegant way to make the technology suitable for both low-power and high-speed applications, using a unique dual-workfunction process that optimizes the threshold voltages of both NMOS and PMOS transistors without any mobility degradation in the channel.

Because the technology is envisioned for use in system-on-a-chip (SoC) applications ranging from video game consoles to enterprise-level corporate data centers, the IBM design also features a record 15 levels of copper interconnect to give circuit designers more freedom that ever before to distribute power and clock signals efficiently across an entire SoC chip, which may be as large as 600mm2.

Making transistors smaller, or scaling them according to Moore’s Law, is what has traditionally driven exponential progress in nanoelectronics and information technology. With today’s nanoscale-sized devices that has become difficult and expensive, which is why new transistor architectures such as FinFETs have become so appealing.

[i] Paper #3.7, “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588µm2 SRAM Cell Size,” S. Natarajan et al, Intel

[ii]  Paper #3.8, “High Performance 14nm SOI FinFET CMOS Technology with 0.0174µm2 Embedded DRAM and 15 Levels of Cu Metallization,” C.-H. Lin et al, IBM

Albert Theuwissen, CEO of Harvest Imaging and professor at Delft University of Technology, is the recipient of the European SEMI Award 2014. The Award, which recognizes Theuwissen’s outstanding contribution to the continuing education of engineers, was presented during the SEMICON Europa Executive Summit in Grenoble today.

Albert Theuwissen is a highly regarded specialist in solid-state image sensors and digital imaging. He worked for nearly 20 years at Philips Research and then at DALSA in lead engineering and management roles. In 2001, Theuwissen became a part-time professor at Delft University of Technology.  In 1995, he wrote the textbook “Solid-State Imaging with Charge-Coupled Devices” which is now a standard reference work in the field of solid-state imaging.

After “retiring” in 2007, Theuwissen founded Harvest Imaging and has played a major role in the continuing education of engineers in the field of solid-state imaging and digital cameras. He has taught and trained over 3,000 engineers at image sensor companies (such as Kodak, Sony, Samsung, Aptina, ST Microelectronics, Micron, Intel, Philips, Canon, DALSA, and Panasonic) and consumer product companies (such as Nokia, Sony-Ericsson, Motorola, Siemens, Research InMotion, Thomson, and many others).  In addition, he has conducted short courses at IEEE’s IEDM, ISSCC, ICIP and SPIE’s Electronic Imaging Conference.

Solid-state image sensors such as the Charge-Coupled Device (CCD) and CMOS Image Sensor (CIS) are complex electron devices.  About one billion image sensor chips are fabricated and sold each year and represent a multi-billion dollar per year IC business segment.  Understanding the fabrication and device physics operation of these devices is difficult and is rarely taught in universities at either the undergraduate or graduate level.

Theuwissen has had a major impact on both the continuing education of engineers and the advancement of consumer digital imaging.  Continuing education — outside of the scope of university professors operating as part-time short-course instructors — within the industry is critical.  By educating technologists and application specialists, Theuwissen created a successful model for future technological education: the entrepreneur-educator.

“Albert recognized the need for technical education and created a successful continuing education offering that navigates and conforms to the competitive and proprietary IP environment, benefitting thousands of electron-device engineers and also the industry,” said Heinz Kundert, president of SEMI Europe. “It is an honor to recognize Albert for his outstanding contributions to the European semiconductor and microsystems industry.”

The European SEMI Award was established more than two decades ago to recognize individuals and teams who made a significant contribution to the European semiconductor and related industries. Prior award recipients hailed from these companies: Infineon, Semilab, Deutsche Solar, STMicroelectronics, IMEC, Fraunhofer Institute, and more.