Tag Archives: letter-wafer-tech

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the EVG 580 ComBond―a high-vacuum wafer bonding system, which enables electrically conductive and oxide-free covalent bonds at room temperature. Built on a modular platform to support high-volume manufacturing (HVM) requirements, the new system is ideally suited for bonding different substrate materials together in order to enable higher-performing devices and new applications, including:

  • Multi-junction solar cells
  • Silicon photonics
  • High-vacuum MEMS packaging
  • Power devices
  • Compound semiconductor and other advanced engineered substrates for “beyond CMOS” applications such as high-mobility transistors, high-performance/low-power logic and radio frequency (RF) devices

“During the recent installation and acceptance test phase our new EVG580 ComBond has demonstrated its capacity to create excellent covalent bonds at room temperature. CEA-Leti is looking forward to working with EVG within our Common Lab on implementing the EVG580 ComBond to further development activities in several key areas,” said Fabrice Geiger, VP Silicon Technologies Division at CEA-Leti.

“The EVG580 ComBond system masters the crucial surface preparation steps that are needed to ensure contamination- and oxide-free bonds at room temperature,” stated Paul Lindner, executive technology director at EV Group. “With this breakthrough technology, we can bond nearly anything on anything—creating many different material combinations in wafer form. This supports our customers’ efforts to develop and ramp new devices into mass production to enable a variety of emerging and high-growth applications—from the development of silicon photonics for next-generation telecommunications to more advanced power devices that can enable electric vehicles to drive longer distances between charges.”

Challenges with Combining Compound Semiconductors and Silicon

Combining materials with different properties to produce electronic devices, such as III-V compound semiconductor materials like gallium nitride (GaN), gallium arsenide (GaAs) and indium phosphide (InP) with silicon substrates, can lead to enhanced device performance due to higher carrier mobility as well as open up new capabilities such as the emission of light through silicon, which can enable optical interconnects and routers. However, combining these materials through traditional epitaxial growth processes leads to crystal dislocation defects due to differences in lattice constant and coefficient of thermal expansion (CTE), which in turn degrade performance.

When someone crumples a sheet of paper, that usually means it’s about to be thrown away. But researchers have now found that crumpling a piece of graphene “paper” — a material formed by bonding together layers of the two-dimensional form of carbon — can actually yield new properties that could be useful for creating extremely stretchable supercapacitors to store energy for flexible electronic devices.

The finding is reported in the journal Scientific Reports by MIT’s Xuanhe Zhao, an assistant professor of mechanical engineering and civil and environmental engineering, and four other authors. The new, flexible superconductors should be easy and inexpensive to fabricate, the team says.

“Many people are exploring graphene paper: It’s a good candidate for making supercapacitors, because of its large surface area per mass,” Zhao says. Now, he says, the development of flexible electronic devices, such as wearable or implantable biomedical sensors or monitoring devices, will require flexible power-storage systems.

Like batteries, supercapacitors can store electrical energy, but they primarily do so electrostatically, rather than chemically — meaning they can deliver their energy faster than batteries can. Now Zhao and his team have demonstrated that by crumpling a sheet of graphene paper into a chaotic mass of folds, they can make a supercapacitor that can easily be bent, folded, or stretched to as much as 800 percent of its original size. The team has made a simple supercapacitor using this method as a proof of principle.

The material can be crumpled and flattened up to 1,000 times, the team has demonstrated, without a significant loss of performance. “The graphene paper is pretty robust,” Zhao says, “and we can achieve very large deformations over multiple cycles.” Graphene, a structure of pure carbon just one atom thick with its carbon atoms arranged in a hexagonal array, is one of the strongest materials known.

To make the crumpled graphene paper, a sheet of the material was placed in a mechanical device that first compressed it in one direction, creating a series of parallel folds or pleats, and then in the other direction, leading to a chaotic, rumpled surface. When stretched, the material’s folds simply smooth themselves out.

Forming a capacitor requires two conductive layers — in this case, two sheets of crumpled graphene paper — with an insulating layer in between, which in this demonstration was made from a hydrogel material. Like the crumpled graphene, the hydrogel is highly deformable and stretchable, so the three layers remain in contact even while being flexed and pulled.

Though this initial demonstration was specifically to make a supercapacitor, the same crumpling technique could be applied to other uses, Zhao says. For example, the crumpled graphene material might be used as one electrode in a flexible battery, or could be used to make a stretchable sensor for specific chemical or biological molecules.

Highlights at the recent SPIE Photomask Technology 2014 conference included a confident announcement from ASML about current EUV source capabilities, an insightful industry-expert panel discussion on mask-making complexities, and fresh energy from the co-located SPIE Scanning Microscopies conference. The event ran 16-18 September at the Monterey Conference Center and Monterey Marriott, and was sponsored by SPIE, the international society for optics and photonics.

In an attention-grabbing announcement, keynote speaker Martin van den Brink, President and CTO of ASML, said that extreme ultraviolet (EUV) source technology is reaching performance levels that enable introduction into production lines in select cases at the 10nm node, and that progress is such that it should soon be ready for full-scale introduction at the 7nm node.

The announcement was important because significant customers have recently criticized ASML for being late on development of EUV technology, which is intended to enable the next generation of computer-chip manufacturing, and have been experimenting with potential alternatives.
Van den Brink’s talk detailed ASML’s steady and substantial progress over the past several months improving the technology for eventual scale-up in semiconductor manufacturing.

The challenge, he said, is implementing affordable scaling to create lower cost and improved performance. That can be achieved through holistic lithography immersion driving productivity and yield with multiple patterning, and with EUV technology driving productivity and improving operational cost to enable 2D patterning and simpler processing, van den Brink said.

During the meeting, Jim Wiley, EUV Infrastructure Executive Strategist at ASML, was presented with the 2014 Photomask Lifetime Achievement Award in recognition of contributions to the industry, particularly in the area of photomask defect characterization, printability, and publication. He has been a supporting member of the Bay Area Chrome User Society (BACUS) since its founding and has served in many leadership roles.

Dan Meisburger of Tec-Start Consulting was awarded the 2014 BACUS Prize in recognition of his work and influence in the development of the high-speed electron beam mask inspection system.

Linda He Yi of the Nanoelectronics Lab in the Department of Electrical Engineering at Stanford University was awarded the 2014 BACUS Scholarship. Working in applications of block copolymer directed self-assembly, she has more than 15 publications and collaborations with ASML, GlobalFoundries, and Applied Materials.

A two-day exhibition included top industry suppliers showing products and systems using technology such as e-beam lithography, EUV, direct laser writing, resists, optical/laser microlithography, and electronic hardware and software.

Photomask Technology included more than 70 presentations on mask making, EUV, 9-inch glass, emerging mask technologies, mask business, and related topics. Paul Ackmann (GlobalFoundries) was symposium chair, and Naoya Hayashi (Dai Nippon Printing) was symposium cochair.

Scanning Microscopies brought approximately 50 more presentations to the conference, in areas such as nanomaterials, optical and particle beam, scanned probe, and imaging. Symposium chairs were Michael Postek and Dale Newbury (National Institute of Standards and Technology), Frank Platek (U.S. Food and Drug Administration), and Tim Maugel (University of Maryland, College Park).

Conference proceedings are being published online in the SPIE Digital Library as manuscripts are approved, with CD and print publication to follow when all manuscripts are published.

Dow Corning, a developer of silicon and wide-bandgap semiconductor technology, announced that it now offers 150mm diameter silicon carbide (SiC) wafers under its Prime Grade portfolio. Recently launched to set new standards for 100mm SiC wafer quality, the portfolio now also offers three tiers of manufacturing quality 150mm SiC substrates – labeled Prime Standard, Prime Select and Prime Ultra. Each tier offers increasingly stringent tolerances on critical defect types that adversely impact device performance, such as micropipe density (MPD), threading screw dislocations (TSD) and basal plane dislocations (BPD).

“SiC wide-bandgap power semiconductors have rapidly evolved from a cutting-edge niche into an established technology sector that is increasingly focused on the manufacturing economies afforded by SiC crystal quality, wafer size and other critical factors,” said Tang Yong Ang, vice president, Compound Semiconductor Solutions, Dow Corning. “Dow Corning’s decision to expand its Prime Grade portfolio to include 150mm diameter SiC wafers aims to meet this very competitive demand. As we rapidly scale production of these high-quality wafers, our customers will be able to more confidently pinpoint the SiC substrate that optimizes the performance and cost of their next-generation device design while leveraging the improved economies of scale offered by larger wafer diameters.”

While many SiC wafer manufacturers promise low micropipe densities for their 150mm substrates, Dow Corning is among the first to specify low tolerances of other defect types, such as TSD and BPD. Such defects reduce device yields, and inhibit the cost efficient manufacture of large-area, next-generation power electronic devices with higher current ratings.

“Dow Corning’s close customer collaboration in both silicon and wide bandgap semiconductor technologies has given us a clear understanding of the competitive demands and opportunities in these markets,” said Gregg Zank, chief technology officer, Dow Corning.

FlipChip International (FCI), a developer of flip chip bumping and advanced wafer level packaging technologies, announced that their engineering team had completed design and production of the 250th Multi-Product Wafer Bump design since January 2013.

Multi-Product Wafer (MPW) Bump Designs are complex and challenging to create but provide a way for customers to quickly test multiple IC designs and provide samples to customers. MPW wafers have many different ICs fabricated on the same wafer. These can be design variations of a single base IC, to help optimize functional performance, or many completely different ICs with different die sizes. FCI has created thousands of product and MPW designs for customers around the world, and partners with many semiconductor manufacturers and foundries to enable them to test out hundreds of new IC designs and sample their customers with bumped ICs without going to the cost of creating individual mask sets for each new IC. FCI’s ability to design, manufacture, and inspect a large number of MPW designs, as well as full-production designs, places them at the cutting edge of advanced Wafer Level Package development.

Doug Scott, FlipChip’s Sr. Director of Engineering, said, “This is an important milestone for FlipChip, reaching the 250 MPW designs in such a short time frame. I’m very proud of the technical team at FCI in achieving this accomplishment. Our dedication to supporting the engineering requirements of all of our customers is an important strength of FCI. We strive to find the best technical solution for our customers, and we’re very pleased to be such an important part of our customers’ development strategy.”

David Wilkie, FlipChip’s CEO, said, “I’d like to congratulate the team for this important milestone. The dedication of the Engineering group in supporting customers around the world in finding the best technical solution to their wafer level packaging challenges remains a core strength of FCI. We’re very proud of our engineering team, and we remain committed to supporting our customers at the highest technical levels.”

Researchers from The University of Texas at Dallas have created technology that could be the first step toward wearable computers with self-contained power sources or, more immediately, a smartphone that doesn’t die after a few hours of heavy use.

This technology, published online in Nature Communications, taps into the power of a single electron to control energy consumption inside transistors, which are at the core of most modern electronic systems.

Researchers from the Erik Jonsson School of Engineering and Computer Science found that by adding a specific atomic thin film layer to a transistor, the layer acted as a filter for the energy that passed through it at room temperature. The signal that resulted from the device was six to seven times steeper than that of traditional devices. Steep devices use less voltage but still have a strong signal.

“The whole semiconductor industry is looking for steep devices because they are key to having small, powerful, mobile devices with many functions that operate quickly without spending a lot of battery power,” said Dr. Jiyoung Kim, professor of materials science and engineering in the Jonsson School and an author of the paper. “Our device is one solution to make this happen.”

Tapping into the unique and subtle behavior of a single electron is the most energy-efficient way to transmit signals in electronic devices. Since the signal is so small, it can be easily diluted by thermal noises at room temperature. To see this quantum signal, engineers and scientists who build electronic devices typically use external cooling techniques to compensate for the thermal energy in the electron environment. The filter created by the UT Dallas researchers is one route to effectively filter out the thermal noise.

Dr. Kyeongjae “K.J.” Cho, professor of materials science and engineering and physics and an author of the paper, agreed that transistors made from this filtering technique could revolutionize the semiconductor industry.

“Having to cool the thermal spread in modern transistors limits how small consumer electronics can be made,” said Cho, who used advanced modeling techniques to explain the lab phenomena. “We devised a technique to cool the electrons internally — allowing reduction in operating voltage — so that we can create even smaller, more power efficient devices.”

Each time a device such as a smartphone or a tablet computes it requires electrical power for operation. Reducing operating voltage would mean longer shelf lives for these products and others. Lower power devices could mean computers worn with or on top of clothing that would not require an outside power source, among other things.

To create this technology, researchers added a chromium oxide thin film onto the device. That layer, at room temperature of about 80 degrees Fahrenheit, filtered the cooler, stable electrons and provided stability to the device. Normally, that stability is achieved by cooling the entire electronic semiconductor device to cryogenic temperatures — about minus 321 degrees Fahrenheit.

Another innovation used to create this technology was a vertical layering system, which would be more practical as devices get smaller.

“One way to shrink the size of the device is by making it vertical, so the current flows from top to bottom instead of the traditional left to right,” said Kim, who added the thin layer to the device.

Lab test results showed that the device at room temperature had a signal strength of electrons similar to conventional devices at minus 378 degrees Fahrenheit. The signal maintained all other properties. Researchers will also try this technique on electrons that are manipulated through optoelectronic and spintronic — light and magnetic — means.

The next step is to extend this filtering system to semiconductors manufactured in Complementary Metal-Oxide Semiconductor (CMOS) technology.

“Electronics of the past were based on vacuum tubes,” Cho said. “Those devices were big and required a lot of power. Then the field went to bipolar transistors manufactured in CMOS technology. We are now again facing an energy crisis, and this is one solution to reduce energy as devices get smaller and smaller.”

Researchers from the Lam Research Corporation in California, Nankai University in China, the University of Michigan and the University of Texas at Arlington contributed to this work.

Electrical engineers at the Technische Universität München (TUM) have demonstrated a new kind of building block for digital integrated circuits. Their experiments show that future computer chips could be based on three-dimensional arrangements of nanometer-scale magnets instead of transistors. As the main enabling technology of the semiconductor industry – CMOS fabrication of silicon chips – approaches fundamental limits, the TUM researchers and collaborators at the University of Notre Dame are exploring “magnetic computing” as an alternative. They report their latest results in the journal Nanotechnology.

In a 3D stack of nanomagnets, the researchers have implemented a so-called majority logic gate, which could serve as a programmable switch in a digital circuit. They explain the underlying principle with a simple illustration: Think of the way ordinary bar magnets behave when you bring them near each other, with opposite poles attracting and like poles repelling each other. Now imagine bringing several bar magnets together and holding all but one in a fixed position. Their magnetic fields can be thought of as being coupled into one, and the “north-south” polarity of the magnet that is free to flip will be determined by the orientation of the majority of fixed magnets.

Gates made from field-coupled nanomagnets work in an analogous way, with the reversal of polarity representing a switch between Boolean logic states, the binary digits 1 and 0. In the 3D majority gate reported by the TUM-Notre Dame team, the state of the device is determined by three input magnets, one of which sits 60nm below the other two, and is read out by a single output magnet.

The latest in a line of advances

This work builds on capabilities the collaborators have developed over several years, ranging from sophisticated simulations of magnetic behavior to innovative fabrication and measuring techniques. It also represents not an end point but a milestone in a series of advances.

For example, they reported the world’s first “domain wall gate” at last year’s International Electron Devices Meeting. The scientists use focused ion-beam irradation to change the magnetic properties of sharply defined spots on the device. So-called domain walls generated there are able to flow through magnetic wires under the control of surrounding nanomagnets. This 2D device, TUM doctoral candidate Stephan Breitkreutz explains, “enables signal routing, buffering, and synchronization in magnetic circuits, similar to latches in electrical integrated circuits.”

A fork in the industry roadmap

All players in the semiconductor business benefit from one industry-wide cooperative effort: developing long-range “roadmaps” that chart potential pathways to common technological goals. In the most recent issue of the International Technology Roadmap for Semiconductors, nanomagnetic logic is given serious consideration among a diverse zoo of “emerging research devices.” Magnetic circuits are non-volatile, meaning they don’t need power to remember what state they are in. Extremely low energy consumption is one of their most promising characteristics. They also can operate at room temperature and resist radiation.

The potential to pack more gates onto a chip is especially important. Nanomagnetic logic can allow very dense packing, for several reasons. The most basic building blocks, the individual nanomagnets, are comparable in size to individual transistors. Furthermore, where transistors require contacts and wiring, nanomagnets operate purely with coupling fields. Also, in building CMOS and nanomagnetic devices that have the same function – for example, a so-called full-adder – it can take fewer magnets than transistors to get the job done.

Finally, the potential to break out of the 2D design space with stacks of 3D devices makes nanomagnetic logic competitive. TUM doctoral candidate Irina Eichwald, lead author of the Nanotechnology paper, explains: “The 3D majority gate demonstrates that magnetic computing can be exploited in all three dimensions, in order to realize monolithic, sequentially stacked magnetic circuits promising better scalability and improved packing density.”

“It is a big challenge to compete with silicon CMOS circuits,” adds Dr. Markus Becherer, leader of the TUM research group within the Institute for Technical Electronics. “However, there might be applications where the non-volatile, ultralow-power operation and high integration density offered by 3D nanomagnetic circuits give them an edge.”

This research was supported by the German Research Foundation (DFG).

Gigaphoton Inc., a lithography light source manufacturer, announced today that it has completed development of an electricity-reduction technology for its flagship “GT Series” of argon fluoride (ArF) immersion lasers used for semiconductor lithography processing. Based on the continuous evolution of its leading-edge “Green Innovations” environmental technologies Gigaphoton is unveiling its “eGRYCOS (e-GIGAPHOTON Recycle Chamber Operation System)” product, which enhances laser efficiency and reduces electricity consumption by 15 percent.

The semiconductor industry has been growing faster than other sectors, and one of the key drivers is the evolving improvements in manufacturing equipment. Because of their use as light sources in leading-edge lithography applications, ArF immersion lasers require i increased output power to support new enhancements of the scanners. Current high-volume production lasers are running at 60 W output, but the latest requirement has reached output of 120 W. As industry demand for higher power grows, the electricity that lasers consume will continue to increase as well.

Gigaphoton has addressed this issue through its EcoPhoton program, and has continued to  work on developing a highly efficient laser chamber design. In a laser chamber, excimer gas flows between two electrodes; as the flow speed increases, the discharge becomes more stable, resulting in better laser performance. Gigaphoton’s redesigned chamber features a hydro-dynamically optimized gas flow channel shape, and enables the same speed of gas flow while consuming less electricity. In addition, the newly designed pre-ionization process enables uniform distribution of ions in the main discharge region, providing laser discharge that is 1.2 times more efficient (compared with existing products). As a result, “eGRYCOS” reduces electricity consumption by 15 percent (compared with existing products) without compromising laser performance.

“Gigaphoton has consistently focused on green innovations to support environmentally conscious ‘green fabs’,” said Hitoshi Tomaru, President and CEO of Gigaphoton Inc. “The ‘eGRYCOS’ product is an example of the success of our EcoPhoton program. We will continue to provide our global customers with innovative technologies that enable increased laser performance with lower energy consumption to meet the demands of today’s leading-edge lithography applications.”

Electricity and magnetism rule our digital world. Semiconductors process electrical information, while magnetic materials enable long-term data storage. A University of Pittsburgh research team has discovered a way to fuse these two distinct properties in a single material, paving the way for new ultrahigh density storage and computing architectures.

While phones and laptops rely on electricity to process and temporarily store information, long-term data storage is still largely achieved via magnetism. Discs coated with magnetic material are locally oriented (e.g. North or South to represent “1” and “0”), and each independent magnet can be used to store a single bit of information. However, this information is not directly coupled to the semiconductors used to process information. Having a magnetic material that can store and process information would enable new forms of hybrid storage and processing capabilities.

Such a material has been created by the Pitt research team led by Jeremy Levy, a Distinguished Professor of Condensed Matter Physics in Pitt’s Kenneth P. Dietrich School of Arts and Sciences and director of the Pittsburgh Quantum Institute.

Levy, other researchers at Pitt, and colleagues at the University of Wisconsin-Madison today published their work in Nature Communications, elucidating their discovery of a form of magnetism that can be stabilized with electric fields rather than magnetic fields. Working with a material formed from a thick layer of one oxide—strontium titanate—and a thin layer of a second material—lanthanum aluminate—these researchers have found that the interface between these materials can exhibit magnetic behavior that is stable at room temperature. The interface is normally conducting, but by “chasing” away the electrons with an applied voltage (equivalent to that of two AA batteries), the material becomes insulating and magnetic. The magnetic properties are detected using “magnetic force microscopy,” an imaging technique that scans a tiny magnet over the material to gauge the relative attraction or repulsion from the magnetic layer.

The newly discovered magnetic properties come on the heels of a previous invention by Levy, so-called “Etch-a-Sketch Nanoelectronics” involving the same material. The discovery of magnetic properties can now be combined with ultra-small transistors, terahertz detectors, and single-electron devices previously demonstrated.

“This work is indeed very promising and may lead to a new type of magnetic storage,” says Stuart Wolf, head of the nanoSTAR Institute at the University of Virginia. Though not an author on this paper, Wolf is widely regarded as a pioneer in the area of spintronics.

“Magnetic materials tend to respond to magnetic fields and are not so sensitive to electrical influences,” Levy says. “What we have discovered is that a new family of oxide-based materials can completely change its behavior based on electrical input.”

A team of researchers from the University of Southampton’s Optoelectronics Research Centre (ORC) has developed a new way to fabricate a potential challenger to graphene.

Graphene, a single layer of carbon atoms in a honeycomb lattice, is increasingly being used in new electronic and mechanical applications, such as transistors, switches and light sources, thanks to the unprecedented properties it offers: very low electrical resistance, high thermal conductivity and mechanically stretchable yet harder than diamond.

Now, ORC researchers have developed molybdenum di-sulphide (MoS2), a similar material to graphene that shares many of its properties, including extraordinary electronic conduction and mechanical strength, but made from a metal (in this case molybdenum combined with sulphur).

This new class of thin metal/sulphide materials, known as transition metal di-chalcogenides (TMDCs), has become an exciting complimentary material to graphene. However, unlike graphene, TMDCs can also emit light allowing applications, such as photodetectors and light emitting devices, to be manufactured.

Until recently, fabrication of TMDCs, such as MoS2, has been difficult, as most techniques produce only flakes, typically just a few hundred square microns in area.

Dr Kevin Huang, from ORC who has led the research, explains: “We have been working on the synthesis of chalcogenide materials using a chemical vapour deposition (CVD) process since 2001 and our technology has now achieved the fabrication of large area (>1000 mm2) ultra- thin films only a few atoms thick. Being able to manufacture sheets of MoS2 and related materials, rather than just microscopic flakes, as previously was the case, greatly expands their promise for nanoelectronic and optoelectronic applications.”

Dr Huang and his team published their findings in the latest issue of the journal Nanoscale. They are currently working with several UK companies and universities, as well as leading international centres at MIT and Nanyang Technological University (Singapore).

Dr Huang adds: “Our ability to not only synthesise large uniform thin films but also to transfer these films to virtually any substrate has led to increased demand for our materials. We welcome enquiries from universities and industry who wish to collaborate with us.”