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Researchers from the University of Texas at Austin and Northwestern University have demonstrated a new method to improve the reliability and performance of transistors and circuits based on carbon nanotubes (CNT), a semiconductor material that has long been considered by scientists as one of the most promising successors to silicon for smaller, faster and cheaper electronic devices. The result appears in a new paper published in the journal Applied Physics Letters, from AIP Publishing.

These are optical images of individual SWCNT field-effect transistors. Credit: S. Jang and A. Dodabalapur/University of Texas at Austin

These are optical images of individual SWCNT field-effect transistors.
Credit: S. Jang and A. Dodabalapur/University of Texas at Austin

In the paper, researchers examined the effect of a fluoropolymer coating called PVDF-TrFE on single-walled carbon nanotube (SWCNT) transistors and ring oscillator circuits, and demonstrated that these coatings can substantially improve the performance of single-walled carbon nanotube devices. PVDF-TrFE is also known by its long chemical name polyvinyledenedifluoride-tetrafluoroethylene.

“We attribute the improvements to the polar nature of PVDF-TrFE that mitigates the negative effect of impurities and defects on the performance of semiconductor single-walled carbon nanotubes,” said Ananth Dodabalapur, a professor in the Cockrell School of Engineering at UT Austin who led the research. “The use of [PVDF-TrFE] capping layers will be greatly beneficial to the adoption of single-walled carbon nanotube circuits in printed electronics and flexible display applications.”

The work was done in collaboration between Dodabalapur’s group at UT Austin and Mark Hersam’s group at Northwestern University as part of a Multi-University Research Initiative (MURI) supported by the Office of Naval Research.

A potential successor to silicon chips

Single-walled carbon nanotubes (SWCNT) are just about the thinnest tubes that can be wrought from nature. They are cylinders formed by rolling up a material known as graphene, which is a flat, single-atom-thick layer of carbon graphite. Most single-walled carbon nanotubes typically have a diameter close to 1 nanometer and can be twisted, flattened and bent into small circles or around sharp bends without breaking. These ultra-thin carbon filaments have high mobility, high transparency and electric conductivity, making them ideal for performing electronic tasks and making flexible electronic devices like thin film transistors, the on-off switches at the heart of digital electronic systems.

“Single-walled carbon nanotube field-effect transistors (FETs) have characteristics similar to polycrystalline silicon FETs, a thin film silicon transistor currently used to drive the pixels in organic light-emitting (OLED) displays,” said Mark Hersam, Dodabalapur’s coworker and a professor in the McCormick School of Engineering and Applied Science at Northwestern University. “But single-walled carbon nanotubes are more advantageous than polycrystalline silicon in that they are solution-processable or printable, which potentially could lower manufacturing costs.”

The mechanical flexibility of single-walled carbon nanotubes also should allow them to be incorporated into emerging applications such as flexible electronics and wearable electronics, he said.

For years, scientists have been experimenting with carbon nanotube devices as a successor to silicon devices, as silicon could soon meet its physical limit in delivering increasingly smaller, faster and cheaper electronic devices. Although circuits made with single-walled carbon nanotube are expected to be more energy-efficient than silicon ones in future, their drawbacks in field-effect transistors, such as high power dissipation and less stability, currently limit their applications in printed electronics, according to Dodabalapur.

A new technique to improve the performance of SWCNTs devices

To overcome the drawbacks of single-walled carbon nanotube field-effect transistors and improve their performance, the researchers deposited PVDF-TrFE on the top of self-fabricated single-walled carbon nanotube transistors by inkjet printing, a low-cost, solution based deposition process with good spatial resolution. The fluoropolymer coated film was then annealed or heated in air at 140 degrees Celsius for three minutes. Later, researchers observed the differences of device characteristics.

“We found substantial performance improvements with the fluoropolymer coated single-walled carbon nanotube both in device level and circuit level,” Dodabalapur noted.

On the device level, significant decreases occur in key parameters such as off-current magnitude, degree of hysteresis, variation in threshold voltage and bias stress degradation, which, Dodabalapur said, means a type of more energy-efficient, stable and uniform transistors with longer life time.

On the circuit level, since a transistor is the most basic component in digital circuits, the improved uniformity in device characteristics, plus the beneficial effects from individual transistors eventually result in improved performance of a five-stage complementary ring oscillator circuit, one of the simplest digital circuits.

“The oscillation frequency and amplitude [of the single-walled carbon nanotube ring oscillator circuit] has increased by 42 percent and 250 percent respectively,” said Dodabalapur. The parameters indicate a faster and better performing circuit with possibly reduced power consumption.

Dodabalapur and his coworkers attributed the improvements to the polar nature of PVDF-TrFE.

“Before single-walled carbon nanotube field-effect transistors were fabricated by inkjet printing, they were dispersed in an organic solvent to make a printable ink. After the fabrication process, there could be residual chemicals left [on the device], causing background impurity concentration,” Dodabalapur explained. “These impurities can act as charged defects that trap charge carriers in semiconductors and reduce carriers’ mobility, which eventually could deteriorate the performance of transistors.”

PVDF-TrFE is a polar molecule whose negative and positive charges are separated on different ends of the molecule, Dodabalapur said. The two charged ends form an electric bond, or dipole, in between. After the annealing process, the dipoles in PVDF-TrFE molecules uniformly adopt a stable orientation that tends to cancel the effects of the charged impurities in single-walled carbon nanotube field-effect transistors, which facilitated carrier flow in the semiconductor and improved device performance.

To confirm their hypothesis, Dodabalapur and his coworkers performed experiments comparing the effects of polar and non-polar vapors on single-walled carbon nanotube field-effect transistors. The results support their assumption.

The next step, Dodabalapur said, is to implement more complex circuits with single-walled carbon nanotube field-effect transistors.

The National Science Foundation (NSF) and Semiconductor Research Corporation (SRC) today announced nine research awards to 10 universities totaling nearly $4 million under a joint program focused on Secure, Trustworthy, Assured and Resilient Semiconductors and Systems (STARSS).

The awards support research at the circuit, architecture and system levels on new strategies, methods and tools to decrease the likelihood of unintended behavior or access; increase resistance and resilience to tampering; and improve the ability to provide authentication throughout the supply chain and in the field.

“The processes and tools used to design and manufacture semiconductors ensure that the resulting product does what it is supposed to do. However, a key question that must also be addressed is whether the product does anything else, such as behaving in ways that are unintended or malicious,” said Keith Marzullo, division director of NSF’s Computer and Network Systems Division, which leads the NSF/SRC partnership on STARSS. “Through this partnership with SRC, we are pleased to focus on hardware and systems security research addressing this challenge and to provide a unique opportunity to facilitate the transition of this research into practical use.”

NSF’s involvement in STARSS is part of its Secure and Trustworthy Cyberspace (SaTC) portfolio, which in August announced nearly $75 million in cybersecurity awards.

The STARRS program expands SRC’s Trustworthy and Secure Semiconductors and Systems (T3S) program, engaging 10 universities across the U.S. Initial T3S industry participants are Freescale, Intel Corporation and Mentor Graphics. NSF is the first federal partner.

“The goal of SRC’s T3S initiative is to develop cost-effective strategies and tools for the design and manufacture of chips and systems that are reliable, trustworthy and secure,” said Celia Merzbacher, SRC Vice President for Innovative Partnerships. “This includes designing for security and assurance at the outset so as to build in resistance and resilience to attack or tampering. The research enabled by the STARSS program with NSF is a cornerstone of this overall effort.”

SRC is a university-research consortium for semiconductors and related technologies.

A number of trends are motivating industry and government to support research in hardware and system security. The design and manufacture of semiconductor circuits and systems requires many steps and involves the work of hundreds of engineers — typically distributed across multiple locations and organizations worldwide. Moreover, a typical microprocessor is likely to include dozens of design modules from various sources. Designers at each level need assurance that the components being incorporated can be trusted in order for the final system to be trustworthy.

Today, the design and manufacture of semiconductor circuits and systems includes extensive verification and testing to ensure the final product does what it is intended to do. Similar approaches are needed to provide assurance that the product is authentic and does not allow unwanted functionality, access or control. This includes strategies, tools and methods at all stages, from architecture through manufacture  and throughout the lifecycle of the product.

The first round of awards made through the STARSS program will support nine research projects with diverse areas of focus. They are:

·      “Combating integrated circuit counterfeiting using secure chip odometers” – Carnegie Mellon University researchers will design and implement secure chip odometers to provide integrated circuits (ICs) with both a secure gauge of use/age and an authentication of provenance to detect counterfeit ICs;

·      “Intellectual Property (IP) Trust-A comprehensive framework for IP integrity validation”- Case Western Reserve University and University of Florida researchers will develop a comprehensive and scalable framework for IP trust analysis and verification by evaluating IPs of diverse types and forms and develop threat models, taxonomy and instances of IP trust/integrity issues.

·      “Design of low-cost, memory-based security primitives and techniques for high-volume products” – University of Connecticut researchers will develop metrics and algorithms to make static RAM physical “unclonable” functions that are substantially more reliable at extreme operating conditions and aging, and extend this to dynamic RAM and Flash;

·      “Trojan detection and diagnosis in mixed-signal systems using on-the-fly learned, pre-computed and side channel tests” – Georgia Institute of Technology researchers will leverage knowledge of state of the art mixed-signal/analog/radio frequency for detection of Trojans in generic mixed-signal systems;

·      “Metric and CAD for differential power analysis (DPA) resistance” – Iowa State University researchers will investigate statistical metrics and design techniques to measure and defend against DPA attacks;

·      “Design of secure and anti-counterfeit integrated circuits” – University of Minnesota researchers will develop hierarchical approaches for authentication and obfuscation of chips;

·      “Hardware authentication through high-capacity, physical unclonable functions (PUF)-based secret key generation and lattice coding” – University of Texas at Austin researchers will develop strong machine-learning resistant PUFs, capable of producing high-entropy outputs, and a new lattice-based stability algorithm for high-capacity secret key generation; and

·      “Fault-attack awareness using microprocessor enhancements” – Virginia Institute of Technology and State University researchers will develop a collection of hardware techniques for microprocessor architectures to detect fault injection attacks, and to mitigate fault analysis through an appropriate response in software.

·      “Invariant carrying machine for hardware assurance” – Northwestern University researchers will develop techniques for improving the reliability and trustworthiness of hardware systems via an Invariant-Carrying Machine approach.

NANIUM today announced it has successfully launched the industry’s largest Wafer-Level Chip Scale Package (WLCSP) in volume. The final units measure 25mm x 23mm and are produced on 300mm wafers, a packaging solution with proven manufacturability that was entirely developed in-house.

“Our customer, Custom Silicon Solutions, is a provider of complex mixed-signal ASIC solutions. We were requested to deliver a customized Fan-In Wafer-Level Packaging/ WLCSP solution beyond common practice, as it was nine times larger in area. Standard WLCSPs usually range up to 8mm x 8mm, in some extreme cases up to 10mm x 10mm,, said Steffen Kroehnert, Director of Technology at NANIUM.

Mike McDaid, Director of Sales at CSS, commented: “After completing a very successful high volume run of a 65nm product in eWLB at NANIUM, we approached them with our next 28nm WLCSP requirements. The first article worked as promised and enabled CSS to get to market quickly with an ASIC which is unprecedented by several times in thermal and computational performance. No other package solution in existence would have achieved the low lead resistance and high reliability we demanded. This ASIC in NANIUM’s WLCSP establishes a new world class of integration, beyond VLSI-SOC (Very Large Scale Integration System-on-Chip). The final product is just about the maximum reticle size allowed and consumes hundreds of Watts.”

The wafers with the high-performance digital chips are produced with 28nm CMOS technology and contain over 5.5 billion transistors, one of the largest transistor-count chip produced by Global Foundries. Once produced in Dresden, Germany, wafers are sent to NANIUM for packaging. Such large dies are usually packaged in Wirebond-BGA or FlipChip-BGA with a small bump pitch, applying underfill material between bumped die and FlipChip substrate to ensure the required board-level reliability. The WLCSP solution developed by NANIUM relies on a high count of 1,188 solder balls at a wide BGA pitch of 0.7mm. It has successfully passed more than 400 temperature cycles on board, as stipulated by the IPC-9701 (TC2) standard, the most critical reliability test for such device.

“It was something new that had never been accomplished in WLCSP before, and we were extremely fortunate that NANIUM decided to take on the challenge,” said Mike McDaid. “Additionally, we were very pleased with the collaborative working process with NANIUM’s engineers. Even when quite formidable design issues were encountered, they proved to be competent, detail-oriented, communicated well and respected the time constraints. We also did a thorough quality audit on-site and were very impressed with the entire manufacturing flow.”

Steffen Kroehnert also commented that “we have been very excited about taking this challenge. At NANIUM, we do our best to understand the needs of our customers and tailor solutions accordingly. CSS has been very satisfied with the performance and the reliability of the product and has approved it for release to volume manufacturing.”

WLCSP is a technology in the semiconductor packaging industry that offers the smallest package form-factor possible. It enables low-cost manufacturing, and a high performance suitable for low I/O density. WLCSP’s product applications include Mobile and consumer products, Wireless connectivity, MEMS and Sensors.

An international team of physicists, led by a research group at the University of Arkansas, has discovered that heating can be used to control the curvature of ripples in freestanding graphene.

The finding provides fundamental insight into understanding the influence temperature exerts on the dynamics of freestanding graphene. This may drive future applications of the flexible circuits of consumer devices such as cell phones and digital cameras.

While freestanding graphene offers promise as a replacement for silicon and other materials in microprocessors and next-generation energy devices, much remains unknown about its mechanical and thermal properties.

The research team published its findings on Wednesday, Sept. 17, in a paper titled “Thermal mirror buckling in freestanding graphene locally controlled by scanning tunneling microscopy” in the online journal Nature Communications, a publication of the journal Nature.

Previously, scientists have used electric voltage to cause large movements and sudden changes in the curvature of the ripples in freestanding graphene, said Paul Thibado, professor of physics at the University of Arkansas. In this paper, the team showed that an alternative method, thermal load, can be used to control these movements.

“Imagine taking a racquetball and cutting it in half,” said Thibado, an expert in experimental condensed matter physics. “You could invert it by pressing on it. That’s what we did here with a cross-section of a single ripple of freestanding graphene at the nanometer scale. Most materials expand when you heat them. Graphene contracts which is very unusual. So when we heated this cross-section, instead of expanding, it contracted, and that thermal stress caused it to buckle in the opposite direction.”

Graphene, discovered in 2004, is a one-atom-thick sheet of graphite. Electrons moving through graphite have mass and encounter resistance, while electrons moving through graphene are massless, and therefore travel much more freely. This makes graphene an excellent candidate material for use in meeting future energy needs and the fabrication of quantum computers, which make enormous calculations with little energy use.

The study was led by Peng Xu, formerly a postdoctoral research associate in the Department of Physics at the University of Arkansas and currently a postdoctoral research associate at the University of Maryland.

Xu and Thibado used scanning tunneling microscopy, which produces images of individual atoms on a surface, combined with large-scale molecular dynamic simulations to demonstrate the thermal mirror buckling.

In the paper, the third published in a major journal by the research team in 2014, they propose a concept for a new instrument that capitalizes on the control of the mirror buckling: a nanoscale electro-thermal-mechanical device.

Such a device would provide an alternative to microelectromechanical systems, which are tiny machines that are activated electrically. The advantage of this nanoscale electro-thermal-mechanical device would be the ability to change its output using electricity or heat. In addition, thermal loads can provide a significantly larger force.

The study, funded by the Office of Naval Research and the National Science Foundation, was conducted primarily through a research partnership between the University of Arkansas and the University of Antwerp in Belgium.

The results were obtained through a collaborative effort with University of Arkansas physics graduate students Steven D. Barber, James Kevin Schoelz and Matthew L. Ackerman; Mehdi Neek-Amal of the University of Antwerp and Shahid Rajaee Teacher Training University in Iran, Ali Sadeghi of the University of Basel in Switzerland and Francois Peeters of the University of Antwerp.

An inter­dis­ci­pli­nary team of researchers led by North­eastern Uni­ver­sity has devel­oped a novel method for con­trol­lably con­structing pre­cise inter-​​nanotube junc­tions and a variety of nanocarbon struc­tures in carbon nan­otube arrays. The method, the researchers say, is facile and easily scal­able, which will allow them to tailor the phys­ical prop­er­ties of nan­otube net­works for use in appli­ca­tions ranging from elec­tronic devices to CNT-​​reinforced com­posite mate­rials found in every­thing from cars to sports equipment.

Their find­ings were pub­lished on Monday in the journal Nature Com­mu­ni­ca­tions. The paper—titled “Sculpting carbon bonds for allotropic trans­for­ma­tion through solid-​​state re-​​engineering of –sp2 carbon”—was co-​​authored by post­docs, stu­dents, and leading CNT researchers from North­eastern Uni­ver­sity, the Mass­a­chu­setts Insti­tute of Tech­nology, and the Korea Advanced Insti­tute of Sci­ence and Tech­nology whose exper­tise runs from physics and mechan­ical engi­neering to mate­rials sci­ence and elec­trical engineering.

The chief archi­tect of the team’s novel method for re-​​engineering carbon bonds was Hyun­y­oung Jung, the paper’s lead author and a post­doc­toral fellow in the lab of co-​​author Yung Joon Jung, a nano-​​manufacturing expert and an asso­ciate pro­fessor of mechan­ical and indus­trial engi­neering.

Hyun­y­oung found that applying con­trolled, alter­nating voltage pulses across single-​​walled carbon nan­otube net­works trans­formed them into larger-​​diameter single-​​walled CNTs; multi-​​walled CNTs of dif­ferent mor­pholo­gies; or multi-​​layered graphene nanorribbons.

The new recon­struc­tion method—unlike pre­vious attempts to meld nanotubes—eschews harsh chem­i­cals and extremely high tem­per­a­tures, making the solid-​​state engi­neering tech­nique emi­nently con­ducive to scal­a­bility. What’s more, the new method pro­duces mol­e­c­ular junc­tions whose elec­trical and thermal con­duc­tiv­i­ties are far supe­rior com­pared to the junction-​​free assem­bled CNT network.

Their robust phys­ical prop­er­ties, the researchers say, make these inter-​​nanotube junc­tions per­fect for rein­forcing com­posite mate­rials that require mechan­ical tough­ness, including tennis rac­quets, golf clubs, cars, and even air­planes, where carbon fibers are cur­rently being used.

“Using these mate­rials for mechan­ical com­po­nents could lighten cars or other mechan­ical struc­tures without sac­ri­ficing strength,” Yung Joon explained.

The researchers described the utility of their ground­breaking work through the use of a metaphor in which carbon nan­otubes were wall-​​building bricks. Fashion a wall by stacking single bricks atop each other, they said, and watch the wall come tum­bling down. But build a wall by placing cement between the bricks and marvel at the indomitable strength of the larger, single unit.

“We have filled in the gaps with cement,” said co-​​author Swastik Kar, an assis­tant pro­fessor of physics at North­eastern, in keeping with the metaphor. “We started with single-​​walled carbon nan­otubes,” he added, “and then used this pio­neering method to bring them together.”

In addi­tion to Kar, Hyun­y­oung, and Yung Joon, the paper’s North­eastern co-​​authors com­prised Younglae Kim, an ex-​​graduate stu­dent, and Sanghyung Hong, a doc­toral can­di­date in Yung Joon Jung’s lab. “Pro­fessor Kar’s and our groups have had a very strong col­lab­o­ra­tion for many years,” Yung Joon said. “This research brings together experts from a number of dis­ci­plines to not only pro­duce a high-​​impact paper but also to gen­erate intel­lec­tual property.”

The team’s research was sup­ported by the National Sci­ence Foun­da­tion and the Min­istry of Industry in the Republic of Korea.

Silicon has few serious competitors as the material of choice in the electronics industry. Yet transistors, the switchable valves that control the flow of electrons in a circuit, cannot simply keep shrinking to meet the needs of powerful, compact devices; physical limitations like energy consumption and heat dissipation are too significant.

Now, using a quantum material called a correlated oxide, Harvard researchers have achieved a reversible change in electrical resistance of eight orders of magnitude, a result the researchers are calling “colossal.” In short, they have engineered this material to perform comparably with the best silicon switches.

The finding arose in what may seem an unlikely spot: a laboratory usually devoted to studying fuel cells—the kind that run on methane or hydrogen—led by Shriram Ramanathan, Associate Professor of Materials Science at the Harvard School of Engineering and Applied Sciences (SEAS). The researchers’ familiarity with thin films and ionic transport enabled them to exploit chemistry, rather than temperature, to achieve the dramatic result.

Because the correlated oxides can function equally well at room temperature or a few hundred degrees above it, it would be easy to integrate them into existing electronic devices and fabrication methods. The discovery, published in Nature Communications, therefore firmly establishes correlated oxides as promising semiconductors for future three-dimensional integrated circuits as well as for adaptive, tunable photonic devices.

Challenging silicon

Although electronics manufacturers continue to pack greater speed and functionality into smaller packages, the performance of silicon-based components will soon hit a wall.

“Traditional silicon transistors have fundamental scaling limitations,” says Ramanathan. “If you shrink them beyond a certain minimum feature size, they don’t quite behave as they should.”

Yet silicon transistors are hard to beat, with an on/off ratio of at least 104 required for practical use. “It’s a pretty high bar to cross,” Ramanathan explains, adding that until now, experiments using correlated oxides have produced changes of only about a factor of 10, or 100 at most, near room temperature. But Ramanathan and his team have crafted a new transistor, made primarily of an oxide called samarium nickelate, that in practical operation achieves an on/off ratio of greater than 105—that is, comparable to state-of-the-art silicon transistors.

In future work the researchers will investigate the device’s switching dynamics and power dissipation; meanwhile, this advance represents an important proof of concept.

“Our orbital transistor could really push the frontiers of this field and say, you know what? This is a material that can challenge silicon,” Ramanathan says.

Solid-state chemical doping

Materials scientists have been studying the family of correlated oxides for years, but the field is still in its infancy, with most research aimed at establishing the materials’ basic physical properties.

“We have just discovered how to dope these materials, which is a foundational step in the use of any semiconductor,” says Ramanathan.

Doping is the process of introducing different atoms into the crystal structure of a material, and it affects how easily electrons can move through it—that is, to what extent it resists or conducts electricity. Doping typically effects this change by increasing the number of available electrons, but this study was different. The Harvard team manipulated the band gap, the energy barrier to electron flow.

“By a certain choice of dopants—in this case, hydrogen or lithium—we can widen or narrow the band gap in this material, deterministically moving electrons in and out of their orbitals,” Ramanathan says. That’s a fundamentally different approach than is used in other semiconductors. The traditional method changes the energy level to meet the target; the new method moves the target itself.

In this orbital transistor, protons and electrons move in or out of the samarium nickelate when an electric field is applied, regardless of temperature, so the device can be operated in the same conditions as conventional electronics. It is solid-state, meaning it involves no liquids, gases, or moving mechanical parts. And, in the absence of power, the material remembers its present state—an important feature for energy efficiency.

“That’s the beauty of this work,” says Ramanathan. “It’s an exotic effect, but in principle it’s highly compatible with traditional electronic devices.”

Quantum materials

Unlike silicon, samarium nickelate and other correlated oxides are quantum materials, meaning that quantum-mechanical interactions have a dominant influence over the material properties—and not just at small scales.

“If you have two electrons in adjacent orbitals, and the orbitals are not completely filled, in a traditional material the electrons can move from one orbital to another. But in the correlated oxides, the electrons repulse each other so much that they cannot move,” Ramanathan explains. “The occupancy of the orbitals and the ability of electrons to move in the crystal are very closely tied together—or ‘correlated.’ Fundamentally, that’s what dictates whether the material behaves as an insulator or a metal.”

Ramanathan and others at SEAS have successfully manipulated the metal-insulator transition in vanadium oxide, too. In 2012, they demonstrated a tunable device that can absorb 99.75% of infrared light, appearing black to infrared cameras.

Similarly, samarium nickelate is likely to catch the attention of applied physicists developing photonic and optoelectronic devices.

“Opening and closing the band gap means you can now manipulate the ways in which electromagnetic radiation interacts with your material,” says Jian Shi, lead author of the paper in Nature Communications. He completed the research as a postdoctoral fellow in Ramanathan’s lab at Harvard SEAS and joined the faculty of Rensselaer Polytechnic Institute this fall. “Just by applying an electric field, you’re dynamically controlling how light interacts with this material.”

Further ahead, researchers at the Center for Integrated Quantum Materials, established at Harvard in 2013 through a grant from the National Science Foundation, aim to develop an entirely new class of quantum electronic devices and systems that will transform signal processing and computation.

Ramanathan compares the current state of quantum materials research to the 1950s, when transistors were newly invented and physicists were still making sense of them. “We are basically in that era for these new quantum materials,” he says. “This is an exciting time to think about establishing the basic, fundamental properties. In the coming decade or so, this could really mature into a very exciting device platform.”

You Zhou, a graduate student at Harvard SEAS, was co-lead author of the paper in Nature Communications. The research was supported by grants from the National Science Foundation (NSF) (CCF-0926148) and the National Academy of Sciences, as well as an NSF Faculty Early Career Development (CAREER) Award to Prof. Ramanathan (DMR-0952794).

Rudolph Technologies has introduced its new SONUS Technology for measuring thick films and film stacks used in copper pillar bumps and for detecting defects, such as voids, in through silicon vias (TSVs). Copper pillar bumps are a critical component of many advanced packaging technologies and TSVs provide a means for signals to pass through multiple vertically stacked chips in three dimensional integrated circuits (3DIC). The new SONUS Technology is non-contact and non-destructive, and is designed to provide faster, less costly measurements and greater sensitivity to smaller defects than existing alternatives such as X-ray tomography and acoustic microscopy.

“SONUS Technology meets a critical need for measuring and inspecting the structures used to connect chips to each other and to the outside world,” said Tim Kryman, Rudolph’s director of metrology product management. “Copper pillar bumps and TSVs are critical interconnect technologies enabling 2.5D and 3D packaging. The mechanical integrity of the interconnect and final device performance are directly dependent on tight control of the plating processes used to create copper pillar bumps. Likewise, the quality of the TSV fill is critical to the electrical performance of stacked devices. This new technology allows us to measure individual films and film stacks with thicknesses up to 100µm, and detect voids as small as 0.5µm in TSVs with aspect ratios of 10:1 or greater.”

Kryman added, “SONUS Technology builds on the expertise we developed in acoustic metrology for our industry-standard MetaPULSE systems, which are widely used for front-end metal film metrology. By offering similar improvements in yield and time-to-profitability in high volume manufacturing (HVM), SONUS offers a compelling value proposition to advanced packaging customers.”

Both MetaPULSE and SONUS systems use a laser to initiate an acoustic disturbance at the surface of the sample. As the acoustic wave travels down through the film stack, it is partially reflected at interfaces between different materials. Although the detection schemes are different, the reflected waves are detected when they return to the surface and the elapsed time is used to calculate the thickness of each layer. In the case of SONUS Technology, two lasers are used. The first laser excites the sample and the second probes for the returning acoustics. This decouples excitation and detection allowing SONUS to continuously probe the sample resulting in a much larger film thickness range. So, where MetaPULSE can measure metal films and stacks to ~10 microns, SONUS can measure films in excess of 100 microns. In addition, SONUS Technology’s use of interferometry to characterize the surface displacement provides a rich data set that can be analyzed to not only characterize film thickness, but perform defect detection.

The primary alternatives for such measurements are X-ray based tomographic analysis and acoustic microscopy. SONUS Technology’s ability to detect voids as small as half a micrometer is approximately twice as good as current X-ray techniques, which have a spatial resolution of about 1 micrometer. Acoustic microscopy can make similar measurements, but the sample must be immersed in water, which, though not strictly destructive, does effectively preclude the return of the sample to production. SONUS is both non-contact and non-destructive and is designed for R&D and high-volume manufacturing.

In the run up to the product introduction, Rudolph worked closely with TEL NEXX to develop SONUS-based process control for pillar bump and TSV plating processes. Arthur Keigler, chief technology officer of TEL NEXX, said, “We are attracted by the opportunity SONUS Technology offers our mutual customers in the advanced packaging market. The ability to measure multi-metal film stacks for Cu pillar, and then continue to use the same tool for TSV void detection offers immediate productivity and cost benefits to manufacturing and development groups alike.”

While Rudolph is initially focused on using the technology for copper pillar bump process metrology and TSV inspection, they are also investigating other applications, ranging from detecting film delamination to metrology and process control for MEMS fabrication processes.

Veeco Instruments Inc. announced today that its new Odyssey Ion Beam Deposition (IBD) Upgrade for the NEXUS IBD-LDD System has repeatedly produced photomask blanks with zero deposition defects larger than 70nm. This represents a significant milestone toward the manufacture of semiconductor devices with advanced extreme ultraviolet (EUV) lithography.

EUV mask blank defects are, as a practical matter, impossible to repair and can render a semiconductor device useless. Because of this, mask blank defects have been a key obstacle toward high volume manufacturing. Veeco’s low-defect Odyssey IBD technology clears the way for further EUV manufacturing advancements for semiconductor devices.

“EUV lithography brings chipmakers the ability to manufacture higher performing devices at lower cost compared to manufacturing methods which rely on multiple patterning steps,” said Ron Kool, Senior Vice President of EUV Product and Service Marketing at ASML. “As ASML is making steady progress preparing the scanner and light source for industrial high volume manufacturing, the readiness of the EUV industry, including mask blanks, is critically important to our customers. Veeco’s dedication to the Odyssey upgrade program, done in coordination with customers, consortia, and other industry stakeholders, is a model for EUV infrastructure advancements.”

Veeco IBD technology features extremely low particulate deposition and precise control of optical properties for single or multi-layer processes. These technology features are required for defect-free, high volume EUV manufacturing. Currently, all of the leading EUV mask blank manufacturers use the Veeco NEXUS IBD-LDD system.

“Veeco is committed to working with our customers and industry partners to advance the EUV roadmap and increase the output of defect-free mask blanks,” said Jim Northup, Senior Vice President and General Manager of Veeco Advanced Deposition & Etch. “We have made significant investments in the Odyssey upgrade and consolidated our optical coating and ion beam resources in a single R&D site to ensure ongoing development of our IBD technology.”

Element Six today announced it has been selected by the European Commission’s Seventh Framework Programme for Research and Technological Development to help develop a new ultrafast pulse disk laser. The new laser will be designed with high average output power to increase productivity and precision in micromachining of transparent materials. As part of the three year project titled “Ultrafast High-Average Power Ti:Sapphire Thin-Disk Oscillators and Amplifiers” (TiSa:TD), Element Six will further develop its low-loss, high purity single crystal chemical vapor deposition (CVD) diamond material to rapidly conduct heat off a titanium sapphire (TiSa) thin-disk, which will be used as the laser gain material. These developments will include increasing the areas available to Element Six customers.

Currently, the most powerful industrial “ultrafast” lasers operate in the picosecond range, which offers sufficient performance for micromachining metals. However, the consortium aims to develop a new femtosecond laser system that allows extremely high precision with higher powers than previously achieved, in order to increase productivity for the micromachining of transparent materials such as glass and ceramics, commonly used in smartphones and tablets. Specifically, collaborators on this project are working to design two high-average power ultrafast TiSa thin-disk laser systems, one amplifier system using chirped pulses to obtain high-energy pulses, and one high-power oscillator to achieve high repetition rates. Both will have a maximum average output power of at least 200 W at a pulse duration of well below 100 femtoseconds.

To achieve these goals, TiSa will be used as the laser crystal material, which is optimal for short pulse laser systems due to the broad bandwidth of its emission, yet lacks good thermal properties. To combat this challenge, Element Six will further develop its single crystal CVD diamond to be mounted to the TiSa as a heat spreader, improving its thermo-optical effects and allowing it to be pumped at the required higher powers.

“The low-loss single crystal CVD diamond material produced by Element Six offers a unique combination of properties—including the highest room temperature thermal conductivity of any bulk material—allowing it to be used as a transparent heat spreader inside the resonator of high-power thin-disk lasers, generating heat flow densities that cannot be handled with other materials,” said the project lead, Dr. Andreas Voss of the Universität Stuttgart, in Germany.

While Element Six’s CVD diamond already has a thermal conductivity of up to 2200 W/mK as well as low birefringence and absorption rate, for this laser system application to be successful, further reductions in absorption coefficient of the CVD diamond and an increase in available area will be needed. “To date, our CVD diamond material has been leveraged for a range of commercial solid state laser systems with great success demonstrating unparalleled levels of heat extraction—enabling laser systems to operate at higher powers with improved beam quality,” said Adrian Wilson, director of the technologies group at Element Six. “For TiSa thin-disk, we have been called upon to further improve our existing crystal CVD diamond, extracting additional value—and we are determined to meet expectations.”

Efforts on TiSa thin-disk began in December 2013, and the project was recently granted € 3.1 million by the European Commission’s Seventh Framework Programme for Research and Technological Development. Other partners collaborating on TiSa thin-disk include the University of Stuttgart, the Centre National de la Recherche Scientifique, Thales Optronique, Oxford Lasers and M-Squared Lasers.

Beautiful, brilliant people


September 10, 2014

BY PETE SINGER, Editor-in-Chief

It would be difficult to overstate how critical the development of a workable, high volume manufacturing EUV lithography solution is to the semiconductor industry. It is no doubt why Intel, TSMC and Samsung invested billions in ASML in 2012, and why ASML acquired Cymer in 2013.

Progress has been slower than hoped, and many are questioning if it will be ready for the 10nm generation, which is slated to go into production in late 2015/early 2016. The cover story this month looks at alternatives, including mutli e-beam and directed self-assembly.

A push to 3D devices, such as the vertical NAND, make continued scaling possible while lessening the lithography (although new challenges are created for deposition and etch technologies). The good news is that it’s possible to get to 10nm and even 7nm without EUV using multi-patterning. The only question is if it will be cost effective to do so.

Earlier this year, at the SEMI Northeast Forum held in Billerica, MA, Patrick Martin, Senior Technology Director at Applied Materials described EUV as a “huge challenge” but then noted that “beautiful, brilliant people are working on this. He said “a thousand people at Cymer spend their life trying to make this work.”

“A thousand people at Cymer spend their life trying to make this work.”

I thought this was an interesting insight. It’s too easy to only look at the myriad of technology challenges that exist in something complex as EUV and think it’s not workable. But if we consider the human factor and that so many people are dedicating their lives to make it work (not to mention the billions of dollars at stake), it suddenly seems very achievable.

One EUV proponent is our blogger Vivek Bakshi, who runs regular workshops on EUV. In August, he reported on some recent good news announced by IBM showing good results using the ASML EUV tool at the Albany Nanotech center. What was a little sad was how many negative comments were made. I suppose with something as critically important as EUV, it’s to be expected that emotions will run high. But let’s not forget those beautiful, brilliant people that are spending their days trying to make it work.

This editorial originally appeared in the September 2014 issue of Solid State Technology.