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You can’t fix what you can’t find. You can’t control what you can’t measure. 

BY DAVID W. PRICE and DOUGLAS G. SUTHERLAND

This is the first in a series of 10 installments which will discuss fundamental truths about process control—inspection and metrology—for the semiconductor industry. By fundamental, we imply the following:

  • Unassailable: They are self-evident, can be proven from first principles, or are supported by the dominant behavior at fabs worldwide
  • Unchanging: these concepts are equally true today for 28nm as they were 15 years ago for 0.25μm, and are expected to hold true in the future
  • Universal: They are not unique to a specific segment of process control; rather they apply to process control as a group, as well as to each individual component of process control within the fab

Each article in this series will introduce one of the 10 fundamental truths and discuss interesting applications of these truths to semiconductor IC fabs. Given the increasing complexity of advanced devices and process integration, process control is growing in importance. By understanding the fundamental nature of process control, fabs can better implement strategies to identify critical defects, find excursions, and reduce sources of variation.

The first fundamental truth of process control for the semiconductor IC industry is:

You can’t fix what you can’t find. You can’t control what you can’t measure.

While it’s true that inspection and metrology systems are not used to make IC devices—they do not add or remove materials or create patterns—they are critical for making high-yielding, reliable devices. By finding defects and measuring critical parameters, inspection and metrology systems monitor the hundreds of steps required to manufacture a device, ensuring the processes meet strict manufacturing specifications and helping fab engineers identify and troubleshoot process issues when there is an excursion. Without inspection and metrology, it would be near impossible for fabs to pinpoint process issues that affect yield. However, it’s not enough to simply “find” and “measure” — a fab’s process control strategy needs to be capable and cost-effective.

Capable inspection and metrology strategies find and measure the defects and parameters that affect device yield. Cost-effective inspection and metrology is performed at the lowest total cost to the factory, where total cost is the sum of the cost of lost yield plus the cost of process control.

First, make it capable

If you can’t find it, you can’t fix it. At the heart of this truth is the understanding that, above all else, a fab’s inspection and metrology strategy must be capable. It must highlight the problems that are limiting baseline yield. It must also provide actionable information that can enable fabs to quickly find and fix excursions (FIGURE 1).

We emphasize this need for capability first because we have observed that some fabs are too quick tosacrifice capability for cost reductions. No strategy is cost-effective if it doesn’t accomplish its fundamental objective.

Below are specific questions that can help fab management evaluate the capability of its process control strategy:

  • Are you finding all sources of your defect-limited yield? Are you finding these in-line or at end-of-line?
  • Does your defect Pareto have sufficient resolution of the top yield-limiters in each module to direct the most appropriate use of factory engineering resources?
  • Have you fully characterized all of the important measurements and defect types (size range, kill ratio, root cause, solution)?
  • Do you understand the most probable incursion scenarios? What is the smallest excursion that you absolutely must detect at this step? How many lots are you willing to have exposed to this excursion before it is detected?
  • Are you inspecting and measuring at all the right steps? Can you quickly isolate the point of formation for excursions? Can you quickly disposition potentially affected lots?
  • Does a particular defect signature become confused by defects added at subsequent process steps? Or do you need separate inspections at each step in order to partition the problem? 
  • Do you have overlapping inspections to guard against the high-frequency, high-impact excursions?
  • What is the alpha risk and beta risk for each inspection or measurement? How are these related to the capture rate, accuracy, precision, matching and more?

Process control Fig 1b Process control fig 1a

 

FIGURE 1. You can’t fix what you can’t find. And you can’t control what you can’t measure. Left: P-MOS SiGe critical dimension measurement. Right: Fin patterning particle leading to a Fin Spire defect at post dummy gate etch. Source: KLA-Tencor

Then, make it cost-effective

Once a capable strategy is in place, then a fab can start the process of making it cost-effective. The best known method for optimizing total cost is usually adjusting the overall lot sampling rate. This is generally preferred because the capability remains constant.

In some cases, it may be possible to migrate to a less sensitive inspection (lower cost of ownership tool or larger pixel size); however, this is a dangerous path because it re-introduces uncertainty (alpha/beta risk) that reduces a fab’s process control capability. This concept will be discussed in more detail in our next article on sampling strategies.

Finally, it is worth pointing out that it is not enough to implement a capable strategy. The fab must ensure that what was once a capable strategy, stays a capable strategy. A fab cannot measure with a broken inspection tool or trust a poorly maintained inspection tool. Therefore, most fabs have programs in place to maintain and monitor the ongoing performance of their inspection and metrology tools.

By optimizing process control strategy to be capable and cost-effective, fabs ultimately find what needs to be fixed and measure what should be controlled—driving higher yield and better profitability.

Ziptronix Inc. today announced that its Direct Bond Interconnect (DBI) hybrid bonding has been implemented by Fermi National Accelerator Laboratory (Fermilab) to improve the performance of high-end 3D sensor arrays, which are used for particle detection in large-scale particle physics and x-ray imaging experiments. This is an example of three-layer DBI hybrid bonding in a 3D imaging chip, using DBI wafer-to-wafer and die-to-wafer processes.

The demonstrator, a vertically integrated x-ray photon imaging chip (VIPIC) detector, was developed by a collaboration of scientists and engineers from Fermilab, Brookhaven National Laboratory and AGH University from Poland. DBI hybrid bonding technology enables versatile new designs for pixelated radiation detectors. Fermilab and Brookhaven are national laboratories funded by the U.S. Department of Energy.

“Implementing DBI hybrid bonding enables us to design sophisticated combinations of sensors and readout electronics,” said Ron Lipton, Staff Scientist, Fermilab. “By enabling vertical signals through stacked sensor, readout and processing layers, we can design large-scale arrays that are side-edge buttable with high fill factor.”

The process flow for manufacturing the VIPIC involves using wafer-to-wafer DBI hybrid bonding to bond two ASIC wafers containing through silicon vias (TSVs). The bonded wafer pair is thinned to expose the TSVs on one side, then singulated. The singulated die stacks are then bonded to an x-ray sensor wafer using die-to-wafer DBI hybrid bonding. Subsequent thinning of the other side of the bonded wafer pair allows backside connections to the 3-layer assembly.

“This is an advanced three-layer imaging chip manufactured using DBI hybrid bonding,” said Paul Enquist, CTO, Ziptronix. “Electrical data shows that this approach achieves lower noise, higher bandwidth and higher gain due to lower capacitive load when compared with parts stacked using bumping. This increases the sensitivity of the 3D image sensors, making them ideal for use in high-end applications.”

DBI hybrid bonding is a conductor/dielectric bonding technology that includes a variety of metal/oxide/nitride combinations, uses no adhesives and is CMOS foundry compatible. It allows for stronger bonds and finer-pitch interconnect over traditional thermocompression bonding since bonding occurs at both the conductive and dielectric materials, versus just the conductor. Bonding therefore takes place over the entire surface area, eliminating the need for underfill as well as significantly reducing the overall height of the structure.

GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, today announced the “GLOBALFOUNDRIES Undergraduate Research Scholarship,” a new scholarship recognizing and rewarding aspiring, leadership-oriented engineering students interested in careers in the semiconductor industry.  The GLOBALFOUNDRIES Undergraduate Research Scholarship will fund undergraduate research opportunities (URO) and intern scholars through the Semiconductor Research Corporation’s (SRC) Education Alliance.

Presented at SRC’s annual TECHCON conference in Austin, Texas, the scholarship was created by GLOBALFOUNDRIES in partnership with SRC to recognize and reward science, technology and engineering students who demonstrate promise in their academic and professional efforts. The selected recipients of this scholarship will have the opportunity to interact with GLOBALFOUNDRIES researchers and access the professional resources of SRC and the SRC Education Alliance.

“Building a pipeline of highly skilled talent is essential to our business and to the competitiveness of the entire semiconductor industry,” said Suresh Venkatesan, senior vice president of technology development, GLOBALFOUNDRIES.  “SRC connects companies with the top universities, which results in exciting research and educational opportunities for the best and the brightest students. The GLOBALFOUNDRIES Undergraduate Research Scholarship gives us the opportunity to support science, technology, engineering and mathematics education and help develop the technical leaders who will continue to drive innovation in the semiconductor industry in the future.”

Until recently, SRC focused exclusively on students seeking advanced degrees, providing fellowships for them to do university research that had practical applications for corporate members of its unique consortium. The URO is SRC’s innovative program providing undergraduates with valuable research experience and mentoring. The goal of the URO is to empower bright, well-educated, and experienced scientists and engineers for which U.S. high-tech companies are seeking.

“Recognizing the critical importance of a strong pipeline of new talent for the semiconductor industry, the SRC Education Alliance through the URO Program provides financial assistance to undergraduates, allowing students and universities to recognize the connections between the materials they are learning in the classroom and the technological innovations that transform the world,” said SRC President Larry Sumney. “We are thrilled to collaborate with GLOBALFOUNDRIES as we continue to develop our URO program.”

Rising sophomores, juniors and seniors in an accredited undergraduate program majoring in the field of engineering are encouraged to apply.  Additional information about the scholarship can be obtained by visiting: www.src.org/program/srcea/uro/globalfoundries.

Every year, TECHCON brings together the brightest minds in microelectronics research to exchange news about the progress of new materials and processes created by SRC’s network of more than 100 of the top engineering universities. Students and industry leaders discuss basic research that is intended to accelerate advancements for both private and public entities.

Graphene is a semiconductor when prepared as an ultra-narrow ribbon – although the material is actually a conductive material. Researchers from Empa and the Max Planck Institute for Polymer Research have now developed a new method to selectively dope graphene molecules with nitrogen atoms. By seamlessly stringing together doped and undoped graphene pieces, they were able to form ”heterojunctions” in the nanoribbons, thereby fulfilling a basic requirement for electronic current to flow in only one direction when voltage is applied – the first step towards a graphene transistor. Furthermore, the team has successfully managed to remove graphene nanoribbons from the gold substrate on which they were grown and to transfer them onto a non-conductive material.

Graphene possesses many outstanding properties: it conducts heat and electricity, it is transparent, harder than diamond and extremely strong. But in order to use it to construct electronic switches, a material must not only be an outstanding conductor, it should also be switchable between ”on” and ”off” states. This requires the presence of a so-called bandgap, which enables semiconductors to be in an insulating state. The problem, however, is that the bandgap in graphene is extremely small. Empa researchers from the ”nanotech@surfaces” laboratory thus developed a method some time ago to synthesise a form of graphene with larger bandgaps by allowing ultra-narrow graphene nanoribbons to ”grow” via molecular self-assembly.

Graphene nanoribbons made of differently doped segments

The researchers, led by Roman Fasel, have now achieved a new milestone by allowing graphene nanoribbons consisting of differently doped subsegments to grow. Instead of always using the same ”pure” carbon molecules, they used additionally doped molecules – molecules provided with ”foreign atoms” in precisely defined positions, in this case nitrogen. By stringing together ”normal” segments with nitrogen-doped segments on a gold (Au (111)) surface, so-called heterojunctions are created between the individual segments. The researchers have shown that these display similar properties to those of a classic p-n-junction, i.e. a junction featuring both positive and negative charges across different regions of the semiconductor crystal, thereby creating the basic structure allowing the development of many components used in the semiconductor industry. A p-n junction causes current to flow in only one direction. Because of the sharp transition at the heterojunction interface, the new structure also allows electron/hole pairs to be efficiently separated when an external voltage is applied, as demonstrated theoretically by theorists at Empa and collaborators at Rensselaer Polytechnic Institute The latter has a direct impact on the power yield of solar cells. The researchers describe the corresponding heterojunctions in segmented graphene nanoribbons in the recently published issue of “Nature Nanotechnology.”

Transferring graphene nanoribbons onto other substrates

In addition, the scientists have solved another key issue for the integration of graphene nanotechnology into conventional semiconductor industry: how to transfer the ultra-narrow graphene ribbons onto another surface? As long as the graphene nanoribbons remain on a metal substrate (such as gold used here) they cannot be used as electronic switches. Gold conducts and thus creates a short-circuit that “sabotages” the appealing semiconducting properties of the graphene ribbon. Fasel’s team and colleagues at the Max-Planck-Institute for Polymer Research in Mainz have succeeded in showing that graphene nanoribbons can be transferred efficiently and intact using a relatively simple etching and cleaning process onto (virtually) any substrate, for example onto sapphire, calcium fluoride or silicon oxide.

Graphene is thus increasingly emerging as an interesting semiconductor material and a welcome addition to the omnipresent silicon. The semiconducting graphene nanoribbons are particularly attractive as they allow smaller and thus more energy efficient and faster electronic components than silicon. However, the generalized use of graphene nanoribbons in the electronics sector is not anticipated in the near future, due in part to scaling issues and in part to the difficulty of replacing well-established conventional silicon-based electronics. Fasel estimates that it may still take about 10 to 15 years before the first electronic switch made of graphene nanoribbons can be used in a product.

Graphene nanoribbons for photovoltaic components

Photovoltaic components could also one day be based on graphene. In a second paper published in Nature Communications, Pascal Ruffieux – also from the Empa “nanotech@surfaces” laboratory – and his colleagues describe a possible use of graphene strips, for instance in solar cells. Ruffieux and his team have noticed that particularly narrow graphene nanoribbons absorb visible light exceptionally well and are therefore highly suitable for use as the absorber layer in organic solar cells. Compared to “normal” graphene, which absorbs light equally at all wavelengths, the light absorption in graphene nanoribbons can be increased enormously in a controlled way, whereby researchers “set” the width of the graphene nanoribbons with atomic precision.

Sandwiching layers of graphene with white graphene could produce designer materials capable of creating high-frequency electronic devices, University of Manchester scientists have found. The researchers have demonstrated how combining the two-dimensional materials in a stack could create perfect crystals capable of being used in next generation transistors.

Hexagonal boron nitride (hBN), otherwise known as white graphene, is one of a family of two-dimension materials discovered in the wake of the isolation of graphene at the University in 2004. Manchester researchers have previously demonstrated how combining 2D materials, in stacks called heterostructures, could lead to materials capable of being designed to meet industrial demands.

Now, for the first time, the team has demonstrated that the electronic behaviour of the heterostructures can be changed enormously by precisely controlling the orientation of the crystalline layers within the stacks.

The researchers, led by University of Manchester Nobel laureate Sir Kostya Novoselov, carefully aligned two graphene electrodes separated by hBN and discovered there was a conservation of electron energy and momentum.

The findings could pave the way for devices with ultra-high frequencies, such as electronic or photovoltaic sensors.

The research was carried out with scientists from Lancaster and Nottingham Universities in the UK, and colleagues in Russia, Seoul and Japan.

Professor Laurence Eaves, a joint academic from the Universities of Manchester and Nottingham, said: “”This research arises from a beautiful combination of classical laws of motion and the quantum wave nature of electrons, which enables them to flow through barriers

“We are optimistic that further improvements to the device design will lead to applications in high-frequency electronics.”

Professor Vladimir Falko, from Lancaster University, added: “Our observation of tunnelling and negative differential conductance in devices made of multilayers of graphene and hexagonal boron nitride demonstrates potential that this system has for electronics applications.

“It is now up to material growers to find ways to produce such multilayer systems using growth techniques rather than mechanical transfer method used in this work.”

Sidense Corp., a developer of non-volatile memory OTP IP cores, today announced that it successfully demonstrated read and write capability for its 1T-OTP bit-cell architecture on test silicon fabricated in a 16nm CMOS FinFET process.

“Sidense’s embedded one-time programmable memory macros have been licensed in customers’ designs from 0.18-micron down to 28nm and have been proven at the 20nm process node as well,” said Wlodek Kurjanowicz, Sidense Founder and CTO. “Our split-channel 1T-OTP macros were designed to be highly scalable with shrinking process nodes. It is gratifying to see our theories proven in new transistor architectures such as FinFET.”

The 3D 16nm FinFET architecture provides higher performance, lower dynamic power and smaller transistor geometries than standard transistors at 20nm, the latter benefit allowing designers to put more functions on a silicon chip. More importantly FinFETs eliminate short-channel effects and the subsequent high leakage currents that limit device scalability of traditional planar transistors. These attributes make devices designed with FinFETs very attractive for market segments that require high performance and minimum power dissipation, such as mobile computing, communications and high-end processor nodes on IoT networks.

Preliminary test results at 16nm confirm correct bit-cell operation with a programming voltage comparable to Sidense 1T-OTP at 28nm with 10X lower leakage current. Programmed bit-cell characteristics are as good as or better than those for 20nm and 28nm bit cells with very large margins between programmed and un-programmed cells and with excellent post-bake bit-cell stability.

“With its enhanced speed performance and reduced power dissipation, TSMC’s 16nm technology is an excellent choice for mobile device chip designs,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “NVM is now, and will continue to be, a key component in mobile devices, and it is encouraging to see good initial test results on Sidense OTP devices at this process node.”

Move over, graphene. An atomically thin, two-dimensional, ultrasensitive semiconductor material for biosensing developed by researchers at UC Santa Barbara promises to push the boundaries of biosensing technology in many fields, from health care to environmental protection to forensic industries.

Based on molybdenum disulfide or molybdenite (MoS2), the biosensor material — used commonly as a dry lubricant — surpasses graphene’s already high sensitivity, offers better scalability and lends itself to high-volume manufacturing. Results of the researchers’ study have been published in ACS Nano.

Concept art of a molybdenum disulfide field-effect transistor based biosensor demonstrated by UCSB researchers with ability to detect ultra-low (femtomolar) concentrations with high sensitivity that is 74-fold higher than that of graphene FET biosensors. - Photo Credit: Peter Allen

Concept art of a molybdenum disulfide field-effect transistor based biosensor demonstrated by UCSB researchers with ability to detect ultra-low (femtomolar) concentrations with high sensitivity that is 74-fold higher than that of graphene FET biosensors. – Photo Credit: Peter Allen

“This invention has established the foundation for a new generation of ultrasensitive and low-cost biosensors that can eventually allow single-molecule detection — the holy grail of diagnostics and bioengineering research,” said Samir Mitragotri, co-author and professor of chemical engineering and director of the Center for Bioengineering at UCSB. “Detection and diagnostics are a key area of bioengineering research at UCSB and this study represents an excellent example of UCSB’s multifaceted competencies in this exciting field.”

The key, according to UCSB professor of electrical and computer engineering Kaustav Banerjee, who led this research, is MoS2’s band gap, the characteristic of a material that determines its electrical conductivity.

Semiconductor materials have a small but nonzero band gap and can be switched between conductive and insulated states controllably. The larger the band gap, the better its ability to switch states and to insulate leakage current in an insulated state. MoS2’s wide band gap allows current to travel but also prevents leakage and results in more sensitive and accurate readings.

The limitations of graphene

While graphene has attracted wide interest as a biosensor due to its two-dimensional nature that allows excellent electrostatic control of the transistor channel by the gate, and high surface-to-volume ratio, the sensitivity of a graphene field-effect transistor (FET) biosensor is fundamentally restricted by the zero band gap of graphene that results in increased leakage current, leading to reduced sensitivity, explained Banerjee, who is also the director of the Nanoelectronics Research Lab at UCSB.

Graphene has been used, among other things, to design FETs — devices that regulate the flow of electrons through a channel via a vertical electric field directed into the channel by a terminal called a “gate.” In digital electronics, these transistors control the flow of electricity throughout an integrated circuit and allow for amplification and switching.

In the realm of biosensing, the physical gate is removed, and the current in the channel is modulated by the binding between embedded receptor molecules and the charged target biomolecules to which they are exposed. Graphene has received wide interest in the biosensing field and has been used to line the channel and act as a sensing element whose surface potential (or conductivity) can be modulated by the interaction (known as conjugation) between the receptor and target molecules that results in net accumulation of charges over the gate region.

However, said the research team, despite graphene’s excellent characteristics, its performance is limited by its zero band gap. Electrons travel freely across a graphene FET — hence, it cannot be “switched off” — which in this case results in current leakages and higher potential for inaccuracies.

Much research in the graphene community has been devoted to compensating for this deficiency, either by patterning graphene to make nanoribbons or by introducing defects in the graphene layer — or using bilayer graphene stacked in a certain pattern that allows band gap opening upon application of a vertical electric field — for better control and detection of current.

Enter MoS2, a material already making waves in the semiconductor world for the similarities it shares with graphene, including its atomically thin hexagonal structure, and planar nature, as well as what it can do that graphene can’t: act like a semiconductor.

“Monolayer or few-layer MoS2 have a key advantage over graphene for designing an FET biosensor: They have a relatively large and uniform band gap (1.2-1.8 eV, depending on the number of layers) that significantly reduces the leakage current and increases the abruptness of the turn-on behavior of the FETs, thereby increasing the sensitivity of the biosensor,” said Banerjee.

‘The best of everything’

Additionally, according to Deblina Sarkar, a PhD student in Banerjee’s lab and the lead author of the article, two-dimensional MoS2 is relatively simple to manufacture.

“While one-dimensional materials such as carbon nanotubes and nanowires also allow excellent electrostatics and at the same time possess band gap, they are not suitable for low-cost mass production due to their process complexities,” she said. “Moreover, the channel length of MoS2 FET biosensor can be scaled down to the dimensions similar to those of small biomolecules such as DNA or small proteins, still maintaining good electrostatics, which can lead to high sensitivity even for detection of single quanta of these biomolecular species,” she added.

“In fact, atomically thin MoS2 provides the best of everything: great electrostatics due to their ultra-thin body, scalability (due to large band gap), as well as patternability due to their planar nature that is essential for high-volume manufacturing,” said Banerjee.

The MoS2 biosensors demonstrated by the UCSB team have already provided ultrasensitive and specific protein sensing with a sensitivity of 196 even at 100 femtomolar (a billionth of a millionth of a mole) concentrations. This protein concentration is similar to one drop of milk dissolved in a hundred tons of water. An MoS2-based pH sensor achieving sensitivity as high as 713 for a pH change by one unit along with efficient operation over a wide pH range (3-9) is also demonstrated in the same work.

“This transformative technology enables highly specific, low-power, high-throughput physiological sensing that can be multiplexed to detect a number of significant, disease-specific factors in real time,” commented Scott Hammond, executive director of UCSB’s Translational Medicine Research Laboratories.

Biosensors based on conventional FETs have been gaining momentum as a viable technology for the medical, forensic and security industries since they are cost-effective compared to optical detection procedures. Such biosensors allow for scalability and label-free detection of biomolecules — removing the step and expense of labeling target molecules with florescent dye. “In essence,” continued Hammond, “the promise of true evidence-based, personalized medicine is finally becoming reality.”

“This demonstration is quite remarkable,” said Andras Kis, professor at École Polytechnique Fédérale de Lausanne in Switzerland and a leading scientist in the field of 2D materials and devices.

“At present, the scientific community worldwide is actively seeking practical applications of 2D semiconductor materials such as MoS2 nanosheets. Professor Banerjee and his team have identified a breakthrough application of these nanomaterials and provided new impetus for the development of low-power and low-cost ultrasensitive biosensors,” continued Kis, who is not connected to the project.

Wei Liu and Xuejun Xie from UCSB’s Department of Electrical and Computer Engineering and Aaron Anselmo from the Department of Chemical Engineering also conducted research for this study. Research on this project was supported by the National Science Foundation, the California NanoSystems Institute at UCSB and the Materials Research Laboratory at UCSB, a National Science Foundation MRSEC.

Contour Semiconductor, Inc., a developer of non-volatile memory technologies, today announced it has been awarded three new patents to back its Diode Transistor Memory (DTM) technology, the world’s lowest production-cost, non-volatile memory technology.The three new patents recognize Contour’s achievements in the field of low-mask count/reduced process step memory, and bring the company’s total issued patents to 45.

The new patents focus on better and more cost effective approaches to phase-change and resistive non-volatile memory, 3D memory, and embedded memory applications – concepts that are “top of the list” for memory manufacturers and their customers.

“Contour’s patent portfolio seeks to return Moore’s Law to the non-volatile discussion, and enable the next big thing,” said Contour CEO Saul Zales. “DTM technology will overcome production and CapEx challenges that stymie NAND manufacturers, and deliver significant technical advantages over traditional NAND flash memory, to support emerging and future technologies like wearables, Internet connected devices and the Internet of Things.”

Contour estimates the production cost of its DTM to be 60-65 percent lower than today’s NAND memory, while maintaining or improving on NAND’s performance and endurance.

NAND is currently used in a wide range of products from digital photography to smartphones and solid-state drives. However, in recent years, the high costs associated with production tools and fabrication facilities have slowed NAND bit growth rate from 70-80 percent to 25-30 percent annually.

ProPlus Design Solutions, Inc. today announced Samsung Electronics has extended its partnership with ProPlus through the deployment of ProPlus’ BSIMProPlus modeling platform for its 14nanometer (nm) FinFET SPICE modeling.

Additionally, Samsung has adopted the 9812D system, the latest generation 1/f noise characterization system, for advanced node process technology development after being a user of 9812B, formerly the industry’s de facto standard 1/f measurement system.

ProPlus’ BSIMProPlus modeling solutions, the 20-year de facto golden modeling solution, has been used by Samsung for more than 15 years to generate SPICE models for its advanced process technologies, including Samsung’s 14nm FinFET technology offerings.

“Samsung has already completed 14LPE FinFET process qualification and started risk production,” remarks Dr. Steve Kwon, vice president of Design Service team at Samsung Electronics. “Based on successful collaboration with our ecosystem partners including ProPlus, we overcame technological challenges in 14nm FinFET technology, and are currently providing our customers with complete SPICE modeling support.”

As the global leader for SPICE modeling solutions and the leading technology provider for Design-for-Yield (DFY) applications, ProPlus provides advanced modeling solutions to all leading foundries and integrated device manufacturers (IDMs). With 20 years’ continuous investment, its BSIMProPlus modeling platform provides the most complete support for all mainstream and leading-edge technologies and is widely used for baseband, RF, noise, reliability, statistical and stress modeling in more than 100 semiconductor companies worldwide.

ProPlus launched 9812D in 2013 for low-frequency noise characterization and process quality monitoring at advanced nodes such as 28nm bulk CMOS, 14nm FinFET and beyond. 9812D offers the highest accuracy, true 10 megahertz (MHz) bandwidth for on-wafer measurement and greatly improved performance with its multiple low-noise amplifiers (LNAs), and a built-in dynamic signal analyzer (DSA) with multi-threaded processing.

“As a valued partner, Samsung has offered us invaluable feedback on our tools and technology roadmap,” comments Dr. Zhihong Liu, chairman and CEO of ProPlus Design Solutions. “As a result, we made a significant investment in BSIMProPlus, including increased performance and capability with a full parallel statistical SPICE engine we call NanoSpice.

“BSIMProPlus, with its full variation modeling capabilities, laid the foundation for ProPlus’ unique position and focus on DFY and support for advanced process nodes, such as FinFET,” adds Dr. Liu.

Spin-charge converters are important devices in spintronics, an electronic which is not only based on the charge of electrons but also on their spin and the spin-related magnetism. Spin-charge converters enable the transformation of electric into magnetic signals and vice versa. Recently, the research group of Professor Jairo Sinova from the Institute of Physics at Johannes Gutenberg University Mainz in collaboration with researchers from the UK, Prague, and Japan, has for the first time realised a new, efficient spin-charge converter based on the common semiconductor material GaAs.

Comparable efficiencies had so far only been observed in platinum, a heavy metal. In addition, the physicists demonstrated that the creation or detection efficiency of spin currents is electrically tunable in a certain regime. This is important when it comes to real devices. The underlying mechanism, that was revealed by theoretical works of the Sinova group, opens up a new approach in searching and engineering spintronic materials. These results have recently been published in the journal Nature Materials.

Spintronics does not only make use of the electron’s charge to transmit and store information but it takes also advantage of the electron’s spin. The spin can be regarded as a rotation of the electron around its own axis, and generates a magnetic field like a small magnet. In some materials, electron spins spontaneously align their direction, leading to the phenomenon of ferromagnetism which is well known e.g. in iron. Additionally, “spin-up” or “spin-down” directions can be used to represent two easily distinguishable states – 0 and 1 – used in information technology. This is already used for memory applications such as computer hard discs.

Making use of electron spin for information transmission and storage, enables the development of electronic devices with new functionalities and higher efficiency. To make real use of the electron spin, it has to be manipulated precisely: it has to be aligned, transmitted and detected. The work of Sinova and his colleagues shows, that it is possible to do so using electric fields rather than magnetic ones. Thus, the very efficient, simple and precise mechanisms of charge manipulation well established in semiconductor electronics can be transferred to the world of spintronic and thereby combine semiconductor physics with magnetism.

Spin-charge converters are essential tools for that. They can transform charge currents into spin currents, and vice versa. The main principle behind these converters is the so called spin-Hall effect. Jairo Sinova had already been involved in the prediction and discovery of this relativistic phenomenon in 2004.

The spin-Hall effect appears when an electric field drives electrons through a semiconductor plate. Taking a look at the classical Hall effect that is known from undergraduate physics, the interaction of moving electrons and an external magnetic field forces the electrons to move to one side of the plate, perpendicular to their original direction. This leads to the so called Hall voltage between both sides of the plate. For the spin-Hall effect electron-spins are generated by irradiating the sample with circularly polarised light. The electron spins are then parallel or antiparallel, and their direction is perpendicular to the plate and the direction of movement. The moving electron spins are now forced to one or the other side of the plate, depending on the spin orientation. The driving force behind this is the so called spin-orbit coupling, a relativistic electromagnetic effect which influences moving electron spins. This leads to the separation of both spin orientations.

To make practical use of this effect, it is essential to get a highly efficient spin separation. Up to now, platinum has been the most efficient spin-charge converter material, as it is a heavy metal, and the spin-orbit coupling of heavy metals is known to be especially strong due to the large amount of protons (positive charge) in their core.

Now, Sinova and his colleagues have shown that gallium-arsenide (GaAs), a very common and widely used semiconductor material, can be an as efficient spin-charge converter as platinum, even at room temperature, which is important for practical applications. Moreover, the physicists have demonstrated for the first time that the efficiency can be tuned continuously by varying the electric field that drives the electrons.

The reason for this – as theoretical calculations of the Sinova group have shown – lies in the existence of certain valleys in the conduction band of the semiconductor material. One can think of the conduction band and its valleys as of a motor highway with different lanes, each one requiring a certain minimum velocity. Applying a higher electric field enables a transition from one lane to the other.

Since the spin-orbit coupling is different in each lane, a transition also affects the strength of the spin-hall effect. By varying the electric field, the scientists can distribute the electron spins on the different lanes, thus varying the efficiency of their spin-charge converter.

By taking into account the valleys in the conduction band, Sinova and his colleagues open up new ways to find and engineer highly efficient materials for spintronics. Especially, since current semiconductor growth technologies are capable of engineering the energy levels of the valleys and the strength of spin-orbit coupling, e.g. by substituting Ga or As with other materials like Aluminum.