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Competition for graphene


August 27, 2014

A new argument has just been added to the growing case for graphene being bumped off its pedestal as the next big thing in the high-tech world by the two-dimensional semiconductors known as MX2 materials. An international collaboration of researchers led by a scientist with the U.S. Department of Energy (DOE)’s Lawrence Berkeley National Laboratory (Berkeley Lab) has reported the first experimental observation of ultrafast charge transfer in photo-excited MX2 materials. The recorded charge transfer time clocked in at under 50 femtoseconds, comparable to the fastest times recorded for organic photovoltaics.

Illustration of a MoS2/WS2 heterostructure with a MoS2 monolayer lying on top of a WS2 monolayer. Electrons and holes created by light are shown to separate into different layers. (Image courtesy of Feng Wang group)

Illustration of a MoS2/WS2 heterostructure with a MoS2 monolayer lying on top of a WS2 monolayer. Electrons and holes created by light are shown to separate into different layers. (Image courtesy of Feng Wang group)

“We’ve demonstrated, for the first time, efficient charge transfer in MX2 heterostructures through combined photoluminescence mapping and transient absorption measurements,” says Feng Wang, a condensed matter physicist with Berkeley Lab’s Materials Sciences Division and the University of California (UC) Berkeley’s Physics Department. “Having quantitatively determined charge transfer time to be less than 50 femtoseconds, our study suggests that MX2 heterostructures, with their remarkable electrical and optical properties and the rapid development of large-area synthesis, hold great promise for future photonic and optoelectronic applications.”

Wang is the corresponding author of a paper in Nature Nanotechnology describing this research. The paper is titled “Ultrafast charge transfer in atomically thin MoS2/WS2 heterostructures.” Co-authors are Xiaoping Hong, Jonghwan Kim, Su-Fei Shi, Yu Zhang, Chenhao Jin, Yinghui Sun, Sefaattin Tongay, Junqiao Wu and Yanfeng Zhang.

Feng Wang is a condensed matter physicist with Berkeley Lab’s Materials Sciences Division and UC Berkeley’s Physics Department. (Photo by Roy Kaltschmidt)

Feng Wang is a condensed matter physicist with Berkeley Lab’s Materials Sciences Division and UC Berkeley’s Physics Department. (Photo by Roy Kaltschmidt)

MX2 monolayers consist of a single layer of transition metal atoms, such as molybdenum (Mo) or tungsten (W), sandwiched between two layers of chalcogen atoms, such as sulfur (S). The resulting heterostructure is bound by the relatively weak intermolecular attraction known as the van der Waals force. These 2D semiconductors feature the same hexagonal “honeycombed” structure as graphene and superfast electrical conductance, but, unlike graphene, they have natural energy band-gaps. This facilitates their application in transistors and other electronic devices because, unlike graphene, their electrical conductance can be switched off.

“Combining different MX2 layers together allows one to control their physical properties,” says Wang, who is also an investigator with the Kavli Energy NanoSciences Institute (Kavli-ENSI). “For example, the combination of MoS2 and WS2 forms a type-II semiconductor that enables fast charge separation. The separation of photoexcited electrons and holes is essential for driving an electrical current in a photodetector or solar cell.”

In demonstrating the ultrafast charge separation capabilities of atomically thin samples of MoS2/WS2 heterostructures, Wang and his collaborators have opened up potentially rich new avenues, not only for photonics and optoelectronics, but also for photovoltaics.

“MX2 semiconductors have extremely strong optical absorption properties and compared with organic photovoltaic materials, have a crystalline structure and better electrical transport properties,” Wang says. “Factor in a femtosecond charge transfer rate and MX2 semiconductors provide an ideal way to spatially separate electrons and holes for electrical collection and utilization.”

Wang and his colleagues are studying the microscopic origins of  charge transfer in MX2 heterostructures and the variation in charge transfer rates between different MX2 materials.

“We’re also interested in controlling the charge transfer process with external electrical fields as a means of utilizing MX2 heterostructures in photovoltaic devices,” Wang says.

This research was supported by an Early Career Research Award from the DOE Office of Science through UC Berkeley, and by funding agencies in China through the Peking University in Beijing.

Scientists have developed what they believe is the thinnest-possible semiconductor, a new class of nanoscale materials made in sheets only three atoms thick.

As seen under an optical microscope, the heterostructures have a triangular shape. The two different monolayer semiconductors can be recognized through their different colors.

The University of Washington researchers have demonstrated that two of these single-layer semiconductor materials can be connected in an atomically seamless fashion known as a heterojunction. This result could be the basis for next-generation flexible and transparent computing, better light-emitting diodes, or LEDs, and solar technologies.

As seen under an optical microscope, the heterostructures have a triangular shape. The two different monolayer semiconductors can be recognized through their different colors. Photo credit: U of Washington

As seen under an optical microscope, the heterostructures have a triangular shape. The two different monolayer semiconductors can be recognized through their different colors. Photo credit: U of Washington

“Heterojunctions are fundamental elements of electronic and photonic devices,” said senior author Xiaodong Xu, a UW assistant professor of materials science and engineering and of physics. “Our experimental demonstration of such junctions between two-dimensional materials should enable new kinds of transistors, LEDs, nanolasers, and solar cells to be developed for highly integrated electronic and optical circuits within a single atomic plane.”

The research was published online this week in Nature Materials.

The researchers discovered that two flat semiconductor materials can be connected edge-to-edge with crystalline perfection. They worked with two single-layer, or monolayer, materials – molybdenum diselenide and tungsten diselenide – that have very similar structures, which was key to creating the composite two-dimensional semiconductor.

Collaborators from the electron microscopy center at the University of Warwick in England found that all the atoms in both materials formed a single honeycomb lattice structure, without any distortions or discontinuities. This provides the strongest possible link between two single-layer materials, necessary for flexible devices. Within the same family of materials it is feasible that researchers could bond other pairs together in the same way.

A high-resolution scanning transmission electron microscopy (STEM) image shows the lattice structure of the heterojunctions in atomic precision. Photo credit: U of Warwick

A high-resolution scanning transmission electron microscopy (STEM) image shows the lattice structure of the heterojunctions in atomic precision. Photo credit: U of Warwick

The researchers created the junctions in a small furnace at the UW. First, they inserted a powder mixture of the two materials into a chamber heated to 900 degrees Celsius (1,652 F). Hydrogen gas was then passed through the chamber and the evaporated atoms from one of the materials were carried toward a cooler region of the tube and deposited as single-layer crystals in the shape of triangles.

After a while, evaporated atoms from the second material then attached to the edges of the triangle to create a seamless semiconducting heterojunction.

“This is a scalable technique,” said Sanfeng Wu, a UW doctoral student in physics and one of the lead authors. “Because the materials have different properties, they evaporate and separate at different times automatically. The second material forms around the first triangle that just previously formed. That’s why these lattices are so beautifully connected.”

With a larger furnace, it would be possible to mass-produce sheets of these semiconductor heterostructures, the researchers said. On a small scale, it takes about five minutes to grow the crystals, with up to two hours of heating and cooling time.

“We are very excited about the new science and engineering opportunities provided by these novel structures,” said senior author David Cobden, a UW professor of physics. “In the future, combinations of two-dimensional materials may be integrated together in this way to form all kinds of interesting electronic structures such as in-plane quantum wells and quantum wires, superlattices, fully functioning transistors, and even complete electronic circuits.”

This photoluminescence intensity map shows a typical piece of the lateral heterostructures. The junction region produces an enhanced light emission, indicating its application potential in optoelectronics. Photo credit: U of Washington

This photoluminescence intensity map shows a typical piece of the lateral heterostructures. The junction region produces an enhanced light emission, indicating its application potential in optoelectronics. Photo credit: U of Washington

The researchers have already demonstrated that the junction interacts with light much more strongly than the rest of the monolayer, which is encouraging for optoelectric and photonic applications like solar cells.

Other co-authors are Chunming Huang and Pasqual Rivera of UW physics; Ana Sanchez, Richard Beanland and Jonathan Peters at the University of Warwick; Jason Ross of UW materials science and engineering; and Wang Yao, a theoretical physicist of the University of Hong Kong.

This research was funded by the U.S. Department of Energy, the UW’s Clean Energy Institute, the Research Grant Council of Hong Kong, the University Grants Committee of Hong Kong, the Croucher Foundation, the Science City Research Alliance and the Higher Education Funding Council for England’s Strategic Development Fund.

JEDEC Solid State Technology Association today announced the publication of JESD209-4 Low Power Double Data Rate 4 (LPDDR4). Designed to significantly boost memory speed and efficiency for mobile computing devices such as smartphones, tablets, and ultra-thin notebooks, LPDDR4 will eventually operate at an I/O rate of 4266 MT/s, twice that of LPDDR3. The new interface promises to have an enormous impact on the performance and capabilities of next-generation portable electronics. “LPDDR4 represents a dramatic performance increase,” said Mian Quddus, Chairman, JEDEC Board of Directors. “It is intended to meet the power, bandwidth, packaging, cost and compatibility requirements of the world’s most advanced mobile systems.” Developed by JEDEC’s JC-42.6 Subcommittee for Low Power Memories, the JESD209-4 LPDDR4 standard can be downloaded from the JEDEC website for free by clicking here.

The market for mobile computing continues to grow, and with it the demand for ever faster devices and ever longer operation on a single charge. LPDDR4 launches with an I/O data rate of 3200 MT/s and a target speed of 4266 MT/s, compared to 2133 MT/s for LPDDR3. To achieve this performance, the members of the committee had to completely redesign the architecture, going from a one-channel die with 16 bits per channel to a two-channel die with 16 bits per channel, for a total of 32 bits.

“LPDDR3 was an evolutionary change from LPDDR2. With LPDDR4, the architecture is completely different,” said Hung Vuong, Chairman of JC-42.6. “We knew the only way to achieve the performance that the industry required was to make a total departure from previous generations.” The two-channel architecture reduces the distance data signals must travel from the memory array to the I/O bond pads. This reduces the power required to transmit the large amount of data the LPDDR4 interface requires. Because most of the area of a memory device is taken up by the memory array, doubling the interface area has a minimal impact on the overall footprint.

The two-channel architecture also allows the clock and address bus to be grouped together with the data bus. Thus, the skew between data bus to the clock and address bus is minimized, allowing the LPDDR4 device to reach a higher data rate. This saves power and improves timing margins compared to the LPDDR3 architecture.

A new approach to signaling

Recognizing that extending the LPDDR3 interface to higher frequencies would consume too much power, the JEDEC committee decided to implement a significant change in LPDDR4’s I/O signaling to low-voltage swing-terminated logic (LVSTL). LPDDR4’s LVSTL I/O signaling voltage of 367 or 440mV is less than 50% the I/O voltage swing of LPDDR3. This reduces power while enabling high-frequency operation. In addition, by using Vssq termination and data bus inversion (DBI), termination power can be minimized since any I/O signal driving a “0” consumes no termination power.

Several other steps were taken to save power. The operating voltage was reduced from the 1.2V of previous generations to 1.1V. Also, the standard was specifically designed to enable power-efficient operation at a wide range of frequencies. The I/O can operate in un-terminated mode at low frequencies with a reduced voltage swing, and the standard allows rapid switching between operating points so the lower frequency operation can be used whenever possible.

This rapid switching is enabled by the addition of frequency set points (FSPs). LPDDR4 specifies two FSPs, which are copies of all the DRAM registers that store operating parameters which might need to be changed for operation at two different frequencies. Once both operating frequencies are trained and the parameters stored in each of the two corresponding FSPs, switching between the frequencies can be accomplished by a single mode register write. This reduces the latency for frequency changes, and enables the system to operate at the optimal speed for the workload more often.

“It supports end-user flexibility,” noted Vuong. “Some designers like to run their devices as fast as they can and then put them to sleep. Others like to run at lower frequencies – and lower power – when possible. A process might take a little longer but that’s a trade-off they’re willing to make. We designed LPDDR4 to be flexible enough to allow the end-user to decide what they want to do.” With that flexibility comes superior performance – an LPDDR4 device, at a similar data rate, will consume less power than an LPDDR3 device.

JEDEC leads in the development of standards for the microelectronics industry.

Gigaphoton Inc., a lithography light source manufacturer, today unveils a new function, called “eTGM,” available for its flagship high-output GT Series of ArF immersion laser products. The eTGM function, a new technology that reduces neon gas consumption by approx. 50%, was developed as part of the EcoPhoton™ program, a roadmap to implement Green Innovations that is being promoted by Gigaphoton.

Today, ArF immersion lasers used for leading-edge semiconductor fabrication utilize a mixture of neon, fluorine, and argon gases as a laser gas, with neon gas accounting for more than 96% of the laser gas mixture. Therefore, a fairly large amount of neon gas is consumed to run ArF immersion lasers. On the other hand, world production of neon gas has been reduced recently, raising the possibility that the price of neon gas will rise in the near future to cause a critical challenge to the entire industry.

The eTGM function closely monitors the laser running status, thereby allowing the injection amount and discharge amount of laser gas to be optimized. By incorporating the eTGM function into the laser unit, the consumption of neon gas can be cut by half without lowering the laser performance. The eTGM function is provided as an option for Gigaphoton’s ArF immersion lasers, and can be incorporated into lasers already running in the field.

In addition, along with introduction of the eTGM function, a new “green monitoring” function is also provided as an upgrade for the paddle of the laser. This upgrade allows the user to monitor the consumption of laser gas in real time under a production environment.

“I am very pleased to introduce eTGM to the market as a new product from our Green Innovations,” commented Hitoshi Tomaru, President and CEO of Gigaphoton, “We believe this technology will help our customers to manage the gas cost in their fabs at an optimum level, thus providing an effective measure against the risk of a rise of neon gas cost caused by the unstable supply of this noble gas. We are committed to proceeding with our EcoPhoton™ program to make further contributions to greening of the semiconductor industry.”

UCL scientists have discovered a new method to efficiently generate and control currents based on the magnetic nature of electrons in semiconducting materials, offering a radical way to develop a new generation of electronic devices.

One promising approach to developing new technologies is to exploit the electron’s tiny magnetic moment, or ‘spin’. Electrons have two properties – charge and spin – and although current technologies use charge, it is thought that spin-based technologies have the potential to outperform the ‘charge’-based technology of semiconductors for the storage and process of information.

In order to utilise electron spins for electronics, or ‘spintronics’, the method of electrically generating and detecting spins needs to be efficient so the devices can process the spin information with low-power consumption. One way to achieve this is by the spin-Hall effect, which is being researched by scientists who are keen to understand the mechanisms of the effect, but also which materials optimise its efficiency. If research into this effect is successful, it will open the door to new technologies.

The spin-Hall effect helps generate ‘spin currents’ which enable spin information transfer without the flow of electric charge currents. Unlike other concepts that harness electrons, spin current can transfer information without causing heat from the electric charge, which is a serious problem for current semiconductor devices. Effective use of spins generated by the spin-Hall effect can also revolutionise spin-based memory applications.

The study published in Nature Materials shows how applying an electric field in a common semiconductor material can dramatically increase the efficiency of the spin-Hall effect which is key for generating and detecting spin from an electrical input.

The scientists reported a 40-times-larger effect than previously achieved in semiconductor materials, with the largest value measured comparable to a record high value of the spin-Hall effect observed in heavy metals such as Platinum. This demonstrates that future spintronics might not need to rely on expensive, rare, heavy metals for efficiency, but relatively cheap materials can be used to process spin information with low-power consumption.

As there are limited amounts of natural resources in the earth and prices of materials are progressively going up, scientists are looking for more accessible materials with which to develop future sustainable technologies, potentially based on electron spin rather than charge. Added to this, the miniaturisation approach of current semiconductor technology will see a point when the trend, predicted by Moore’s law, will come to an end because transistors are as small as atoms and cannot be shrunk any further. To address this, fundamentally new concepts for electronics will be needed to produce commercially viable alternatives which meet demands for ever-growing computing power.

Co-author of the study, Dr Hidekazu Kurebayashi (UCL London Centre for Nanotechnology), said, “We borrowed 50-year-old semiconductor phenomena for our modern spintronic research. Our results are the start of the story but are a proof of principle with a promising future for spins; as we know that there is existing matured semiconductor growth technology, we can stand on the shoulders of the giants.”

A new paper by University of Notre Dame researchers describes their investigations of the fundamental optical properties of a new class of semiconducting materials known as organic-inorganic “hybrid” perovskites.

The research was conducted at the Notre Dame Radiation Laboratory by Joseph Manser, a doctoral student in chemical and biomolecular engineering, under the direction of Prashant Kamat, Rev. John A. Zahm Professor of Science. The findings appear in a paper in the August 10 edition of the journal Nature Photonics.

The term “perovskites” refers to the structural order these materials adopt upon drying and assembling in the solid state.

“Hybrid perovskites have recently demonstrated exceptional performance in solid-state thin film solar cells, with light-to-electricity conversion efficiencies approaching nearly 20 percent,” Manser said. “Though currently only at the laboratory scale, this efficiency rivals that of commercial solar cells based on polycrystalline silicon. More importantly, these materials are extremely easy and cheap to process, with much of the device fabrication carried out using coating and or printing techniques that are amenable to mass production. This is in stark contrast to most commercial photovoltaic technologies that require extremely high purity materials, especially for silicon solar cells, and energy-intensive, high-temperature processing.”

Manser points out that although the performance of perovskite solar cells has risen dramatically in only a few short years, the scientific community does not yet fully know how these unique materials interact with light on a fundamental level.

Manser and Kamat used a powerful technique known as “transient absorption pump-probe spectroscopy” to examine the events that occur trillions of a second after light absorption in the hybrid methylammonium lead iodide, a relevant material for solar applications. They analyzed both the relaxation pathway and spectral broadening in photoexcited hybrid methylammonium lead iodide and found that the excited state is primarily composed of separate and distinct electrons and holes known as “free carriers.”

“The fact that these separated species are present intrinsically in photoexcited hybrid methylammonium lead iodide provides a vital insight into the basic operation of perovskite solar cells,” Manser said. “Since the electron and hole are equal and opposite in charge, they often exist in a bound or unseparated form known as an ‘exciton.’ Most next-generation’ photovoltaics based on low-temperature, solution-processable materials are unable to perform the function of separating these bound species without intimate contact with another material that can extract one of the charges. ”

This separation process siphons energy within the light absorbing layer and restricts the device architecture to one of highly interfacial surface area. As a result, the overall effectiveness of the solar cell is reduced.

“However, from our study, we now know that the photoexcited charges in hybrid perovskites exist in an inherently unbound state, thereby eliminating the additional energy loss associated with interfacial change separation,” Manser said. “These results indicate that hybrid perovskites represent a ‘best of both worlds’ scenario, and have the potential to mitigate the compromise between low-cost and high-performance in light-harvesting devices.”

Although the research was on the fundamental optical and electronic properties of hybrid perovskites, it does have direct implications for device applications. Understanding how these materials behave under irradiation is necessary if they are to be fully optimized in light-harvesting assemblies.

University of California, Davis researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, are exploring new materials and device structures to develop next-generation memory technologies.

The research promises to help data storage companies advance their technologies with predicted benefits including increased speed, lower costs, higher capacity, more reliability and improved energy efficiency compared to today’s magnetic hard disk drive and solid state random access memory (RAM) solutions.

Conducted by UC Davis’ Takamura Research Group that has extensive experience in the growth and characterization of complex oxide thin films, heterostructures and nanostructures, the research involves leveraging complex oxides to manipulate magnetic domain walls within the wires of semiconductor memory devices at nanoscale dimensions. This work utilized sophisticated facilities available through the network of Department of Energy-funded national laboratories at the Center for Nanophase Materials Sciences, Oak Ridge National Laboratory and the Advanced Light Source, Lawrence Berkeley National Laboratory.

“We were inspired by the ‘Race Track Memory’ developed at IBM and believe complex oxides have the potential to provide additional degrees of freedom that may enable more efficient and reliable manipulation of magnetic domain walls,” said Yayoi Takamura, Associate Professor, Department of Chemical Engineering and Materials Science, UC Davis.

Existing magnetic hard disk drive and solid state RAM solutions store data either based on the magnetic or electronic state of the storage medium. Hard disk drives provide a lower cost solution for ultra-dense storage, but are relatively slow and suffer reliability issues due to the movement of mechanical parts. Solid state solutions, such as Flash memory for long-term storage and DRAM for short-term storage, offer higher access speeds, but can store fewer bits per unit area and are significantly more costly per bit of data stored.

An alternative technology that may address both of these shortcomings is based on the manipulation of magnetic domain walls, regions that separate two magnetic regions. This technology, originally proposed by IBM researchers and named ‘Race Track Memory,’ is where the UC Davis work picked up.

With most previous studies focused on metallic magnetic materials and their alloys due to well-established processing steps and high Curie temperatures, challenges still remain in manipulating parameters such as the type of domain walls formed, their position within the nanowires and their controlled movement along the length of the nanowires.

The UC Davis research investigates the use of complex oxides, such as La0.67Sr0.33MnO3 (LSMO), and heterostructures with other complex oxides as candidate materials. Complex oxides are part of an exciting new class of so-called “multifunctional’ materials that exhibit multiple properties (e.g. electronic, magnetic, etc.) and may thereby enable multiple functions in a single device. For the case of LSMO, it is a half metal, exhibits colossal magnetoresistance (CMR), meaning it can dramatically change electrical resistance in the presence of a magnetic field, and undergoes a simultaneous ferromagnetic-to-paramagnetic and metal-to-insulator transition at its Curie temperature.

In addition, these properties are sensitive to external stimuli, such as applied magnetic/electric fields, light irradiation, pressure and temperature. These attributes may allow researchers to better manipulate the position and movement of the magnetic domain walls along the length of the nanowires.

“While still in the early stages, the innovative research from the UC Davis team is helping the industry gain a better fundamental understanding linking the chemical, structural, magnetic and electronic properties of next-generation memory materials,” said Bob Havemann, Director of Nanomanufacturing Sciences at the SRC.

A “valley of death” is well-known to entrepreneurs–the lull between government funding for research and industry support for prototypes and products. To confront this problem, in 2013 the National Science Foundation (NSF) created a new program called InTrans to extend the life of the most high-impact NSF-funded research and help great ideas transition from lab to practice.

Today, in partnership with Intel Corporation, NSF announced the first InTrans award of $3 million to a team of researchers who are designing customizable, domain-specific computing technologies for use in healthcare.

The work could lead to less exposure to dangerous radiation during x-rays by speeding up the computing side of medicine. It also could result in patient-specific cancer treatments.

Led by the University of California, Los Angeles, the research team includes experts in computer science and engineering, electrical engineering and medicine from Rice University and Oregon Health and Science University. The team comes mainly from the Center of Domain-Specific Computing (CDSC), which was supported by an NSF Expeditions in Computing Award in 2009.

Expeditions, consisting of five-year, $10 million awards, represent some of the largest investments currently made by NSF’s Computer, Information Science and Engineering (CISE) directorate.

Today’s InTrans grant extends research efforts funded by the Expedition program with the aim of bringing the new technology to the point where it can be produced at a microchip fabrication plant (or fab) for a mass market.

“We see the InTrans program as an innovative approach to public-private partnership and a way of enhancing research sustainability,” said Farnam Jahanian, head of NSF’s CISE Directorate. “We’re thrilled that Intel and NSF can partner to continue to support the development of domain-specific hardware and to transition this excellent fundamental research into real applications.”

In the project, the researchers looked beyond parallelization (the process of working on a problem with more than one processor at the same time) and instead focused on domain-specific customization, a disruptive technology with the potential to bring orders-of-magnitude improvements to important applications. Domain-specific computing systems work efficiently on specific problems–in this case, medical imaging and DNA sequencing of tumors–or a set of problems with similar features, reducing the time to solution and bringing down costs.

“We tried to create energy-efficient computers that are more like brains,” explained Jason Cong, the director of CDSC, a Chancellor’s Professor of computer science and electrical engineering at UCLA, and the lead on the project.

“We don’t really have a centralized central processing unit in there. If you look at the brain you have one region responsible for speech, another region for motor control, another region for vision. Those are specialized ‘accelerators.’ We want to develop a system architecture of that kind, where each accelerator can deliver a hundred to a thousand times better efficiency than the standard processors.”

The team plans to identify classes of applications that share similar computation kernels, thereby creating hardware that solves a range of common related problems with high efficiency and flexibility. This differs from specialized circuits that are designed to solve a single problem (such as those used in cell phones) or general-purpose processors designed to solve all problems.

“The group laid out a different way of presenting the problem of domain-specific computing, which is: How to determine the common features and support them efficiently?” said Sankar Basu, program officer at NSF. “They developed a framework for domain-specific hardware design that they believe can be applied in many other domains as well.”

The group selected medical imaging and patient specific cancer treatments–two important problems in healthcare–as the test applications upon which to create their design because of healthcare’s significant impact on the national economy and quality of life.

Medical imaging is now used diagnose a multitude of medical problems. However, diagnostic methods like x-ray CT (computed tomography) scanners can expose the body to cumulative radiation, which increases risk to the patient in the long term.

Scientists have developed new medical imaging algorithms that lead to less radiation exposure, but these have been constrained due to a lack of computing power.

Using their customizable heterogeneous platform, Cong and his team were able to make one of the leading CT image reconstruction algorithms a hundred times faster, thereby reducing a subject’s exposure to radiation significantly. They presented their results in May 2014 at the IEEE International Symposium on Field-Programmable Custom Computing Machines.

“The low-dose CT scan allows you to get a similar resolution to the standard CT, but the patient can get several times lower radiation,” said Alex Bui, a professor in the UCLA Radiological Sciences department and a co-lead of the project. “Anything we can do to lower that exposure will have a significant health impact.”

In theory, the technology also exists to determine the specific strain of cancer a patient has through DNA sequencing and to use that information to design a patient-specific treatment. However, it currently takes so long to sequence the DNA that once one determines a tumor’s strain, the cancer has already mutated. With domain-specific hardware, Cong believes rapid diagnoses and targeted treatments will be possible.

“Power- and cost-efficient high-performance computation in these domains will have a significant impact on healthcare in terms of preventive medicine, diagnostic procedures and therapeutic procedures,” said Cong.

“Cancer genomics, in particular, has been hobbled by the lack of open, scalable and efficient approaches to rapidly and accurately align and interpret genome sequence data,” said Paul Spellman, a professor at OHSU, who works on personalized cancer treatment and served as another co-lead on the project.

“The ability to use hardware approaches to dramatically improve these speeds will facilitate the rapid turnarounds in enormous datasets that will be necessary to deliver on precision medicine.”

Down the road, the team will work with Spellman and other physicians at OHSU to test the application of the hardware in a real-world environment.

“Intel excels in creating customizable computing platforms optimized for data-intensive computation,” said Michael C. Mayberry, corporate vice president of Intel’s Technology and Manufacturing Group and chair of Corporate Research Council. “These researchers are some of the leading lights in the field of domain-specific computing.

“This new effort enables us to maximize the benefits of Intel architecture. For example, we can ensure that Intel Xeon processor features are optimized, in connection with various accelerators, for a specific application domain and across all architectural layers,” Mayberry said. “Life science and healthcare research will undoubtedly benefit from the performance, flexibility, energy efficiency and affordability of this application.”

The InTrans program not only advances important fundamental research and integrates it into industry, it also benefits society by improving medical imaging technologies and cancer treatments, helping to extend lives.

“Not every research project will get to the stage where they’re ready to make a direct impact on industry and on society, but in our case, we’re quite close,” Cong said. “We’re thankful for NSF’s support and are excited about continuing our research under this unique private-public funding model.”

Extremely thin, semi-transparent, flexible solar cells could soon become reality. At the Vienna University of Technology, Thomas Mueller, Marco Furchi and Andreas Pospischil have managed to create a semiconductor structure consisting of two ultra-thin layers, which appears to be excellently suited for photovoltaic energy conversion.

Several months ago, the team had already produced an ultra-thin layer of the photoactive crystal tungsten diselenide. Now, this semiconductor has successfully been combined with another layer made of molybdenum disulphide, creating a designer-material that may be used in future low-cost solar cells. With this advance, the researchers hope to establish a new kind of solar cell technology.

The solar cell's layer system: two semiconductor layers in the middle, connected to electrodes on either side.

The solar cell’s layer system: two semiconductor layers in the middle, connected to electrodes on either side.

Two-Dimensional Structures

Ultra-thin materials, which consist only of one or a few atomic layers are currently a hot topic in materials science today. Research on two-dimensional materials started with graphene, a material made of a single layer of carbon atoms. Like other research groups all over the world, Thomas Mueller and his team acquired the necessary know-how to handle, analyse and improve ultra-thin layers by working with graphene. This know-how has now been applied to other ultra-thin materials.

“Quite often, two-dimensional crystals have electronic properties that are completely different from those of thicker layers of the same material”, says Thomas Mueller. His team was the first to combine two different ultra-thin semiconductor layers and study their optoelectronic properties.

Two Layers with Different Functions

Tungsten diselenide is a semiconductor which consists of three atomic layers. One layer of tungsten is sandwiched between two layers of selenium atoms. “We had already been able to show that tungsten diselenide can be used to turn light into electric energy and vice versa”, says Thomas Mueller. But a solar cell made only of tungsten diselenide would require countless tiny metal electrodes tightly spaced only a few micrometers apart. If the material is combined with molybdenium disulphide, which also consists of three atomic layers, this problem is elegantly circumvented. The heterostructure can now be used to build large-area solar cells.

When light shines on a photoactive material single electrons are removed from their original position. A positively charged hole remains, where the electron used to be. Both the electron and the hole can move freely in the material, but they only contribute to the electrical current when they are kept apart so that they cannot recombine.

To prevent recombination of electrons and holes, metallic electrodes can be used, through which the charge is sucked away – or a second material is added. “The holes move inside the tungsten diselenide layer, the electrons, on the other hand, migrate into the molybednium disulphide”, says Thomas Mueller. Thus, recombination is suppressed.

This is only possible if the energies of the electrons in both layers are tuned exactly the right way. In the experiment, this can be done using electrostatic fields. Florian Libisch and Professor Joachim Burgdörfer (TU Vienna) provided computer simulations to calculate how the energy of the electrons changes in both materials and which voltage leads to an optimum yield of electrical power.

Tightly Packed Layers

“One of the greatest challenges was to stack the two materials, creating an atomically flat structure”, says Thomas Mueller. “If there are any molecules between the two layers, so that there is no direct contact, the solar cell will not work.” Eventually, this feat was accomplished by heating both layers in vacuum and stacking it in ambient atmosphere. Water between the two layers was removed by heating the layer structure once again.

Part of the incoming light passes right through the material. The rest is absorbed and converted into electric energy. The material could be used for glass fronts, letting most of the light in, but still creating electricity. As it only consists of a few atomic layers, it is extremely light weight (300 square meters weigh only one gram), and very flexible. Now the team is working on stacking more than two layers – this will reduce transparency, but increase the electrical power.

Tighter overlay requirements are motivating device manufacturers to explore new ways to characterize and manage overlay to improve yield. 

BY SHRINIVAS SHETTY, DAVID M. OWEN and SCOTT ZAFIROPOULO Ultratech, Inc., San Jose, CA 

Control of overlay in multi-layer devices structures has always been important in semiconductor fabrication. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. As devices shrink, the overlay require- ments become more and more stringent (FIGURE 1). The tighter overlay requirements are motivating device manufacturers to explore new ways to characterize and manage overlay to improve yield. The overlay budget includes contributions from the lithographic scanner, the reticle and the wafer. The wafer represents the largest source of overlay variability during high-volume manufacturing. Therefore, the development of an inspection strategy to control within-wafer and wafer-to-wafer variability may provide the key to meeting the challenges associated with future generations of devices.

Traditional wafer warpage or distortion measurements have typically used point-by-point measurements to generate low-density maps of the wafer geometry with a few hundred data points across the wafer. Depending on the specific technique, a higher density map may be possible at the expense of throughput or limiting the measurement to a small portion of the wafer. The trade-off of point density and throughput has meant that the use of wafer distortion characterization for overlay control has been limited to off-line process development and not to improve yields.

FIGURE 1. As devices shrink, the overlay requirements become more and more stringent.

FIGURE 1. As devices shrink, the overlay requirements become more and more stringent.

The Superfast system based on the Coherent Gradient Sensing (CGS) interferometer uniquely provides high-density front-side pattern wafer maps (>3,000,000 data points) with fast data acquisition (seconds per wafer). The high throughput along with small foot print leads to a low cost of ownership relative to competing technologies.

This article discusses using deformation data from the front-side of a patterned wafer on the Superfast, we are able to understand the relationships between surface displacements, stress and overlay. It also reviews a case study evaluating the role of millisecond annealing parameters on overlay and stress.

Superfast (CGS) technology description

The CGS interferometer is a type of lateral shearing interferometer. The interference is generated in a self-referencing manner using two parallel diffraction gratings. This self-referencing approach eliminates the need for an independent reference beam from, for example, a flat mirror and ensures excellent fringe contrast regardless of the reflectivity of the surface under investigation. This is a key differentiator to accurately measure patterned wafers.

The interferometer essentially compares the relative heights of two points on the surface that are separated by a fixed distance, called the shearing distance. Physically, the change in height over a fixed distance provides slope or tilt information and the fringes in a CGS interference pattern are contours of constant slope. The slope data derived from the interference patterns is integrated numerically to generate the surface shape or topography.

Application to thin film stress measurement

The Superfast inspection system is designed for semiconductor manufacturing based on the CGS interferometer. The Superfast tool features a collimated probe beam of >300mm in diameter that is expanded from a relatively low power HeNe laser. The probe beam illuminates the entire wafer at once and the wafer is supported on three lift pins, which are then subtracted from the final analysis. The beam that reflects off of the wafer surface is distorted in accordance with the local height variations of the wafer. The distorted beam is steered through the two parallel diffraction gratings to generate an interference pattern that is imaged on to a CCD array. As a result, the wafer surface is mapped with high resolution (>3,000,000 data points) with measurement times of seconds.

FIGURE 2. Typical results from the Superfast inspection system, designed for semiconductor manufacturing based on the CGS interferometer.

FIGURE 2. Typical results from the Superfast inspection system, designed for semiconductor manufacturing based on the CGS interferometer.

Data integrity on patterned wafers is further enhanced through the implementation of phase shifting. Phase shifting is achieved by moving the gratings in the direction parallel to the shearing direction. Phase shifting provides several advantages and for the measurement of patterned wafers. The most notable being that fringe contrast in the interference fringes, that modulate with phase shifting can effectively be separated from pattern contrast, which is static with phase shifting. Phase shifting along with the inherent self-referencing nature of the CGS technique results in relatively high measurement integrity on patterned wafers without the need for dedicated or distinct targets, pads or other specialized features in the layout. Typical results are shown in FIGURE 2.

Compared to other techniques, Superfast has several distinct advantages.

  • Front Side Pattern Wafer Measurement: Core CGS 3G technology has been used to measure front-side of pattern wafers for over a decade.
  • High Data Density: Superfast generates high density maps of surface displacements that feature more than 3,000,000 points of data. In this manner, detailed within-die, die-to- die and wafer-to-wafer process variations that lead to overlay errors can be characterized.
  • High Throughput/Low Cost: The Superfast data set consists of interferometric images of the full wafer. These images can be captured rapidly using CCD camera, providing system throughputs of 100-150 wafers per hour.
  • Flexible Implementation: Superfast is capable of evaluating overlay at any step in the process flow and does not rely on dedicated overlay targets. In this manner, Superfast provides the ability to catch potential overlay problems due to process excursions upstream of lithography, thereby reducing material- at-risk and the need for subsequent scrap or rework. 
FIGURE 3. Displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction.

FIGURE 3. Displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction.

Case study: millisecond anneal characterization

This section describes a case study to illustrate the application of Superfast technology to characterize a millisecond anneal process. Four wafers of a full-flow 65nm device were annealed using Laser Spike Annealing (LSA). The device contained silicon germanium with 20% Ge. The four wafers were processed at peak annealing temperatures of 1235 or 1270oC and annealing times of 200 or 400 microseconds. Process-induced deformation information was collected by measure pre-anneal and post-anneal wafer topography using the Superfast system. After millisecond annealing, the wafers were processed through to contact patterning. Overlay data was collected post-lithography for all four wafers. The overlay was measured at 9 sites per shot for 28 shots. Surface displacement data was extracted at the same nominal locations on the wafer and displacement residuals were computed using linear inter-field and intra-field correction.

The displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction are shown in FIGURE 3. Inspection of Fig. 3 reveals that the vector maps for the 1235oC temperature conditions (Figs. 3a & 3b) as well as the 1270oC / 200μs condition (Fig. 3c) all exhibit similar features such that the displacement vectors are generally in the same direction at a particular location in those three vector maps with the same relative vector magnitudes within-wafer. On the other hand, the vector map for the 1270oC / 400μs anneal (Fig. 3d) shows a fundamentally different distortion characteristic, indicating perhaps a change in deformation mechanism associated with the higher thermal budgets. This data suggests that wafer distortion measurements may provide a relatively efficient way to study transitions in mechanisms that occur under different processing conditions.

The correlation between the surface displacement residuals and the overlay residuals is shown in FIGURE 4. The data in Fig. 4 is based on the |mean|+3 sigma values of both quantities as evaluated at the locations shown in the vector maps of Fig. 3. There are several features of the plot in Fig. 4 that are notable. First, the corre- lation between overlay residuals and displacement residuals is excellent with a correlation coeffi- cient, r=0.985. Second, the extrapolation of the best-fit straight line to a displacement value of zero indicates a corresponding finite and positive overlay value of ~0.2. This result is not unexpected, since it is anticipated that other factors such as pattern placement error, lens errors and wafer distortion from other processes will contribute to the total overlay error. As such the overlay axis intercept provides an estimate of those other factors. Third, the slope of overlay versus displacement line is <1. A slope of less than 1 is consistent with the concept discussed in section 3, that the non-uniform stress component of the displacement field is related to the force acting along the interface or potential for mis-alignment. In this respect, it represents perhaps the maximum expected mis-alignment and the resulting overlay error will be some fraction of the ‘potential’ (i.e. slope <1). In addition, the slope value indicates that surface displacement is a more sensitive metric than overlay in that for the same process variability, surface displacement will change more rapidly than overlay.

FIGURE 4. The correlation between the surface displacement residuals and the overlay residuals is shown.

FIGURE 4. The correlation between the surface displacement residuals and the overlay residuals is shown.

Summary and conclusions

The tightening of overlay budgets at advanced technology nodes has led to a greater importance in understanding and when possible controlling wafer distortion. This paper has provided a description of a novel measurement and analysis approach to quickly and efficiently evaluate the effect of process-induced deformation on surface displacement and its relation to overlay errors. The millisecond annealing case study showed excellent correlation between the displacement residuals and overlay residuals with the correlation coefficient of 0.985. Utilizing the fundamental advantages of the CGS technology, the superfast is well suited for front- side patterned wafer topography measurement. The system allows for rapid measurement of wafer distortion and surface displacement with very high system throughputs. Data maps consisting of >3,000,000 data points can be acquired in seconds on patterned wafers without the need for special targets or dedicated structures.