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Four joint laboratories, representing a commitment of S$200m between private and public sectors, were launched today between A*STAR’s Institute of Microelectronics (IME), and its 10 industry partners. The Advanced Semiconductor Joint Labs will develop and advance semiconductor technologies for future electronics markets. The industry partners involved in this international collaboration are: Applied Materials, Dai Nippon Printing, DISCO, KLA-Tencor, Mentor Graphics, Nikon, Panasonic Factory Solutions Asia Pacific, PINK, Tokyo Electron Ltd. and Tokyo Ohka Kogyo.

While expectations are for smart devices to sustain a compact form factor, consumers also expect powerful performance and low power consumption. The challenge for the semiconductor industry is to meet these needs by addressing system and integration scaling in the electronics market. The four joint labs in lithography, wafer level packaging (WLP), metrology and assembly, will provide an integrated platform for semiconductor R&D, starting with patterning, further development of 3D Integrated Circuits (IC), quality control, and finally, the assembly and high-volume manufacturing of chips.

The joint labs build upon the successful model of the IME-Applied Materials Centre of Excellence. Together, the four labs will enable the development of innovative semiconductor technologies and allow partners to undertake solutions-oriented semiconductor R&D and facilitate commercialisation that is earlier, faster and cheaper. This international partnership also bears testament to the industry relevance of IME’s deep research capabilities, and will encourage further development of solutions for global implementation.

Mr Lim Chuan Poh, Chairman of A*STAR, said, “The launch of IME’s Advanced Semiconductor Joint Labs today is an excellent example of public-private partnership under an open innovation framework. I am pleased that A*STAR IME has entered into this strategic partnership with many leading global industry players to capture new growth opportunities for Singapore and the region. The launch of the Advanced Semiconductor Joint Labs reaffirms A*STAR’s deep capabilities and strong infrastructure in the R&D ecosystem to serve the growing needs of the semiconductor industry.”

Professor Dim-Lee Kwong, Executive Director of IME said, “These joint labs further demonstrate our ability to build a global network of partnerships that stretch across the supply chain. These collaborations will encourage semiconductor R&D that is relevant for industry, and provide solutions for a rapidly evolving global electronics market. Through this integrated platform, our partners can leverage A*STAR IME’s technologies and expertise to develop innovative technologies and products to address challenges in the semiconductor industry.”

Interest in magnetic random access memory (MRAM) is escalating, thanks to demand for fast, low-cost, nonvolatile, low-consumption, secure memory devices. MRAM, which relies on manipulating the magnetization of materials for data storage rather than electronic charges, boasts all of these advantages as an emerging technology, but so far it hasn’t been able to match flash memory in terms of storage density.

In the journal Applied Physics Letters, from AIP Publishing, a France-U.S. research team reports an intriguing new multi-bit MRAM storage paradigm with the potential to rival flash memory.

Increasing the density of memory devices is highly desirable and can be accomplished via a variety of methods. One way is by reducing the patterning dimensions, which leads to an increased number of memory cells per unit surface. Another approach involves increasing the storage capacity of each individual cell — aka “multi-bit storage.”

“Multi-bit storage is typically achieved in MRAM technology by measuring the multiple voltage levels corresponding to various magnetic configurations,” explained Quentin Stainer, lead author of the paper and a Ph.D. student at SPINTEC/CEA, a research institute for electronics and information technologies located in Grenoble, France, and also affiliated with Crocus Technology, a France- and U.S.-based firm that develops magnetically enhanced semiconductor technologies.

At the heart of the team’s work is Crocus Technology’s proprietary Magnetic Logic Unit (MLU) technology, which enables the researchers to remotely control a sensor to probe these configurations. “By identifying key features of the electrical responses we obtain, typically known as ‘extrema points,’ we can infer the stored information,” Stainer said.

The highlight of their work was the “unambiguous demonstration of the feasibility of our method, with as much as 3 bits per unit cells, and recently up to 4 bits, obtained on 110-nanometer-wide devices,” he noted.

It’s also worth noting that the team says their storage paradigm should be able to provide an increased robustness and tolerance to process variability, which will make it easier to produce devices based on this technology for industrial applications.

“Our work will enable the development of products for a wide range of applications including, but not limited to, secure data storage for connected devices — such as smart card, content-addressable memory for Internet routers, as well as high-performance, high-density, and high-temperature memory,” Stainer said.

The team’s next step? Developing a fully functional multi-bit MLU memory product to further demonstrate the industrial viability of their storage paradigm. “New memory paradigms derived from this work are also under development — with potential multi-bit capacities of up to 8 bits per single cell,” he added.

Over the years, computer chips have gotten smaller thanks to advances in materials science and manufacturing technologies. This march of progress, the doubling of transistors on a microprocessor roughly every two years, is called Moore’s Law. But there’s one component of the chip-making process in need of an overhaul if Moore’s law is to continue: the chemical mixture called photoresist. Similar to film used in photography, photoresist, also just called resist, is used to lay down the patterns of ever-shrinking lines and features on a chip.

Paul Ashby and Deirdre Olynick of Berkeley Lab at the Advanced Light Source (ALS) Extreme Ultraviolet 12.0.1 Beamline.

Paul Ashby and Deirdre Olynick of Berkeley Lab at the Advanced Light Source (ALS) Extreme Ultraviolet 12.0.1 Beamline. Credit: Roy Kaltschmidt, Berkeley Lab

Now, in a bid to continue decreasing transistor size while increasing computation and energy efficiency, chip-maker Intel has partnered with researchers from the U.S. Department of Energy’s Lawrence Berkeley National Lab (Berkeley Lab) to design an entirely new kind of resist. And importantly, they have done so by characterizing the chemistry of photoresist, crucial to further improve performance in a systematic way. The researchers believe their results could be easily incorporated by companies that make resist, and find their way into manufacturing lines as early as 2017.

The new resist effectively combines the material properties of two pre-existing kinds of resist, achieving the characteristics needed to make smaller features for microprocessors, which include better light sensitivity and mechanical stability, says Paul Ashby, staff scientist at Berkeley Lab’s Molecular Foundry, a DOE Office of Science user facility. “We discovered that mixing chemical groups, including cross linkers and a particular type of ester, could improve the resist’s performance.” The work is published this week in the journal Nanotechnology.

Finding a new kind of photoresist is “one of the largest challenges facing the semiconductor industry in the materials space,” says Patrick Naulleau, director of the Center for X-ray Optics (CXRO) at Berkeley Lab. Moreover, there’s been very little understanding of the fundamental science of how resist actually works at the chemical level, says Deirdre Olynick, staff scientist at the Molecular Foundry. “Resist is a very complex mixture of materials and it took so long to develop the technology that making huge leaps away from what’s already known has been seen as too risky,” she says. But now the lack of fundamental understanding could potentially put Moore’s Law in jeopardy, she adds.

To understand why resist is so important, consider a simplified explanation of how your microprocessors are made. A silicon wafer, about a foot in diameter, is cleaned and coated with a layer of photoresist. Next ultraviolet light is used to project an image of the desired circuit pattern including components such as wires and transistors on the wafer, chemically altering the resist.

Depending on the type of resist, light either makes it more or less soluble, so when the wafer is immersed in a solvent, the exposed or unexposed areas wash away. The resist protects the material that makes up transistors and wires from being etched away and can allow the material to be selectively deposited. This process of exposure, rinse and etch or deposition is repeated many times until all the components of a chip have been created.

The problem with today’s resist, however, is that it was originally developed for light sources that emit so-called deep ultraviolet light with wavelengths of 248 and 193 nanometers. But to gain finer features on chips, the industry intends to switch to a new light source with a shorter wavelength of just 13.5 nanometers. Called extreme ultraviolet (EUV), this light source has already found its way into manufacturing pilot lines. Unfortunately, today’s photoresist isn’t yet ready for high volume manufacturing.

“The semiconductor industry wants to go to smaller and smaller features,” explains Ashby. While extreme ultraviolet light is a promising technology, he adds, “you also need the resist materials that can pattern to the resolution that extreme ultraviolet can promise.” So teams led by Ashby and Olynick, which include Berkeley Lab postdoctoral researcher Prashant Kulshreshtha, investigated two types of resist. One is called crosslinking, composed of molecules that form bonds when exposed to ultraviolet light. This kind of resist has good mechanical stability and doesn’t distort during development—that is, tall, thin lines made with it don’t collapse. But if this is achieved with excessive crosslinking, it requires long, expensive exposures. The second kind of resist is highly sensitive, yet doesn’t have the mechanical stability.

When low concentrations of crosslinker is added to resist (left), it gains mechanical stability and doesn't require expensive exposures as with high crosslinker concentrations (right). Credit:

When a low concentrations of crosslinker is added to resist (left), it is able to pattern smaller features and doesn’t require longer, expensive exposures as with a high concentrations of crosslinker (right). Credit: Prashant Kulshreshtha, Berkeley Lab

When the researchers combined these two types of resist in various concentrations, they found they were able to retain the best properties of both. The materials were tested using the unique EUV patterning capabilities at the CXRO. Using the Nanofabrication and Imaging and Manipulation facilities at the Molecular Foundry to analyze the patterns, the researchers saw improvements in the smoothness of lines created by the photoresist, even as they shrunk the width. Through chemical analysis, they were also able to see how various concentrations of additives affected the cross-linking mechanism and resulting stability and sensitivity.

The researchers say future work includes further optimizing the resist’s chemical formula for the extremely small components required for tomorrow’s microprocessors. The semiconductor industry is currently locking down its manufacturing processes for chips at the so-called 10-nanometer node. If all goes well, these resist materials could play an important role in the process and help Moore’s Law persist. This research was funded by the Intel Corporation, JSR Micro, and the DOE Office of Science (Basic Energy Sciences).

By Brian Cronquest, Vice President, Technology & IP, MonolithIC 3D Inc.

Hughes Metras, Leti’s VP of Strategic Partnerships North America, introduced the lead talk at their SemiconWest 2014 Leti Day about monolithic 3D technology as the “solution for scaling.” Hughes presented the Leti device technology roadmap which showed monolithic 3D (M3D) as an alternative to scaling from the 2Xnm nodes to well past 5nm. Here’s the important piece of that roadmap, which highlights the partnership with Qualcomm (ST and IBM helped with some of the work as well):

Fig 1

 

The lead talk was given by device scientist Olivier Faynot, Leti’s Device Department Director.  He titled his talk “M3D, a disruptive approach for further scaling,” and began with why the industry needs a solution for scaling.

Most in the industry are in agreement that scaling past the 22nm node, while still quite technically feasible, has priced itself out of most markets. Olivier discussed the what (transistor costs are no longer decreasing) and the why (litho cost escalation and connectivity inefficiencies of energy and delay). And then he made the statement: “if we just keep the current (2Xnm) technology, we can go farther in cost scaling.” [note: see the following blogs and comments for more info on this crucial topic:  Tech Design Forums summary “3D and EDA need to make up for Moore’s Law, says Qualcomm” and Zvi-Or-Bach’s EETimes blogs Qualcomm Calls for Monolithic 3D IC and  28nm – The Last Node of Moore’s Law.]

Oliver showed a summary of a DAC2014 paper and a Qualcomm/GeorgiaTech DAC2014 paper Power/Performance/Area analysis of M3D for an FPGA:

Fig 2

 

The solution is to build the stack sequentially, in a monolithic fashion. Olivier described their monolithic 3D, or sequential 3D, process flow where the lower-level (first layer) of transistors and its interconnect are conventionally made, then inter-level metal is crafted to help the vertical interconnection, and then a second layer of monocrystalline silicon is layer transferred and oxide-oxide low temperature bonded to the top of the inter-level metal dielectric. This is a blanket layer so there are no alignment issues such as those suffered by the thick layer and pre-made (TSV) parallel processing flows. The layer that is transferred in M3D is very thin (10-200nm final), so that direct alignment thru that thin layer to the lower level alignment marks can be made with conventional equipment and achieve conventional alignment tolerances (single digit nanometers).

Now upper-level transistors are formed utilizing SPER (Solid Phase Epitaxial Regrow) for junction doping at 475-600°C and other lower (<400°C) temperature processing for gate stacks, etc. The upper-level and inter-level vertical interconnect is then processed, again with full alignment capability to the lower layer. Note that the lower level transistor Ni salicides are stabilized with platinum co-deposition and fluorine/tungsten implantation to enable their survival at the 475-600°C SPER thermal exposure.

Fig 3

 

Oliver also talked about using laser annealing to activate implanted dopants and repair damages during upper-level transistor processing. He called the laser (pulsed and short wavelength) option of solving the thermal challenge of monolithic 3D as the “crème brûlée” of methods and they were ‘seeing good results.’ Hopefully we will see published data soon. For more information on SPER and laser processing please see my recent blog Monolithic 3DIC: Overcoming silicon defects.

Fig 4

 

Oliver was also asked in the Q&A if stress was a big issue. He replied that stress was not an issue, rather, the biggest challenges were integration ones (how to form a low temp top transistor, stability of the local interconnect level, and the bottom transistor salicide stability). Olivier was asked in the Q&A what the observed performance differences were between the upper-level and lower-level transistors. He replied” Currently we are achieving 95% (of the lower for the upper). We believe we can make 100%.”

Leti has a 14nmPDK ready to go for those who want to design a test circuit in their monolithic 3D flow. They have ELDO, HSPICE, Virtusoso, Calibre, StarRC, etc. files available.

Fig 5

 

Not too surprisingly, the Qualcomm logo showed up on some of the Leti presentation slides. Back in December 2013, Leti signed an agreement to work with Qualcomm – Qualcomm to Evaluate Leti’s Non-TSV 3D Process. ST and IBM have also been working with Leti in various aspects, for example, IBM & Leti used COMPOSE3 to simulate a monolithic InGaAs nFET monolithically over a SiGe pFET on SOI.

CEA-Leti has been busy working on processing flows to enable monolithic 3D devices since before 2009. Perrine Batude won the 2009 Roger A. Haken Best Student Paper Award for the IEDM 2009 paper entitled, “Advances in 3D CMOS Sequential Integration,” where she showed results for a sequentially processed P over N (no metal between transistors layers) testchip Batude’s 2011 IEDM paper showed a 50nm 3D sequential structure on 10nm channel silicon:

Fig 6

 

CEA-Leti also opened a complete 300mm fab extension dedicated to 3D-integration applications, both parallel and monolithic, with an inauguration event in January 2011. As well, back in December 2013, Soitec and CEA renewed their long-standing partnership for an additional five years.

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. I would like to invite you to the IEEE S3S Conference: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S Conference will be held October 6-9, 2014 at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

See you there!

Entegris, Inc. announced the latest addition to its Torrento family of ultra clean liquid filtration solutions used in the semiconductor manufacturing process. The Torrento X Series is the first commercial nondewetting all PTFE filter with 10nm particle retention for advanced wet etch and clean applications.

“As the industry ramps to sub-2X nm manufacturing processes, enhanced cleanliness requirements have become a necessity to reduce particle defectivity and minimize metal contaminants that impact wafer yields,” said Todd Edlund, senior vice president and general manager of Entegris’ Critical Materials Handling Business. “Our new Torrento filter can enable integrated device manufactures to efficiently scale-up and produce more advanced devices.”

Torrento X series filters facilitate “drop-in replacement” of new or existing filters, enabling greater installation flexibility and reducing overall operational costs. The field-proven high-flux membrane filter comes standard with ultra-low metallic cleanliness technology (UCM) to minimize the most challenging contaminants in advanced semiconductor fabs. Entegris also offers an Extreme-Ultra Clean Membrane (X-UCM) option with a higher level of cleanliness compared to any prior generation of PTFE filters with faster start up times and superior retention ratings.

The Torrento X series with 10nm retention, as well as other technology leading contamination control and substrate handling solutions will be featured at the Company’s hospitality suite at the W Hotel in San Francisco, Ca from July 8 through July 10, 2014, which is concurrent with SEMICON West held at the Moscone Center.

Graphene is gaining heated attention, dubbed a “wonder material” with great conductivity, flexibility and durability. However, graphene is hard to come by due to the fact that its manufacturing process is complicated and mass production not possible. Recently, a domestic research team developed a carbon material without artificial defects commonly found during the production process of graphene while maintaining its original characteristics. The newly developed material can be used as a substitute for graphene in solar cells and semiconductor chips. Further, the developed process is based on the continuous and mass-produced process of carbon fiber, making it much easier for full-scale commercialization. In recognition of the innovative approach, the research was introduced on the cover of Nanoscale, a peer-reviewed journal in the field of nano science.

The research team led by Dr. Han-Ik Joh at KIST along with Dr. Seok-In Na at Chonbuk National University and Dr. Byoung Gak Kim at KRICT synthesized carbon nanosheets similar to graphene using polymer, and directly used the transparent electrodes for organic solar cells. The research outcome was introduced in Nanoscale, a journal of Royal Society of Chemistry in the UK under the title of “One-step Synthesis of Carbon Nanosheets Converted from a Polycylic Compound and Their Direct Use as Transparent Electrodes of ITO-free Organic Solar Cells” and was selected as a cover story in the January 21st edition in recognition for this innovative and superb research findings.

To manufacture high quality graphene in large volume, the CVD (chemical vapor deposition)* method is widely used. However, this method requires intensive post-processing (transfer process) as it has to remove used metal after the manufacturing process and move the manufactured graphene to another board such as a solar cell substrate. In this process the quality quickly degrades as it is prone to wrinkles or cracks.
 

The research team developed “carbon nanosheet” in a two-step process, which consists of coating the substrate with a plymer solution and heating. Considering that the existing process consists of 8 steps to manufacture graphene, the new method makes it much simpler. In addition, the new method can be directly used as solar cell without any additional process.

The research team synthesized a polymer with a rigid ladder structure, namely PIM-1(Polymer of intrinsic microporosity-1) to form the CNS through the simpole process, which is spin-coated on the quarts substrates using PIM-1 solution with light green color and then heat-treated at 1,200 °C, leading to transparent and conductive CNS.

The carbon nanosheet can be mass-produced in a simpler process while having high quality since the new process bypasses the steps that are prone to formation of defects such as elimination of the metal substrate or transfer of graphene to another board. The final product is as effective as graphene.

Dr. Han Ik Joh at KIST said, “It is expected to be applied for commercialization of transparent and conductive 2D carbon materials without difficulty since this process is based on the continuous and mass-produced process of carbon fiber.”

This is a follow-up research from the team that recently released its findings on the carbon nanosheet manufacturing based on polyacrylonitrile (published in the 2013 Carbon Vol. 55 and Applied Physics Letters Vol. 102). The new findings are even more meaningful as it offers deeper understanding on the growth mechanism of carbon nanosheet and much simpler manufacturing process.

The research was conducted with the funding from the KIST Proprietary Research Project and National Research Foundation of Korea.

Columbia researchers have observed the fractional quantum Hall effect in bilayer graphene and shown that this exotic state of matter can be tuned by an electric field.

The fractional quantum Hall effect, which can occur when electrons confined to thin sheets are exposed to large magnetic fields, is a striking example of collective behavior where thousands of individual electrons behave as a single system. However, while the basic theory describing this effect is well established, many details of this collective behavior remain not well understood, in part because it is only observable in systems with extremely low disorder.

Graphene, an atomically thin sheet of carbon, is a promising material for study of the fractional quantum Hall effect both because it can it be a nearly defect-free crystal, and because researchers can ‘tune’ the charge density with an external metal ‘gate’ electrode and observe how the quantum states evolve in response. Over the past several years, a collaborative effort at Columbia University spanning researchers from Mechanical Engineering, Electrical Engineering and Physics, developed a series of breakthrough fabrication techniques in order to take advantage of this opportunity, allowing them to report the first observation of the fractional quantum Hall effect in graphene in 2009, and the first wide-range tuning of the effect in 2011.

An even more interesting system for study of the fractional quantum Hall effect is so-called bilayer graphene, which consists of two stacked graphene sheets. In this material, use of two metal gate electrodes (above and below) allows independent tuning of the charge density in each layer, which provides a completely new way to manipulate the fractional quantum Hall states. In particular, theory predicts that it should be possible to create exotic ‘non-abelian’ states that could be used for quantum computation.

While observation of the fractional quantum Hall effect in single layer graphene required simply making cleaner devices, observing this effect in bilayer graphene proved more difficult. “We knew that we could fabricate very clean bilayer graphene structures, but we suffered from our inability to make good electrical contact since bilayer graphene develops an electronic ‘band-gap’ under the high magnetic fields and low temperatures required for our experiments,” says Cory Dean, professor of Physics who recently moved to Columbia University, and lead author on the paper. A critical breakthrough was re-design of the devices so that the charge density in the contact regions could be tuned independently from the rest of the device, which allowed them to maintain good electrical contact even under large magnetic fields. “Once we had this new device structure the results were spectacular.”

Reporting in the July 4, 2014 edition of Science, the team demonstrates the existence of the fractional quantum Hall effect in bilayer graphene and shows evidence of a controllable phase transition by application of electric fields. One of the key questions towards understanding the fractional quantum Hall effect in any system is to identify the order associated with the ground state. For example, do all electrons associated within the collective state carry the same spin? In bilayer graphene this question is more complex since there are several degrees of symmetry at play all at once. In addition to spin, electrons can polarize by spontaneously residing entirely on one layer versus the other. This complexity provides an interesting new phase space to explore for new and unusual effects. In particular, several theories have predicted that application of electric fields to bilayer graphene could enable transitions between these ground state orders. “This is a new experimental knob that just is not available in other systems,” says James Hone, a professor of Mechanical Engineering and co-author on the paper. The team has confirmed for the first time that varying the applied electric field causes a phase transition, but the exact nature of these different phases remains an open question. “While theory expects that we can tune the ground state order, the complexity of the system makes it difficult to determine exactly which order is actually realized,” says Physics Professor and co-author Philip Kim.

“This is where the next phase of our research is headed,” says Dean. “The implications for this result could be far reaching,” he adds, “While we do not yet see any evidence of non-abelian states, the fact that we are able to modify the nature of the fractional quantum Hall effect by electric fields is a really exciting first step.”

While previous efforts have been able to demonstrate different aspects of the sample requirement, no other group has been able to bring this all together into a single device. Dean attributes this success to the unique collaborative environment fostered at Columbia University. “This is truly a remarkable environment,” he says, adding, “The open exchange of ideas across several disciplines makes the environment at Columbia a fertile ground for doing great science.” Device fabrication and initial testing was done at Columbia University. Measurement under large magnetic fields was then performed by the Columbia team with the aid of the National High Magnetic Field Laboratory user facility in Tallahassee, Florida. “We have established a fantastic relationship with the NHFML over many years,” says Dean. “The support provided by the NHMFL personnel at both the technical and scientific level has been invaluable to our efforts.”

Bending the rules


July 1, 2014

For his doctoral dissertation in the Goldman Superconductivity Research Group at the University of Minnesota, Yu Chen, now a postdoctoral researcher at UC Santa Barbara, developed a novel way to fabricate superconducting nanocircuitry. However, the extremely small zinc nanowires he designed did some unexpected — and sort of funky — things.

Chen, along with his thesis adviser, Allen M. Goldman, and theoretical physicist Alex Kamenev, both of the University of Minnesota, spent years seeking an explanation for these extremely puzzling effects. Their findings appear this week in Nature Physics.

“We were determined to figure out how we could reconcile the strange phenomena with the longstanding rules governing superconductivity,” said lead author Chen. “The coexistence of superconductivity with dissipation, which we observed, is counterintuitive and bends the rules as we know them.”

Typically superconductivity and dissipation are thought to be mutually exclusive because dissipation, a process in thermodynamic systems whereby electric energy is transformed into heat, is a feature of a normal — versus a superconductive — state.

“But we discovered that superconductivity and dissipation can coexist under rather generic conditions in what appears to be a universal manner,” Chen said.

After long and careful work, which involved both experimental and theoretical efforts, the researchers found an explanation that fits. Behind all of the observed phenomena is a peculiar nonequilibrium state of quasiparticles — electron-like excitations that formed in the nanowires Chen designed.

The quasiparticles are created by phase slips. In a superconductive state, when supercurrent flows through the nanowire, the quantum mechanical function describing the superconductivity of the wire evolves along the length of the wire as a spiral shaped like a child’s Slinky toy. From time to time, one of the revolutions of the spiral contracts and disappears altogether. This event is called a phase slip. This quirk generates quasiparticles, giving rise to a previously undiscovered voltage plateau state where dissipation and superconductivity coexist.

“The most significant achievement was making the nanowires smaller and cooler than anyone had done previously,” Kamenev said. “This allowed the quasiparticles to travel through the wire faster and avoid relaxation. This leads to a peculiar nonthermal state, which combines properties of a superconductor and a normal metal at the same time.”

In addition to discovering this unique phenomenon, the team also found another heretofore-unseen property in the voltage plateau. When a magnetic field is turned on in the voltage plateau state, rather than shrinking the superconducting region, which is what would usually occur, the superconducting area expands and is enhanced.

“This is an unexpected property of very small nanowires,” said Goldman.

This state appears to be universal for ultra-small superconducting circuitry like Chen’s, which features ideal contacts between the nano-elements and the leads. Such nanoscale superconductors may be key components in future superconducting computer systems.

“Our findings demonstrate that superconducting nanocircuits can be used as a simple, but rather generic platform to investigate nonequilibrium quantum phenomena,” Chen concluded.

“Now we need to explore the parameters of nanowires that give rise to the effect and those that don’t,” Goldman said. “We also need to examine the behavior of wires of different lengths and different materials in order to further define the parameters.”

Do not fold, spindle or mutilate. Those instructions were once printed on punch cards that fed data to mainframe computers. Today’s smart phones process more data, but they still weren’t built for being shoved into back pockets.

In the quest to build gadgets that can survive such abuse, engineers have been testing electronic systems based on a new materials that are both flexible and switchable – that is, capable of toggling between two electrical states, on-off, one-zero, the binary commands that can program all things digital.

Now three Stanford researchers believe that they’ve discovered just such a flexible, switchable material. It is a crystal that can form a paper-like sheet just three atoms thick. Computer simulations show that this crystalline lattice has the remarkable ability to behave like a switch: it can be mechanically pulled and pushed, back and forth, between two different atomic structures – one that conducts electricity well, the other that does not.

“Think of it like flicking a light switch on and off,” says Karel-Alexander Duerloo, a Stanford Engineering graduate student and first author of an article in Nature Communications.

So far this discovery only exists as a simulation. But co-author and team leader Evan Reed, Assistant Professor of Materials Science and Engineering, hopes this work will inspire experimental scientists to fabricate this super-thin crystal and use it to create electronic and other devices that would be as light and flexible as fibers.

Theoretically, such electronic materials have potential to reduce battery-draining power consumption in existing devices such as smart phones. This new, power-efficient material could also make it possible to create ‘smart’ clothing – imagine an ultralight cell phone or a GPS system integrated into your shirt.

Duerloo said this switchable material is formed when one atomic layer of molybdenum atoms gets sandwiched between two atomic layers of tellurium atoms.

Molybdenum and tellurium are elements that are currently used as additives for making alloys, such as steel. Tellurium is also an important component of many modern solar cells.

In his simulation, Duerloo relied on the fact that molybdenum and tellurium form a sheet-like crystal lattice that is just three-atoms thick. Notably, this atomic sandwich can form different crystalline structures that have useful properties: in one structure this lattice easily conducts electricity; in the other configuration it does not (see graphic: https://stanford.box.com/s/kf9r191eu56sy63119fq caption below).

Duerloo’s simulations show that it takes just a tiny effort to toggle the atomic structure of this three-layer amalgam from a non-conductive state into a conductive state. A gentle push switches the material back to the off state (see animation: https://stanford.box.com/s/k8d1p7frar3hl9pfa333 caption below).

These simulations, as yet unsupported by experimental confirmation, are at the leading edge of a new branch of materials science that delves into the behavior of monolayer substances.

The first and most famous monolayer is graphene, which was first observed in 2004. Graphene is a layer of carbon atoms that form a lattice that resembles chicken wire. Although it is just one atom thick, graphene is incredibly strong. A sheet of graphene could bear the weight of a cat without breaking this atomically thin lattice.

Graphene is also electrically conductive. That makes it potentially useful as a light, low power electronic component.

The discoverers of graphene shared a Nobel Prize in 2010, but even before this their work was so honored that other scientists had started looking for other monolayer materials with this interesting confluence of properties: strong, stable, crystalline structures that could conduct electricity.

To help find the most promising materials from a vast universe of molecular structures, a new discipline is rising: computational materials science.

“We’re like the advance scouts that survey the terrain and look for the best materials,” Reed said.

Now that they have simulated the potential of this molybdenum-tellurium crystal the Stanford researchers – the third team member is graduate student Yao Li — hope experimental scientists will explore possible uses of this three-atom thick switch.

“No would have known this was possible before because they didn’t know where to look,” Duerloo said.

Gigaphoton Inc., a major lithography light source manufacturer, announced today that it has succeeded in the development of an innovative purge process, one that does not use the rare gas helium, for its flagship “GT Series” of ArF immersion lasers. Evolving its “Green Innovations” environmental technologies, this innovative helium-free purge process enables significant reduction of helium consumption for lithography tools.

Since its establishment in 2000, Gigaphoton has consistently focused on achieving the highest levels of output power, performance, and stability in the industry, as well as saving on power consumption to deliver the higher efficiency required for environmentally conscious “green fab.” Recently, an unstable supply and a price rise of helium gas have triggered Gigaphoton to work on development of the purge process that does not use helium, teaming up with a device manufacturer and a scanner manufacturer. At completion of evaluating the process performance at a Japanese device manufacturer, Gigaphoton has proven that this innovative purge process can be used for volume production.

On Earth, helium is a rare gas – 5.2 ppm by volume in the atmosphere. It is mainly mined as a byproduct when natural gas is mined. Helium has been used in various industries, including for medical equipment, linear motor cars, and semiconductors, and is indispensable for modern life.But consumption of helium in manufacturing has been increased dramatically, and it is forecast that our helium supply will be depleted in approximately 25 years if consumption continues at the current rate. So, the unstable supply and price rise of helium has become a serious issue today.

Gigaphoton recognizes that this issue produces a negative impact upon the entire industrial world. The company has considered how to use a gas substituting for helium as early as possible in order to reduce helium consumption for the purge process and thus help to conserve the helium supply for other industries that require helium more seriously, thus making a great contribution to the industrial world.

Helium is used as a purge gas for optical component modules within a laser light source. It removes active gases and impurities generated within the modules to prevent optical components from being damaged. One laser unit consumes approx. 80-160 kiloliters of helium per year. Therefore, all the laser light sources currently operating worldwide consume approx. 100,000 kiloliters of helium annually.

Instead of helium, Gigaphoton has developed, for the first time in the world, the purge process that uses nitrogen, an inert gas that accounts for approx. Seventy eight percent of the atmosphere, with a stable supply, and proven that the process can maintain laser performance at the same level as that with helium.

“As a laser supplier supporting the semiconductor manufacturing, we will strive to maintain a stable production environment and stay active to be conscious of global environment and whole industries,” said Hitoshi Tomaru, President and CEO of Gigaphoton Inc. “We are committed to proceeding with our EcoPhoton program to make further contributions to greening of the semiconductor industry.”