Tag Archives: letter-wafer-tech

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled the GEMINI FB XT—its next-generation fusion wafer bonding platform, which combines several performance breakthroughs to move the semiconductor industry closer to the goal of high-volume manufacturing (HVM) of 3D-ICs with through-silicon vias (TSVs).  Featuring up to a three-fold improvement in wafer-to-wafer bond alignment accuracy as well as a 50 percent increase in throughput over the previous industry benchmark platform, the GEMINI FB XT clears several key hurdles to the industry’s adoption of 3D-IC/TSV technology in order to drive continuous improvements in device density and performance without the need for increasingly costly and complex lithography processing.

ev group

Wafer-to-wafer bonding is an essential process step to enable 3D devices such as stacked DRAM, memory-on-logic and future CMOS image sensors.  At the same time, minimizing the dimensions of TSVs, which serve as the electrical contacts between the bonded wafers, is a key requirement for bringing down the cost of 3D devices and supporting higher levels of device performance and bandwidth, as well as lower power consumption.  However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected devices on the bonded wafers, as well as to minimize the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices.

Alignment is key for fusion-bonded 3D-ICs

According to the 2012 edition of the International Technology Roadmap for Semiconductors (ITRS), high-density TSV applications will require wafer bonding alignment accuracy of 500 nm (3 sigma) by 2015.  To enable high process yields for hybrid bonding, even tighter specifications are needed.  The GEMINI FB XT incorporates EVG’s newly introduced SmartView NT2 bond aligner, which enables dramatically improved wafer-to-wafer alignment accuracy to below 200nm (3 sigma).  This corresponds to up to a three-fold improvement over EVG’s widely adopted SmartView NT platform—the previous industry benchmark for bond aligners—and exceeds the latest ITRS Roadmap requirements, thereby filling a critical gap faced by device manufacturers that are considering adopting 3D-IC/TSV designs as part of their product roadmaps.  An integrated metrology module validates alignment after pre-bonding to enable customers to quickly fine-tune the bonding process for HVM processing if necessary.

Leveraging EVG’s XT Frame platform, which is utilized across the spectrum of the company’s industry-leading systems, the GEMINI FB XT is optimized for ultra-high throughput and productivity.  Additional pre- and post-processing modules have been added for wafer cleaning and surface preparation, plasma activation and wafer bond alignment that enable increases in throughput by up to 50 percent.  This significantly increased throughput combined with the tighter alignment specifications supports IC manufacturers’ efforts to move wafer stacking upstream in the manufacturing value chain from mid-end-of-line (MEOL) and back-end-of-line (BEOL) processing to front-end-of-line (FEOL) processing.  This, in turn, enables device manufacturers to integrate more functionality into their product at the wafer level, where higher levels of parallel processing can significantly drive down 3D-IC/TSV manufacturing costs.

“While EUV lithography continues to face delays, 3D-IC/TSV integration has emerged as one of the most promising approaches to extending Moore’s Law for future device generations.  Yet enabling 3D-IC/TSV integration for emerging memory and logic applications is impossible without the ability to achieve tight wafer-to-wafer alignment,” stated Paul Lindner, executive technology director at EV Group.  “EVG is continuing to drive improvements across our suite of solutions for 3D-IC/TSV applications to help bring our customers closer to the goal of commercializing 3D-IC technology.  Our new GEMINI FB XT platform marks a major milestone along that path, and we look forward to working with our customers to make the promise of 3D-IC high-volume manufacturing a reality for them.”

By Shannon Davis, Web Editor

Overheard @The ConFab: “I feel the best I’ve felt about semi since 2009.” –Mike Noonen, Silicon Catalyst

Monday’s research and development panel discussion at The ConFab 2014 started on that optimistic note as Moderator Scott Jones of AlixPartners led a discussion on Optimizing R&D Collaboration. Panelists Chris Danely of JP Morgan, Lode Lauwers of imec, Rory McInerney of Intel and Mike Noonen of Silicon Catalyst discussed where the next big growth drivers will come from and the ability of the industry to continue scaling and remain on Moore’s Law through the introduction of new technologies such as EUV, Advanced Packaging and 450mm. The panel also touched on the role startups will play and how increased collaboration can benefit the industry.

Here are highlights from Monday’s discussion.

How do you feel about the semiconductor cycle – is that at a positive point for innovation and small, start-up companies?

Mike Noonen: I feel the best about I’ve felt about semi since 2009. Without a doubt. When you combine that situation that we’re in with a couple driving forces, all of that has fundamental benefits to the semiconductor business at large. You take those mega trends that are not leading edge applications with the challenge of Moore’s Law – those are developing a whole host of innovation. We think this is a great time to think about how to reinvigorate startups – this is the best time to think about innovation.

From left to right: Panelists Chris Danely of JP Morgan, Mike Noonen of Silicon Catalyst, Lode Lauwers of imec, and Rory McInerney of Intel

From left to right: Panelists Chris Danely of JP Morgan, Mike Noonen of Silicon Catalyst, Lode Lauwers of imec, and Rory McInerney of Intel

Consolidation is a big theme right now. Is this something that’s holding us back the industry?

Rory McInerney: I don’t think the industry is consolidating for us as much as we think. The big players are still HP, Lenovo, etc. The new players are Google, Facebook, Amazon, etc. – many didn’t exist 10 years ago. Within our world, there’s the traditional space, but there’s a ton of new stuff in the cloud and server segment.

Tell us some of the most exciting areas Intel is participating in.

Rory McInerney: On the data center side, we do want our 10 and 7nm, but one of the drivers of our business is the massive amount of data being generated around the world. There are tens of billions of devices that will be connected to the Internet in the few years. The only commonality in the [IoT] numbers is that they go up. All of them will have some element of connectivity and with that comes data. And that drives a virtual cycle. In our business, we love this – my point is, there’s a huge room for innovation. The innovation isn’t just the device but the software and application side.

How do investors view the emerging markets and trends? Do they see the opportunities or are they still focusing on traditional markets?

Chris Danely: From a broad perspective, the thing that an analyst looks at – are they playing to their strengths? You might have a company that starts out very successful, but they don’t play to their strengths and start to waste money. For example, Texas Instruments has taken their R&D down, but still outgrow the industry, because they play to their strengths. Another example is Intel – in the last 3 years, they were in the foundry business – we see a lot of potential to upset the apple cart in the foundry business. Nobody else could do this, but this is an area where we see them exploiting their strengths. Is the company playing to its strengths? We also look at ARM on servers – we don’t know if this is going to work or not, but I don’t think this changing the landscape of the industry. There’s still a bright future with semiconductor stocks.

How can executives communicate their R&D strategy better?

Chris Danely: I’ll use my personal experience – you want to keep that message very simple. Identify the growth trends. Make sure the message goes out continuously. Don’t be afraid to use a few buzz words/charts.

Lode Lauwers: If I may, Wall Street is looking in the short term. Time scale [for R&D] is close to 15 years. I don’t know if Wall Street has that visibility. I think a company should consider R&D as a long term investment. We go for long term engagements.

Rory McInerney: It’s a portfolio question in terms of R&D – you’re going to have your short term and your long term investments. I don’t think Wall Street is looking at all the details of investments. I think that our investments on the product side go out 10 years, but they’re small compared to our other investments.

Chris Danely: Wall Street has to consider about things on a six month basis.

Mike Noonen: Biotech, which has a very long time to market, is the second largest venture capital in the US. Biotech has remained lucrative and interesting in the US. In this area, companies go after a single application or problem, and it’s a vibrant and healthy investment. The take away is – it’s all about the economics. It might enable small start ups to innovate and then be acquired.

How should the industry leverage a company like imec?

Lode Lauwers: More than ever, you need to build partnerships. In this industry, we used to say, “Our company can work on its own.” Now, your ecosystem needs to become wider. Ten years ago, people were still sponsoring R&D. Now we are assessed in every individual area, deliverable by deliverable, on does it benefit, is there ROI. You need to be able to deliver relevant work. A company on its own doesn’t always have these abilities in house. Using imec, it’s like building on competences.

Do you see differences in how you approach partnerships?

Chris Danely: The CEOs and CFOs of semi companies are under pressure to not increase expenses, and that’s stifled risk-taking. Some are now approaching R&D through acquisition of startups with personnel – rather than partnerships.

Do you think these companies are larger – semi is a part of a much larger landscape – do you think this might drive the industry/change the landscape?

Rory McInerney: About 70-80 percent of cloud computing today is driven by the social media. That didn’t exist 5 years ago. There is a direct link between that and the changing semi landscape.

What is the biggest risk in the industry right now?

Chris Danely: Saturation. Semi companies are profitable, but we’re starting to see a lot of them, especially as fablite and fabless models are catching on.

Moderator Scott Jones of AlixPartners

Moderator Scott Jones of AlixPartners

SPTS Technologies, a manufacturer of etch, deposition and thermal processing equipment for the semiconductor industry, today announced that it has signed an agreement with CEA-Leti in Grenoble, France, to develop 3D-TSV technologies.

The two-year agreement enters under the framework of the Nanoelec Research Technology Institute program which is led by CEA-Leti, and covers co-development of a range of deposition processes for next-generation 3D high aspect ratio through-silicon-via (TSV) solutions. The agreement builds on the long established relationship between the partners who have already collaborated in the past, particularly on the development and optimization of an advanced MOCVD TiN barrier for high aspect ratio TSV.

3D packaging of semiconductor devices, using TSVs to connect stacked die, is accepted as a critical technology to deliver industry performance goals without exceeding power budgets. To scale future 3D devices, new techniques will be needed to manufacture TSV’s of smaller diameter and higher aspect ratio than are used today.  Under this agreement, SPTS and CEA-Leti aim to develop production worthy solutions to address these challenges. Previous collaboration has resulted in a number of key advancements in the formation of TSVs using SPTS’ deep reactive ion etch (DRIE), chemical vapor deposition (CVD) and physical vapor deposition (PVD). One of the key achievements includes optimization of an advanced metal organic chemical vapor deposition (MOCVD) TiN barrier for high aspect ratio TSV.

“The results previously achieved keeps SPTS at the forefront of 3D-TSV development,” said Kevin Crofton, president and chief operating officer of SPTS. “In partnership with CEA-Leti, we plan now to develop technology and processes that will further extend TSV aspect ratios beyond 20:1, with a particular focus on developing an MOCVD copper process as a seed layer to replace ionized PVD.”

“The work with SPTS and other partners will create solutions that will be transferred into industry,” said Dr. Laurent Malier, CEO of CEA-Leti and President of the Nanoelec RTI board. “Combining Leti’s integration expertise with the specific process knowledge of successful equipment manufacturers like SPTS enables innovation and allows us to create an optimized, cost-effective process flow for volume manufacturing of 3D-IC devices.”

When it comes to electronics, silicon may one day have to share the spotlight. In a paper recently published in Nature Communications, researchers from the USC Viterbi School of Engineering describe how they have overcome a major issue in carbon nanotube technology by developing a flexible, energy-efficient hybrid circuit combining carbon nanotube thin film transistors with other thin film transistors. This hybrid could take the place of silicon as the traditional transistor material used in electronic chips, since carbon nanotubes are more transparent, flexible, and can be processed at a lower cost.

Electrical engineering professor Dr. Chongwu Zhou and USC Viterbi graduate students Haitian Chen, Yu Cao, and Jialu Zhang developed this energy-efficient circuit by integrating carbon nanotube (CNT) thin film transistors (TFT) with thin film transistors comprised of indium, gallium and zinc oxide (IGZO).

“I came up with this concept in January 2013,” said Dr. Chongwu Zhou, professor in USC Viterbi’s Ming Hsieh Department of Electrical Engineering. “Before then, we were working hard to try to turn carbon nanotubes into n-type transistors and then one day, the idea came to me. Instead of working so hard to force nanotubes to do something that they are not good for, why don’t we just find another material which would be ideal for n-type transistors—in this case, IGZO—so we can achieve complementary circuits?”

Carbon nanotubes are so small that they can only be viewed through a scanning electron microscope. This hybridization of carbon nanotube thin films and IGZO thin films was achieved by combining their types, p-type and n-type, respectively, to create circuits that can operate complimentarily, reducing power loss and increasing efficiency. The inclusion of IGZO thin film transistors was necessary to provide power efficiency to increase battery life. If only carbon nanotubes had been used, then the circuits would not be power-efficient. By combining the two materials, their strengths have been joined and their weaknesses hidden.

Zhou likened the coupling of carbon nanotube TFTs and IGZO TFTs to the Chinese philosophy of yin and yang.

“It’s like a perfect marriage,” said Zhou. “We are very excited about this idea of hybrid integration and we believe there is a lot of potential for it.”

The potential applications for this kind of integrated circuitry are numerous, including Organic Light Emitting Diodes (OLEDs), digital circuits, radio frequency identification (RFID) tags, sensors, wearable electronics, and flash memory devices. Even heads-up displays on vehicle dashboards could soon be a reality.

The new technology also has major medical implications. Currently, memory used in computers and phones is made with silicon substrates, the surface on which memory chips are built. To obtain medical information from a patient such as heart rate or brainwave data, stiff electrode objects are placed on several fixed locations on the patient’s body. With this new hybridized circuit, however, electrodes could be placed all over the patient’s body with just a single large but flexible object.

With this development, Zhou and his team have circumvented the difficulty of creating n-type carbon nanotube TFTs and p-type IGZO TFTs by creating a hybrid integration of p-type carbon nanotube TFTs and n-type IGZO TFTs and demonstrating a large-scale integration of circuits. As a proof of concept, they achieved a scale ring oscillator consisting of over 1,000 transistors. Up to this point, all carbon nanotube-based transistors had a maximum number of 200 transistors.

“We believe this is a technological breakthrough, as no one has done this before,” said Haitian Chen, research assistant and electrical engineering PhD student at USC Viterbi. “This gives us further proof that we can make larger integrations so we can make more complicated circuits for computers and circuits.”

The next step for Zhou and his team will be to build more complicated circuits using a CNT and IGZO hybrid that achieves more complicated functions and computations, as well as to build circuits on flexible substrates.

“The possibilities are endless, as digital circuits can be used in any electronics,” Chen said. “One day we’ll be able to print these circuits as easily as newspapers.”

Zhou and Chen believe that carbon nanotube technology, including this new CNT-IGZO hybrid, could be commercialized in the next five to 10 years.

“I believe that this is just the beginning of creating hybrid integrated solutions,” said Zhou. “We will see a lot of interesting work coming up.”