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Consumer demand and government mandates for electronic systems that improve vehicle performance, that add comfort and convenience, and that warn, detect, and take corrective measures to keep drivers safe and alert are being added to new cars each year. This system growth, along with rising prices for memory components within them, are expected to raise the automotive IC market 18.5% this year to a new record high of $32.3 billion, surpassing the previous record of $27.2 billion set last year (Figure 1), according to IC Insights’ soon to be released Update to the 2018 IC Market Drivers report.  If the forecast holds, it would mark the third consecutive year of double-digit growth for the automotive IC market.

Figure 1

Over the past several years, the global automotive IC market has experienced some extraordinary swings in growth. After increasing 11.5% in 2014, the automotive IC market declined 2.5% in 2015, but then rebounded with solid 10.6% growth in 2016. It is worth noting that the sales decline experienced in 2015 was primarily the result of falling ASPs across all the key automotive IC product categories—microcontrollers, analog ICs, DRAM, flash, and general- and special-purpose logic ICs, which offset steady unit growth for automotive ICs that year.

IC Insights’ recently updated automotive IC market forecast shows the automotive IC market growing to $43.6 billion in 2021, which represents a compound annual growth rate (CAGR) of 12.5% from 2017 to 2021, highest among the six major end-use applications (Figure 2).

Figure 2

Collectively, automotive ICs are forecast to account for only about 7.5% of the total IC market in 2018, although that share is forecast to increase to 9.3% in 2021.  Analog ICs—both general-purpose analog and application-specific automotive analog—are expected to account for 45% of the 2018 automotive IC market, with MCUs capturing 23% share. There are many suppliers of automotive analog devices but a rash of acquisitions among them in recent years has reduced the number of larger manufacturers. Some of the acquisitions that have impacted the automotive analog market include NXP, which acquired Freescale in 2015 and is now itself in the process of being acquired by Qualcomm; Analog Devices, which acquired Linear Technology in March 2017; and Renesas, which acquired Intersil.

By Deb Vogler

This year’s Advanced Lithography TechXPOT at SEMICON West will explore the progress on extreme ultra-violet lithography (EUVL) and its economic viability for high-volume manufacturing (HVM), as well as other lithography solutions that can address the march to 5nm and onward to 3nm. Several session speakers offered their insights into the readiness of EUVL for 5nm and how other lithography solutions will enable 3nm. See the full list of speakers and program agenda at http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.

Diverging viewpoints on EUVL readiness for 5nm

Mike Lercel, Director of Strategic Marketing at ASML

ASML expects its first customer to start volume manufacturing with EUV at the 7nm logic node and the mid-10nm DRAM node in the 2018/2019 timeframe. “EUV will replace the most difficult layers that require multiple patterning, and many layers will continue to be allocated to immersion tools for the foreseeable future,” said Lercel. “For the 5nm logic node, more layers are expected to migrate to EUV.”

Three ASML customers have early-access versions of the next-generation TWINSCAN NXT:2000i for the development of advanced logic and DRAM nodes. “This system delivers 2.0nm cross-matched on-product overlay, achieved through several hardware advancements,” noted Lercel. “It is also significant because this mix-and-match use with EUV features a significantly different hardware platform.” TWINSCAN NXT:2000i features a new alignment sensor and improved wafer table flatness, endurance, and clamping mechanism to enhance matching to EUV.

ASML has achieved good industrialization progress of its pellicle, with tests confirming that pellicles can withstand 245W source power and an offline power lifetime test indicating 400W capability. Compared to the 7nm logic node, the requirements for EUV masks will become tighter at 5nm, but Lercel noted that ASML sees good progress with the industry infrastructure to support 5nm in areas such as reducing mask blank defects. “We will continue to improve pellicle transmission for enhanced throughput, but there are no fundamental changes in pellicle requirements for 5-3nm logic nodes. We see no infrastructure showstoppers for the introduction of EUVL at the 5nm node.”

Stephen Renwick, Director of Imaging Physics at Nikon Research Corporation of America

Renwick said that the 7nm logic node is expected to be fabbed mostly using 193i lithography. “EUV will struggle to be ready for 5nm, limited by yield issues caused by stochastic effects in the resist,” said Renwick. “Ready or not, though, it will be used.” Renwick suggests that introducing multiple-patterning with EUV may be needed but would increase costs. “193i lithography will continue to be used with quadruple-patterning and in combination with other techniques – there is no single solution.”

Figure 1. Normalized cost/layer vs. lithography method. SOURCE: Nikon Research Corporation of America

When choosing between immersion lithography and EUV for different customer segments at 5nm, Renwick noted that the cost depends on the layer. “Some time ago, we calculated that the costs of either 193i triple-patterning or 193i SADP with two cuts were roughly equal to single-patterning with EUV,” explained Renwick (Figure 1). “That agreed with chipmakers’ public estimates and meant that the choice of lithography method depended more on the performance tradeoffs involved, such as 193i’s better line-edge roughness. At the 5nm node, we are probably faced with quad-patterning from 193i, double-patterning from existing EUV tools, or single-patterning from as-yet undelivered high-numerical aperture (NA) EUV tools.” Renwick believes that the competition between low-NA EUV double-patterning and 193i quad-patterning will be similar to the current situation (i.e., comparison of 193i triple-patterning or 193i SADP with two cuts vs. single-patterning with EUV), but for high-NA EUV tools he believes it’s too early to say.

Other challenges Renwick sees on the horizon for EUVL at 5nm are stochastic effects in EUV resists. “They cause yield problems on contact arrays and unacceptable line-edge roughness on line/space patterns,” said Renwick. “It’s unlikely that these effects will go away without increasing the litho dose, which will further challenge throughput performance.” He also questions whether EUV pellicles, though under development, will be “ready for prime time.”

Harry Levinson, Sr. Director of Strategic Lithography Technology and Sr. Fellow at GLOBALFOUNDRIES

Levinson said additional fundamental engineering work is needed to ready EUV lithography for 5nm. “Among the top problems are stochastics-induced resist defects, which increase significantly as dimensions shrink below those for 7nm,” explained Levinson (Figure 2). “Higher exposure doses will be required to address these issues related to stochastics at 5nm, which will require higher source output” (than 7nm).

Levinson said there will be greater motivation to use EUVL at the 5nm node vs. at 7nm to offset the large number of exposures associated with 193nm immersion multiple-patterning solutions. “The primary application of EUV lithography at 7nm will be for contact, via and cut layers,” Levinson noted. “It will be important to enable EUVL for metal masks at the 5nm node, which increases the need for an ample supply of very low defect EUV mask blanks.” Levinson added that the 7nm node is already stressing defect inspection capabilities, and no actinic defect inspection system is yet available for patterned masks. “This situation becomes more problematic with widespread application of EUVL to metal layers.”

Mask development for 5nm

Christopher C. Progler, CTO & Strategic Planning at Photronics

Progler said that the basic infrastructure for delivering EUV masks is available, especially for dark field layers and near in nodes. “The interconnected or more open frame patterns will need refinements to the processes and two to three nodes out will need certain new infrastructure,” said Progler. Overall, the main challenges for initial insertion are about creating a cost-effective and rapid-turn EUV mask process, he said. “The industry can certainly deliver EUV masks in some form. It is more a question of doing it efficiently and productively to match the stated value proposition of EUV over other lithographic methods. We don’t want a pick two of ‘cost, cycle time, capability’ sort of mask solution.”

More specifically, Progler explained that after the initial EUV mask development for 5nm focused on contacts and block layers, the major push for N5 switched to delivering single-exposure EUV metal patterning as early as possible. “This has opened some new challenges for masks given the resolution, critical pattern density and tight pitch defect requirements of the re-aggregated single-layer metal mask designs,” said Progler. “For example, on the resolution side, we are accelerating the insertion of higher dose photoresists and also driving patterning module improvements in CD control, mask LER and sidewall angle.” Progler added that at N5, the mask 3D structure itself – including the sidewall – will have a greater impact on lithography because it is tied to stochastic error rates on the wafer.

“Reliable, wide-area metrology for some of these 2D and 3D mask parameters is currently hard to come by. We may see an evolution of the blank structure at some point in N5, including hard mask options for pattern stability and expect earlier insertion of EUV mask process correction with model-based hot spot detection and rule checking as well. We also hope mask-scanner dedication is not needed, but there are some indications process sensitivity may push us earlier in this direction.” He added that to reduce metal layer defects, more attention needs to be devoted to advanced repair and model-based validation. “We are, unfortunately, still in a situation of blurry vision and high native defect counts alongside possible in situ contamination during mask changes.”

Figure 2. Resist stochastics-induced defects. Graph courtesy of Peter DeBisschop, imec; Source: GLOBALFOUNDRIES

Progler pointed out that, with the advent at 5nm, metal masks will require some level of actinic blank inspection for yield, increasing the cost of an already expensive mask technology. “So, unless we want to contend with double and triple photomasks’ starts to deliver a single metal layer, it will be very important to tighten the multi-sensor inspection, defect abatement, and repair loops,” said Progler. He does see some clouds forming around high-volume manufacturing pellicles for metal layers. “This remains an open question, mainly for thermal and materials reasons, not to mention cost and cycle time,” Progler said. “We may be pessimistic, but we do not see an HVM pellicle solution converging in the required timeframe, which means leaning even more on a wafer-level inspection in the validation loop.” He believes that streamlining validation will be a differentiator. “I can imagine one losing most of the EUV cycle time benefits by endlessly circling masks around if this is not done well.”

How does the industry get to 3nm?     

ASML plans to ship its first high-NA EUV prototope/pilot systems between 2020 and 2023 to support 3-2nm process development. “System designs are now being finalized and the platform is starting to come to life,” said Lercel. ASML supplier ZEISS is building a high-NA cleanroom for optics production. ASML believes that EUV, high-NA and DUV systems will be used together at the most advanced nodes and is designing to account for this mixed environment. “As chipmakers drive toward smaller geometries in the most advanced nodes like 3nm, they face unprecedented challenges in devices and materials. This will make the process control requirements even more challenging.” ASML is tackling these challenges with its YieldStar metrology platform, e-beam metrology (HMI) and computational lithography solutions that are designed to expand the process window, enhance process control, and improve patterning defect detection. “This ‘Holistic Lithography’ approach will become increasingly important to ensure throughput and yield at the most advanced nodes.”

Levinson said that the issues he projects for 5nm will need to be addressed further at 3nm. “The challenges associated with resists at 3nm dimensions are such that it isn’t clear that chemically amplified resists will be capable of meeting requirements,” said Levinson. “If true, we would be seeing the most significant change in resist platforms in a quarter of a century. Potentially cost-reducing technologies such as directed self-assembly (DSA) are always welcome, but EUVL will be the lithographic workhorse through the 3nm node, and likely beyond.”

At 3nm, mask makers will confront the realities of higher EUV NA tools. “We will need to implement thinner mask absorbers, new films, and perhaps hard masks,” Progler said. “This puts us in a new materials regime for masks, and history has shown us the mask industry takes a long time to refine processes and tools for new mask materials.” He explained that the small scale of the mask ecosystem and the small number of large suppliers available to address the challenges accounts for this lengthy time frame.

Still, looking ahead, Progler noted that Photronics has already done a few studies on the impact of proposed half-field, high NA anamorphic optics on masks. “We uncovered some challenges that need to be addressed, particularly at boundaries and within the overall mask flow,” said Progler. As mask resolution continues to scale down, the industry will need fundamentally higher resolution mask making and inspection processes, requiring next-generation multi-beam mask writing and electron beam inspection, he explained.

At 3nm and below, Progler noted that the metrology needs for masks, while not as severe as that for wafers at these nodes, will test the mask equipment infrastructure in ways that could challenge the relatively small mask industry. “Of course, EUV multi-patterning comes into play as well, and with that, the SRAF sizes will drop below 20nm, requiring an asymmetric compensation over a much wider influence area than the OPC people are used to considering.” With EUV multi-patterning, Progler explained that it will be increasingly important to match or pair EUV masks and to consider how 3D effects and stochastics will drive new technology to enable new requirements for high-speed metrology and simulation components. “All the justifiable hand-wringing over EPE with ArF multi-patterning today gets introduced to the EUV scene when masks are ganged together to make a single device layer,” said Progler.

Originally published on the SEMI blog.

A new class of adsorbent materials offer high capacity storage and safe delivery of dopant gases

BY J. ARNÓ, O.K. FARHA, W. MORRIS, P. SIU, G.M. TOM, M.H. WESTON, and P.E. FULLER, NuMat Technologies, Skokie, USA J. MCCABE, M. S. AMEEN, Axcelis Technologies, Beverly, MA

Metal-Organic Framework (MOF) materials are a new class of crystalline adsorbents with broad applicability in electronics materials storage, delivery, purification, and abatement. The adsorbents have unprecedented surface areas and uniform pore sizes that can be precisely customized to the specific properties of electronic gases. ION-X® is a sub-atmospheric dopant gas delivery system designed for ion implantation, and the first commercial product that uses MOFs (ION-X® is commercially available through an agreement between NuMat Technologies and Versum Materials). The performance of ION-X deliv- ering arsine (AsH3), phosphine (PH3), and boron triflu- oride (BF3) was evaluated in high current implanters at the Axcelis Advanced Technology Center and compared to the incumbent delivery systems. In-process and on-wafer results of the MOF-based dopant gases compared positively to conventional source gases. Flow, pressure, and beam stability were undistinguishable from conven- tional gas sources throughout the lifetime of the cylinder. Beam and wafer contamination levels (both surface and energetic) were below specification limits, matching the performance of the reference qualified products.

Dopant gas safety challenges

The storage and delivery of hazardous gases creates signif- icant environmental, health, and safety challenges. Their usage requires implementation of stringent safety control systems to minimize the risks of exposure to humans and the environment. The dangers associated with handling toxic gases are the result of both the inherent chemical hazard of the molecule and the kinetic energy stored in the vessel in the form of compression. In essence, the lethality of a toxic release is magnified exponentially by the energetic force of the high-pressure storage. Historically, one way to mitigate these risks was to dilute the hazardous material with inert gases in an effort to attenuate the toxicity effects. Depending on the concentration, this solution provides a safety factor improvement of 10 or 100 by virtue of reducing the molecular density of the hazardous gas to 10% or 1% mixtures, respectively. This approach is commonly used in the electronics manufacturing industry for gases that are known to have extreme toxicity. Hydride gases (i.e. arsine, phosphine, germane, or diborane) are examples of such highly toxic gases used as source materials in a number of electronic manufacturing processes. While this dilution method is effective at reducing the toxicity levels, these mixtures are typically produced at cylinder pressures significantly higher than the pressures of the pure toxic gases. In a release event, this solution reduces the lethality of the dose at the expense of a higher release rate.

In 1993, ATMI (now an Entegris company) introduced a different approach to reduce the toxic gas storage hazards [1]. The technology involves using nano-porous adsor- bents to condense the gas molecules onto their surfaces. This process effectively reduces the kinetic energy of the gas, thus reducing the pressure in the gas cylinder. The large available surface areas within these materials result in gas storage capacities comparable to the high-pressure cylinders. The intrinsic safety advantages of adsorbed gas cylinders are derived from the reduction in pressure within the cylinder. Typically, these vessels are filled to sub-atmospheric pressures (measured at room temperature) in order to inhibit an outward gas release in the event of a leak.

The first sub-atmospheric dopant gas delivery systems used zeolites (SDS® 1) while the second and third genera- tions (SDS® 2 and SDS® 3) evolved to activated carbon adsorbent materials. These gas cylinders store and deliver dopant precursor gases (primarily arsine, phosphine, and boron trifuoride) predominantly for ion implantation processes. In its third generation, and in order to further improve gas storage capacities, SDS 3 evolved by creating a highly dense monolithic adsorbent that nearly eliminated void volumes in the cylinder.

In this paper, we describe a new sub-atmospheric gas delivery system (ION-X ®) that uses a novel ultra-high surface area class of materials called metal-organic frame- works (MOFs). In addition, the implant process perfor- mance using the new product delivering arsine, phosphine, and boron trifluoride was evaluated in a major ion implant OEM facility will be described.

MOF overview: The next generation in nano- porous adsorbents

MOF are three-dimensional crystalline structures assembled with metal-containing nodes connected by organic links (FIGURE 1). The resulting highly organized molecular structures generate nano-pores with record surface areas [2-4]. In addition, the large number of available metal nodes and organic linkers provide unpar- alleled molecular design flexibility to tailor the chemical and physical properties of the adsorbent material to fit the application. Since their discovery in the early 1990’s, MOFs have evolved from an academic curiosity to a widely recognized new class of materials with practical applications in energy, specialty chemicals, military, medical, pharmaceutical, and electronics industries. MOFs are one of the fastest growing classes of materials, with thousands of experimental structures now being reported.

For gas storage and delivery applications, MOFs’ design flexibility provides advantages over traditional adsorbents (FIGURE 2). Pore size, surface area, and chemical stability can be tailored to the specific properties of the adsorbed gases. Compared to zeolites and activated carbon adsorbents, MOFs have significantly larger surface areas (up to 7,000m2/g has been reported[5]. This property, combined with bulk density, is critical in gas storage applications where capacity is measured in terms of vessel volume rather than adsorbent mass. Pore size tunability is also an important parameter in efforts to match the dimensions of the MOF cavities to the molecular sizes of the target adsorbates. This parameter impacts adsorption capacities (how much gas can be loaded) and desorption characteristics (how much can be delivered as a function of pressure). Unlike the broad pore size distributions found in activated carbon adsorbents, MOFs’ crystallinity results in more “usable” pores. This pore size uniformity also results in higher gas quality, as impurities are selectively size excluded.

Preventing reactions between the adsorbent and the target gas is extremely important in electronics applications. Adsorbent/gas interactions will contribute to gas decomposition, leading to impurities and unwanted dopant gas composition changes that could affect the process. The molecular composition of zeolites and carbon adsor- bents are limited to a few elements (typically carbon, aluminum, and silicon) and their oxides. MOFs, on the other hand, can be synthetized from a large range of organic and inorganic constituents, offering more options for creating stable gas/ adsorbent interactions.

MOF-based gas delivery system for ion implant gases ION-X (FIGURE 3) is a sub-atmospheric dopant gas storage and delivery system designed for ion implantation [6]. ION-X uses individual MOF structures with tailored pore sizes to effectively and reversibly adsorb arsine, phosphine, and boron trifluoride gases. The pressure in filled ION-X cylinders is below one atmosphere, significantly reducing the health and environmental impact of an accidental gas release. Furthermore, MOFs’ ultra-high surface areas and uniform structures provide capacity and deliverable advantages compared to existing carbon adsorbent-based products (FIGURE 4). It is important to note that the first-generation ION-X cylinders utilize granulated MOFs with similar adsorbent bulk density to the first-generation carbon product: for the same mass of adsorbent, MOFs provide 40% to 55% higher gas delivery by virtue of their superior surface area and pose size uniformity. Analogous to the evolution of SDS®2, MOF densification inside the cylinder will further increase the gas capacity in next-generation ION-X products.

Implant performance characterization

The performances of ION-X dopant delivery systems were recently evaluated using a PurionH 300 mm high current ion implanter at Axcelis’ Advanced Technology Center (Beverly, MA, USA). The test plan included flow, mass spectral, and metal contamination analyses (both at the surface and at implanted depth). The experiments were repeated using commercially available and well-estab- lished sub-atmospheric dopant gas sources in order to provide a basis for comparison.

Cylinder installation and setup was seamless, requiring no modifications to the existing gas box hardware or software. Flow rate stability for all three gases (AsH3, PH3, and BF3) was demonstrated in the 3.5 to 8 sccm ranges down to cylinder pressures of 20 torr (spec limit). For arsine, the flow experiment continued through a full cylinder depletion, showing a stable flow rate down to cylinder pressure below 3 torr.

The beam energy, purity, and stability were evaluated by analyzing the mass spectra generated during the implantation processes. In all cases, the target dose was 5 x 1015 at/cm2 with beam energies of 40 keV, 20 keV and 15 keV for As+, P+, and BF¬2+ ion implants respectively. The stability and purity of the target doping ion beams were within specifications and very similar to the ones produced by the reference gas sources. Based on the mass spectra, ION-X did not generate any impurities derived from either gas or MOF decomposition.

Neutral and energetic metal contamination levels were thoroughly investigated in this study. All metal analyses were performed by sampling wafers produced using the recipes described in the previous paragraph. Vapor Phase Decomposition-inductively coupled Plasma-Mass Spectrometry (VPD-ICP-MS) was used to monitor the contamination from key trace metals at the wafer surface. Particular attention was placed on monitoring zinc and iron, metals used in the hydride and BF3 ION-X MOF adsorbents respectively. Results show that all metal levels were within specification limits and compared well to the levels detected in control wafers. In all cases, zinc and iron surface contamination levels were below their corresponding detection limits of 0.03 and 0.05 x 1010 atoms/cm2.

Energetic metal contamination is of special interest in ion implantation as even low levels of impurities could affect the performance of the electronic devices. The depth profile of the metals used in ION-X’s MOFs composition were measured using Secondary Ion Mass Spectrometry (SIMS). Wafers used for SIMs analyses were doped using both ION-X and incumbent gas sources using the same ion implant tool and previously stated recipes. The zinc and iron metal concentration profiles for the hydride and boron implants were well within specifications and show no discernable differences between the incumbent and the MOF-based gas sources (FIGURE 5). These results, combined with the previous surface contamination tests, conclusively establish the gas and ion purity of the dopant species extracted from ION-X adsorbents. Moreover, the results are consistent with extensive gas analyses performed at NuMat after subjecting the MOF adsorbent materials to accelerated aging, vibration, and cycle testing.

Summary

This article provides process and on-wafer performance of ION-X, a new MOF-based dopant gas delivery system. The adsorbents used in these cylinders have surface areas, stability, purity, and pore sizes ideal for the storage and delivery of ion implant dopant gases. In-process and on-wafer performance of boron trifluoride, arsine, and phosphine dopant sources compared positively to conven- tional source gas cylinders. The issue of contamination was investigated in detail, demonstrating that the new adsorbents do not contribute to surface or energetic metal impurities. The results published in this article provide independent evaluation of the new product, supporting the safe use of this product in mainstream ion implant applications. To that end, ION-X is already qualified and being used at an electronics manufacturing site with confirmed high stability and purity performance.

References

  1. Olander, K. and Avila, A., “Subatmospheric Has Storage and Delivery: Past, Present, and Future”, Solid State Technology, Volume 57 (2014), pp 27-302.
  2. Y. Cui, B. Li, H. He, W. Zhou, B. Chen, and G. Qian, “Metal–Organic Frameworks as Platforms for Functional Materials,” Accounts of Chemical Research, vol. 49, pp. 483-493, 2016/03/15 2016.
  3. H. Furukawa, K. E. Cordova, M. O’Keeffe, and O. M. Yaghi, “The Chemistry and Applications of Metal-Organic Frameworks,” Science, vol. 341, 2013.
  4. P. Silva, S. M. F. Vilela, J. P. C. Tome, and F. A. Almeida Paz, “Multifunc- tional metal-organic frameworks: from academia to industrial applications,” Chemical Society Reviews, vol. 44, pp. 6774-6803, 2015.
  5. Omar K Farha et al., “Metal-Organic Framework Materials with Ultrahigh Surface Areas: Is the Sky the Limit?” J. Am. Chem. Soc. (2012), Vol. 134, pp 15016−15021
  6. G. M. Tom et al., “Utilization of Metal-Organic Frameworks for the Management of Gases Used in Ion Implantation”, 2016 21st International Conference on Ion ImplantationTechnology (IIT),Tainan, 2016, pp. 1-4.

Memory devices employ a wide range of packaging technology from wire-bond leadframe and BGA to TSV.

BY SANTOSH KUMAR, Yole Développement, Lyon-Villeurbanne, France

The memory market is going through a strong growth phase. The total memory market grew by >50% YoY to more than US$125 billion in 2017 from US$79.4 billion in 2016. [1] RAM and NAND dominate the market, representing almost 95 % of standalone memory sales. There is a supply/demand mismatch in the market which is impacting on the ASP of memory devices, and as a result the large memory IDMs are reaping record profits. The memory industry has consolidated with the top five players – Samsung, SKHynix, Micron, Toshiba and Western Digital – accounting for 90% of the market.

The demand for memory is coming from all sectors but the mobile and computing (mainly servers) market is showing particularly strong growth. On average, the DRAM memory capacity per smartphone will rise more than threefold to reach around 6GB by 2022. DRAM cost per smartphone represents >10% of the bill of materials of the phone and is expected to increase further. The NAND capacity per smartphone will increase more than fivefold to reach >150GB by 2022. For servers, the DRAM capacity per unit will increase to a whopping 0.5TB by 2022, and the NAND capacity per SSD for the enterprise market will be in excess of 5TB by 2022. The growth in these markets is led by applications like deep learning, big-data, networking, AR/ VR, and autonomous driving. The automotive market, which traditionally used low density (low-MB) memory, will see the adoption of DRAM memory led by the emerging trend of autonomous driving and in-vehicle infotainment. The NOR flash memory market also saw a resurgence and is expected to grow at an impressive 16% CAGR to reach ~US$4.4 billion by 2022, due to its application in new areas such as AMOLED displays, touch display driver ICs and industrial IoTs.

On the supply side, the consolidation of players, the difficulty in migrating to advanced nodes due to technical challenges, and the need for higher investment to migrate from 2D to 3D NAND, has led to shortfall in both DRAM & NAND flash supply. DRAM players want to retain high ASPs (& high profitability) to justify the huge capex investment for advanced node migration and as such are not inclined to increase capacity. Entry of Chinese memory players will ease the supply side constraint, but it’ll not happen before 2020.

Memory device packaging

There are many variations of memory device packaging. This implies a wide range of packaging technology from the low pin count SOP package to the high pin-count TSV, all depending upon the specific product requirements such as density, performance, cost, etc. We have broadly identified five packaging platforms for memory devices: viz lead frame, wire-bond BGA, flip-chip BGA, WLCSP and TSV, even though in each platform there are many varia- tions and different nomenclature in industry.

The total memory package market is expected to grow at 4.6% CAGR2016-2022 to reach ~US$26 billion by 2022. [1] Wire-bond BGA accounted for more than 80% of the packaging market in dollar terms in 2016. Flip-chips, however, started making inroads in the DRAM memory packaging market and is expected to grow at ~20% CAGR in the next five years to account for more than 10% of the memorypackagingmarket.Currentlytheflip-chipmarket is only around 6% of the total memory packaging market. Flip-chip growth is led by its increased adoption in the DRAM PC/server segment fueled by a high bandwidth requirement.

Currently Samsung has already converted >90% of its DRAM packaging line. SK Hynix have started the conversion and other players will also adopt it in future. At Yole Développement (Yole), we believe that all DDR5 memory for PC/servers will move to flip-chip.

TSV is employed in high bandwidth memory devices requiring high bandwidth with low latency memory chips for high performance computing in various applications. In 2016 the TSV market was <1% of the total memory market. However, it is expected to grow by >30% CAGR to reach ~8% of memory packaging in dollar terms. WLSCP packaging is used in NOR flash and niche memory devices (EEPROMs/EPROM/ROM). It is expected to grow at >10% CAGR, but in terms of value will remain <1% of the market by 2022.

In mobile applications, memory packaging will mainly remain on the wire-bond BGA platform but will start to move into the multi-chip package (ePoP) for high end smartphones.

The main requirement of NAND flash devices is high storage density at low cost. NANDs are stacked using wire bonding to provide high density in a single package. The NAND packaging market is expected to reach ~ US$ 10 billion by 2022. NAND flash packaging will remain on the wire bond BGA platform and will not migrate to flip-chip. Toshiba, however, will start using TSV packaging in NAND devices to increase the data transfer rate for high end applications. Following Toshiba, we believe Samsung and SKHynix will also bring TSV packaged NAND devices into the market.

OSATs account for <20% of the memory packaging business

The total memory packaging market is estimated to have been ~US$20 billion in 2016. There are many OSATs involved in the memory packaging business, and >80% of the packaging (by value) is still done internally by OSATs. The majority of these are small OSATs and have only low-end packaging capability. Global memory IDMs have much experience in packaging, accumulated over years, and have their own internal large capacity. Therefore, there is limited opportunity for OSATs to make inroads into the packaging activity of IDMs. Many Chinese players, however, are entering the memory market with more than US$50 billion investment committed. [1] These new entrants do not have experience in memory assembly / packaging, unlike global IDMs, and they will outsource major packaging activities to OSATs. The flip-chip business for memory packaging will increase to 13% of the total market to reach US$3.5 billion in 2022. This is an opportunity for low-end memory OSATs to invest in flip-chip bumping and assembly capacity. Otherwise they will lose business to the big OSATs with advanced packaging capability.

Conclusion

The memory industry is going through a golden phase with strong demand coming from all sectors, particularly from the mobile and computing (mainly servers) markets.

Memory devices employ a wide range of packaging technology from wire-bond leadframe and BGA to TSV. Wire-bond BGA still accounts for the bulk of the memory packaging market. However, flip-chip technology will start making inroads in DRAM memory packaging and will grow at 20% CAGR (by revenue) over the next five years, accounting for ~13% of the total memory packaging market by 2022. The memory packaging market is mainly controlled by IDMs. OSATs have limited opportunity to impact IDM packaging activity. Many Chinese players, however, are entering the memory business and, unlike global IDMs, these new players lack experience in memory assembly/packaging and they outsource most of their packaging activity to OSATs.

SANTOSH KUMAR is a Senior Technology and Market Research Analyst at Yole Développement in France.

References

1. Memory Packaging Market and Technology Report 2017, Yole Développement

IC Insights recently released its May Update to the 2018 McClean Report.  This Update included a look at the top-25 1Q18 semiconductor suppliers, a discussion of the 1Q18 IC industry market results, and an update of the 2018 capital spending forecast by company.

Overall, the capital spending story for 2018 is becoming much more positive as compared with the forecast presented in IC Insights’ March Update to The McClean Report 2018 (MR18).  In the March Update, IC Insights forecast an 8% increase in semiconductor industry capital spending for this year. However, as shown in Figure 1, IC Insights has raised its expectations for 2018 capital spending by six percentage points to a 14% increase.  If this increase occurs, it would be the first time that semiconductor industry capital outlays exceeded $100 billion.  The worldwide 2018 capital spending forecast figure is 53% higher than the spending just two years earlier in 2016.

Although Samsung says it still does not have a full-year capital spending forecast for this year it did say it will spend “less” in semiconductor capital outlays in 2018 as compared to 2017, when it spent $24.2 billion.  However, as of 1Q18, with regard to its capex, its “foot is still on the gas!”  Samsung spent $6.72 billion in capex for its semiconductor division in 1Q18, slightly higher than the average of the previous three quarters.  This figure is almost 4x the amount the company spent just two years earlier in 1Q16!  Over the past four quarters, Samsung has spent an incredible $26.6 billion in capital outlays for its semiconductor group. Wow!

IC Insights has estimated Samsung’s semiconductor group capital spending will be $20.0 billion this year, $4.2 billion less than it spent in 2017.  However, given the strong start to its spending this year, it appears there is currently more upside than downside potential to this forecast.

With the DRAM and NAND flash memory markets still very strong, SK Hynix is expected to ramp up its capital spending this year to $11.5 billion, 42% greater than the $8.1 billion it spent in 2017. The increased spending by SK Hynix this year will primarily focus on bringing on-line two large memory fabs—M15, a 3D NAND flash fab in Cheongju, South Korea and its expansion of its huge DRAM fab in Wuxi, China.  The Cheongju fab is being pushed to open before the end of this year.  The Wuxi fab is also targeted to open by the end of this year, a few months earlier than its original planned start date of early 2019.

Figure 1

After strong year-over-year growth of 24% in 2017, worldwide semiconductor revenue is forecast to grow for the third consecutive year in 2018 to $450 billion, up 7.7% over 2017, according to a new Semiconductor Applications Forecaster (SAF) from International Data Corporation (IDC). The SAF also forecasts that semiconductor revenues will log a compound annual growth rate (CAGR) of 2.9% from 2017-2022, reaching $482 billion in 2022.

The overall memory market was the key story of last year, due to strong demand, limited supply, and product mix constraints. The DRAM and NAND memory markets grew to $73 billion and $49 billion respectively, reflecting year-over-year growth rates of 77% and 52% for 2017. Excluding DRAM and NAND, the overall semiconductor market grew by 12% year over year. For 2018, non-memory semiconductors are forecast to grow $11 billion to $302 billion. Both DRAM and NAND will continue to grow this year, but are expected to decline from 2019-2021 before recovering slightly in 2022.

The strong memory market resulted in Samsung Electronics capturing the top semiconductor manufacturer spot away from Intel and raised the profile of all the memory manufacturers, which now represent three of the top five semiconductor companies compared to only two the previous year. Revenue concentration continued to increase for the overall market with the top 10 companies making up 60% of the semiconductor market compared to 56% in 2016 and 53% in 2015.

“Market consolidation in the semiconductor industry over the past five years continues to shape the competitive landscape for semiconductor suppliers as each company continues to refine its core markets and make acquisitions to find new and emerging sectors for growth. The pace of change and technology is expected to accelerate as machine learning and autonomous systems enable a more diverse set of architectures to address the opportunity. This will fuel the engine of growth for semiconductor technology over the next decade,” said Mario Morales, program vice president, Semiconductors at IDC.

The automotive market and the industrial markets will continue to be the leading areas of growth for the semiconductor market throughout the forecast period, growing at a 9.6% and 6.8% CAGR from 2017-2022. “The key drivers of electrification, connectivity and infotainment, advanced driver assistance (ADAS), and autonomous driving features will continue to drive the growth of semiconductor content on a per vehicle basis,” said Nina Turner, research manager for Semiconductors at IDC.

Other key findings from IDC’s Semiconductor Application Forecaster (excluding memory) include:

  • Semiconductor revenue for the computing industry segment will decline 4.0% this year and will show a negative CAGR of -0.7% for the 2017-2022 forecast period. Two bright spots for the computing segment are computing and enterprise SSDs, growing in high double digits and 9.8% CAGR respectively for 2017-2022.
  • Semiconductor revenue for the mobile wireless communications segment will grow 5.5% year over year this year with a CAGR of 5.8% for 2017-2022. Semiconductor revenue for 4G mobile phones will experience an annual growth rate of 10.9% in 2018 and a CAGR of 3.1% for 2017-2022. 5G will also drive growth in the later part of the forecast as the technology becomes mainstream by the middle of the next decade.
  • Communications infrastructure semiconductors are forecast to grow at a 1.7% CAGR from 2017-2022 with the strongest growth coming from consumer networks.

By Walt Custer, Custer Consulting Group

Broad global & U.S. electronic supply chain growth

The first quarter of this year was very strong globally, with growth across the entire electronics supply chain. Although Chart 1 is based on preliminary data, every electronics sector expanded –  with many in double digits. The U.S. dollar-denominated growth estimates in Chart 1 have effectively been amplified by about 5 percent by exchange rates (as stronger non-dollar currencies were consolidated to weaker U.S. dollars), but the first quarter global rates are very impressive nonetheless.

Walt Custer Chart 1

U.S. growth was also good (Chart 2) with Quarter 1 2018 total electronics equipment shipments up 7.2 percent over the same period last year. Since all the Chart 2 values are based on domestic (US$) sales, there is no growth amplification due to exchange rates.

Walt Custer Chart 2

We expect continued growth in Quarter 2 but not at the robust pace as the first quarter.

Chip foundry growth resumes

Taiwan-listed companies report their monthly revenues on a timely basis – about 10 days after month end. We track a composite of 14 Taiwan Stock Exchange listed chip foundries to maintain a “pulse” of this industry (Chart 3).

Walt Custer Chart 3

Chip foundry sales have been a leading indicator for global semiconductor and semiconductor capital equipment shipments. After dropping to near zero in mid-2017, foundry growth is now rebounding.

Chart 4 compares 3/12 (3-month) growth rates of global semiconductor and semiconductor equipment sales to chip foundry sales. The foundry 3/12 has historically led semiconductors and SEMI equipment and is pointing to a coming cyclical upturn. It will be interesting to see how China’s semiconductor industry buildup impacts this historical foundry leading indicator’s performance.

Walt Custer Chart 4

Passive Component Shortages and Price Increases

Passive component availability and pricing are currently major issues. Per Chart 5, Quarter 1 2018 passive component revenues increased almost 25 percent over the same period last year. Inadequate component supplies are hampering many board assemblers with no short-term relief in sight.

Walt Custer Chart 5

Peeking into the Future

Looking forward, the global purchasing managers index (a broad leading indicator) has moderated but is still well in growth territory.

Walt Custer Chart 6

The world business outlook remains positive but requires continuous watching!

Walt Custer of Custer Consulting Group is an  analyst focused on the global electronics industry.

Originally published on the SEMI blog.

IC Insights will release its May Update to the 2018 McClean Report later this month.  This Update includes a discussion of the 1Q18 IC industry market results, an update of the 2018 capital spending forecast by company, and a look at the top-25 1Q18 semiconductor suppliers (the top-15 1Q18 semiconductor suppliers are covered in this research bulletin).

The top-15 worldwide semiconductor (IC and O-S-D—optoelectronic, sensor, and discrete) sales ranking for 1Q18 is shown in Figure 1.  It includes eight suppliers headquartered in the U.S., three in Europe, two in South Korea, and one each in Taiwan and Japan.  After announcing in early April 2018 that it had successfully moved its headquarters location from Singapore to the U.S. IC Insights now classifies Broadcom as a U.S. company.

The top-15 ranking includes one pure-play foundry (TSMC) and four fabless companies.  If TSMC were excluded from the top-15 ranking, Taiwan-based fabless supplier MediaTek ($1,696 million) would have been ranked in the 15th position.

IC Insights includes foundries in the top-15 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted.  With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers.  As shown in the listing, the foundries and fabless companies are identified.  In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

Overall, the top-15 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

Figure 1

Figure 1

In total, the top-15 semiconductor companies’ sales surged by 26% in 1Q18 compared to 1Q17, six points higher than the total worldwide semiconductor industry 1Q18/1Q17 increase of 20%.  Amazingly, the Big 3 memory suppliers—Samsung, SK Hynix, and Micron, each registered greater than 40% year-over-year growth in 1Q18. Fourteen of the top-15 companies had sales of at least $2.0 billion in 1Q18, four companies more than in 1Q17. As shown, it took just over $1.8 billion in quarterly sales just to make it into the 1Q18 top-15 semiconductor supplier list.

Intel was the number one ranked semiconductor supplier in 1Q17 but lost its lead spot to Samsung in 2Q17 as well as in the full-year 2017 ranking, a position it had held since 1993.  With the continuation of the strong surge in the DRAM and NAND flash markets over the past year, Samsung went from having 5% less total semiconductor sales than Intel in 1Q17 to having 23% more semiconductor sales than Intel in 1Q18!

It is interesting to note that memory devices represented 83% of Samsung’s semiconductor sales in 1Q18, up six points from 77% in 1Q17 and up 12 points from 71% just two years earlier in 1Q16.  Moreover, the company’s non-memory sales in 1Q18 were only $3,300 million, up 6% from 1Q17’s non-memory sales level of $3,125 million.

As would be expected, given the possible acquisitions and mergers that could occur this year (e.g., Qualcomm/NXP), as well as any memory market volatility that may develop, the top-15 ranking is likely to undergo a significant amount of upheaval over the next few years as the semiconductor industry continues along its path to maturity.

Reaching their highest recorded quarterly level ever, worldwide silicon wafer area shipments jumped to 3,084 million square inches during the first quarter 2018, a 3.6 percent increase over fourth quarter 2017 area shipments of 2,977 million square inches and a 7.9 percent rise over first quarter 2017 shipments, according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

“Global silicon wafer shipment volumes started the year at historic levels,” said Neil Weaver, chairman SEMI SMG and Director, Product Development and Applications Engineering of Shin-Etsu Handotai America. “As a result, silicon shipments, like device shipments, are positioned to be strong this year.”

Silicon* Area Shipment Trends

Millions of Square Inches
1Q 2017
2Q 2017
3Q 2017
4Q 2017
1Q 2018
Total
2,858
2,978
2,997
2,977
3,084

Source: SEMI, May 2018

*Semiconductor applications only

Silicon wafers are the fundamental building material for semiconductors, which, in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release includes polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to end users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

 

By Lung Chu

Lung ChuThe growth of China’s semiconductor industry outstripped sector expansion in many other regions in 2017 thanks in part to heavy government investments and supportive state policies. But China’s chip industry also struggled under the weight of overheated investment, inconsistent project quality, insufficient investment in research and development, a poor ability to innovate, and barriers to international cooperation. To overcome these headwinds to growth, China must identify global trends in the development of global semiconductor industry and better understand the forces it needs to mobilize to further expand its own semiconductor sector.

AI and 5G fuel global semiconductor industry growth

In 2017, global semiconductor industry revenue reached a seven-year peak, expanding 22 percent to nearly USD 420 billion, and entered a new growth phase with artificial intelligence (AI), 5G and other new technologies leading the surge with greater market segmentation, diversification and decentralization. The emergence of smart automobiles, smart cities, smart medicine, AR/VR and other new markets headed the list of new applications. In the next three to five years, semiconductor industry growth is expected to remain stable, with no marked declines. In 2018, the growth rate is expected to fall to between 5 percent and 8 percent, with the expansion more comprehensive and balanced.

The memory market, in particular, will find it hard to match its 2017 blistering growth rate. The market’s expected growth of 10 percent to 20 percent will be chiefly driven by DRAM and 3D NAND Flash. In 2019, NAND growth will continue but DRAM shipments could decline.

Emphasis on both innovation and investment key to sustainable growth of Chinese IC

Under the China government’s Guidelines to Promote National IC Industry Development, designed to provide key policy guidance and capital support for the development of China’s IC industry, the Chinese semiconductor industry is seeing particularly rapid growth that is expected to be a key contributor to continuing global industry expansion. In IC design, HiSilicon and Unigroup Spreadtrum & RDA ranked among the top 10 in the world. In wafer fabrication, Chinese IC manufacturing accounted for 13 percent to 15 percent of global market capacity despite SMIC and Huahong Group lagging international competition in advanced processing. In packaging and testing – China’s strongest segment – JCET, NFME and Huatian Technology also ranked in the global top 10.

The Guidelines to Promote National IC Industry Development has fueled a boom in capital investments. However, investments must go well beyond fab construction to add new capacity for China’s semiconductor industry to flourish. A strategy for sustainable, long-term chip industry growth must focus more on technology innovation while continuing heavy capital investments, though it takes time for innovation to lead to higher capacity demand and GPD growth and more jobs.

Despite large investments by the 02 Special Project in semiconductor equipment and materials, China trails other regions of the world in advanced technologies. Global spending on semiconductor equipment reached a record-breaking USD 56 billion in 2017, with Korea a major driver. In 2017, Samsung alone invested USD 25 billion in semiconductor equipment, followed by TSMC (USD 10.8 billion), Intel (USD 11.5 billion), Hynix (USD 8.5 billion), Micron (USD 0.5 billion), SMIC (USD 2.3 billion) and YMTC (USD 2 billion). In 2018, Samsung’s equipment spending is expected to drop slightly, to USD 24 billion, while investments by Intel and TSMC will be remain roughly equal.

China’s equipment spending will continue to grow in 2018, with SMIC and YMTC maintaining investment levels similar to last year’s and other China semiconductor manufacturers starting to ramp up investments. In 2018, China is expected to surpass Taiwan in equipment spending to claim the number two position after Korea.

SIIP China dedicated to international connection and cooperation

The huge investments in China’s semiconductor industry need to be supported by robust business strategies, greater international cooperation, deeper expertise in advanced technologies, and more skilled workers. China lags the global industry in all of these areas. The rapid rise of China’s semiconductor industry has raised concerns among many countries over China’s growing influence, with some, most notably the United States, going so far as to implement containment measures. Other regions including Japan, Korea and Taiwan followed suit.

The continued growth of China’s semiconductor industry hinges on technological innovation enabled by international cooperation, as well as strong international communication to allay concerns and misunderstandings over the rising prominence of China’s chip sector. China must overcome these obstacles. One partial solution is for China to convince the rest of the world that its need a thriving semiconductor industry if only to meet enormous demand for electronics products within its own borders.

As the largest international semiconductor industry association, SEMI enjoys a unique ability to strengthen the connection between China’s semiconductor sector and its international counterparts. SEMI is well-known for its vital support of the traditional semiconductor equipment and materials markets, but SEMI’s work also spans IC design, manufacturing, packaging and testing. What’s more, SEMI has expanded into innovative market vertical applications such as AI, smart manufacturing, smart transportation and smart automotive as it aims to bring together supply chains across these growth areas.

For its part, SEMI China remains dedicated to improving communications and cooperation between the Chinese and global semiconductor industries. SEMI China will also continue to encourage deeper collaboration among individual enterprises and government institutions in the interest of industry growth while making full use of SEMI’s international, professional and localization platform to promote the development of China’s semiconductor industry.

Last year, we established SEMI Innovation Investment Platform (SIIP) China to help grow China’s pool of skilled workers, promote advanced technology, generate industry capital, and expand China’s semiconductor industry while developing stronger connections with chip sectors in other regions. SIIP China is focused on the following:

  • Promoting sustainable development of the Chinese semiconductor industry
  • Establishing stronger connections to help take advantage of global technology and investment opportunities
  • Providing a platform for open communications between the Chinese and global semiconductor industries
  • Promoting greater coordination between China and its global partners
  • Helping newly enterprises secure funds for expansion

Encouraging greater cooperation with foreign semiconductor manufacturers in the interest of openness and mutual benefit will be the best way for China to overcome obstacles to the development of its semiconductor industry. Meanwhile, China will continue to strive to merge into the global semiconductor industry and become a key partner.

SEMICON China has witnessed the development of Chinese semiconductor industry

SEMICON China-1

SEMICON China marked its 30th anniversary this year. Over the past three decades, China’s semiconductor industry has seen remarkable growth. This year’s SEMICON China was the largest ever. SEMICON China and FPD China 2018 numbered 3,628 booths, covered 74,000 square meters of exhibition space and attracted 1,116 exhibitors from 21 countries and regions and 91,252 professional attendees from 58 countries and regions.

Most of China’s top device makers and global leading packaging houses, together with their equipment and materials suppliers, exhibited at SEMICON China and FPD China 2018, representing the global IC manufacturing ecosystem. The number of SEMICON China and FPD China 2018 visitors jumped 32.3 percent from last year, with representation by professionals from the design, manufacturing, assembly and test, equipment and materials sectors.

Lung Chu is President of SEMI China.

Originally published on the SEMI blog.