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By Emir Demircan, Senior Manager Advocacy and Public Policy, SEMI Europe

With its leading research and development hubs, materials and equipment companies and chipmakers, the EU is in a strategic position in the global electronics value chain to support the growth of emerging applications such as autonomous driving, internet of things, artificial intelligence and deep learning. Underpinning the European electronics industry’s competitive muscle requires a new EU-wide strategy aimed at strengthening the value chain and connecting various players. Specializing and investing in key application segments, such as automotive where the EU enjoys a central place at global level, is crucial to help European electronics industry hold its ground.  In parallel, Europe’s production capabilities need bolstered, requiring effective use of Important Projects of Common European Interest (IPCEI).

On research, development and innovation (RD&I), the upcoming Framework Programme 9 (FP9) must provide unprecedented collaboration and funding opportunities to Europe’s electronics players. Concerning small and medium enterprises (SMEs) and startups, it is vital that EU policies are aligned with global trends and small and young companies benefit from a business-friendly regulatory framework. And as an overarching action, building a younger, bigger and more diverse talent pipeline is paramount for Europe to innovate in the digital economy.

Laith Altimime, President at SEMI Europe, opening speech at ISS Europe 2018

Laith Altimime, President at SEMI Europe, opening speech at ISS Europe 2018

These were the clarion messages that emerged from the Industry Strategy Symposium (ISS) Europe organized by SEMI in March, an event that brought together more than 100 industry, research and government representatives for in-depth discussions on strategies and innovations for Europe to compete globally. Here are the key takeaways:

1) Build a strong electronics value chain with a focus on emerging demands

In recent years the EU has focused on beefing up semiconductor production in Europe within the 2020-25 window, starting with the EU 10|100|20 Electronic Strategy of 2013. The strategy aims to secure about 20 percent of global semiconductor manufacturing by 2020 with the help of € 10 billion in public and private funding and € 100 billion investment from the industry. Today, Europe is not nearly on track to achieving this target. Supply-side policies have done little to help grow the EU semiconductor industry. Now is the time to change our thinking.

To nourish the electronics industry in Europe, we need to shift our focus to demand. Semiconductors are a key-enabling technology for autonomous driving, wearables, healthcare, virtual and augmented reality (VR/AR), artificial intelligence (AI) and all other internet of things (IoT) and big data applications. To become a world leader in the data economy and energize its semiconductor industry, Europe needs to start by better understanding the evolution of data technologies and their requirements from electronics players, then design and implement an EU-wide strategy focused on strengthening collaboration within the value chain.

2) Specialize and invest in Europe’s strengths that are enabled by electronics

Jens Knut Fabrowsky, Executive VP Automotive Electronics at Bosch

Jens Knut Fabrowsky, Executive VP Automotive Electronics at Bosch

Fueled by increasing demand for smaller, faster and more reliable products with greater power, the global electronics industry has developed a sophisticated global value chain. Europe brings to this ecosystem leading equipment and materials businesses, world-class R&D and education organizations, and key microelectronics hubs throughout Europe that are home to multinationals headquartered both in and outside of the EU. Nevertheless, global competition is growing ever fiercer in the sectors where the European microelectronics industry is most competitive: automotive, energy, healthcare and industrial automation. In the future, Europe is likely to be more challenged between the disruptive business models of North America and the manufacturing capacity of East Asia. The European electronics industry must re-evaluate its strengths and set a strategic direction.

Make no mistake: Europe is in a strong position to advance its microelectronics industry. The EU already boasts leading industries that rely on advances made by electronics design and manufacturing. Take the automotive industry – crucial to Europe’s prosperity. Accounting for 4 percent of the EU GDP and providing 12 million jobs in Europe, according to the European Commission, the EU automotive industry exerts an important multiplier effect in the economy. Automotive is essential to both upstream and downstream industries such as electronics – a level of importance not lost on the EU’s GEAR 2030 Group. Since the 1980s, automotive industry components have increasingly migrated from mechanical to electrochemical and electronics.

Today, electronic components represent close to a third of the cost of an automobile, a proportion that will grow to as high as 50 percent by 2030 with the rise of autonomous and connected vehicles. Automotive experts anticipate that over the next five to 10 years, new cars will feature at least some basic automated driving and data exchange capabilities as electronics deepen their penetration into the automotive value chain. Europe’s leadership position and competitive edge in automotive are under threat by competitors across the world as they invest heavily in information and communications technologies (ICT) and electronics for autonomous driving and connected vehicles. Investing in next-generation cars will help the European electronics industry retain its strong competitive position, as will investments in other key application areas such as healthcare, energy and industrial automation where Europe is a global power.

3) Make better use of Important Projects of Common European Interest (IPCEI)

Microelectronics is capital-intensive, with a state-of-the-art fab easily costing billions of euros. That’s why countries around the world are making heavy government-backed investments to build domestic fabs. For instance, China’s “Made in China 2025” initiative, which establishes an Integrated Circuit Fund to support the development of the electronics industry, calls for 150 billion USD in funding to replace imported semiconductors with homegrown devices. In 2014, the European Commission adopted new rules to IPCEI, giving Member States a tool for financing large, strategically important transnational projects. IPCEI should help Member States fill funding gaps to overcome market failures and reinvigorate projects that otherwise would not have taken off. To fully benefit from the IPCEI, the industry requires Member States involved in a specific IPCEI to work in parallel and at the same pace and faster approvals of state-supported manufacturing projects.

4) Use FP9 to strengthen Europe’s RD&I capabilities

Panel Discussion on growing Europe in the global value chain. (L-R) Bryan Rice, GLOBALFOUNDRIES; James Robson, Applied Materials Europe; Joe De Boeck, imec; Leo Clancy, IDA Ireland; James O’Riordan, S3; Colette Maloney, European Commission; Moderator: Andreas Wild

Panel Discussion on growing Europe in the global value chain. (L-R) Bryan Rice, GLOBALFOUNDRIES; James Robson, Applied Materials Europe; Joe De Boeck, imec; Leo Clancy, IDA Ireland; James O’Riordan, S3; Colette Maloney, European Commission; Moderator: Andreas Wild

A top EU priority in recent years has been to enhance Europe’s position as a world leader in the digital economy. Fulfilling this mission requires an innovative electronics industry in Europe. To this end, FP9 should encourage greater collaboration between large and small companies to leverage their complementary strengths – the dynamism, agility and innovation of smaller companies and the ability of larger companies to mature and scale new product ideas on the strength of their extensive private funding instruments and testing and demonstration facilities. Also, future EU-funded research actions should prioritize electronics projects involving players across the value chain, starting with materials and equipment providers and spanning chipmakers, system integrators and players from emerging “smart” verticals such as automotive, medical technology and energy. FP9 should also play the pivotal role of setting clear objectives, increasing investments, and easing rules for funding. These measures would help expand the European electronics ecosystem, accelerate R&D results and defray the rising costs of developing cutting-edge solutions key to the growth of emerging industry verticals.

5) Support high-tech SMEs, entrepreneurship and startups to become globally competitive

European SMEs, the backbone of EU’s manufacturing, are already strong players in the global economy, making outsize contributions to Europe’s innovation. Yet more of Europe’s small and young businesses with limited resources are challenged in Europe’s regulatory labyrinth. Only by improving the European regulatory environment in a way that supports young and small businesses can Europe fulfill its vision of a dynamic electronics ecosystem and digital economy. Access to finance must also be easier, particularly as underinvested startups struggle under a European venture capital apparatus that is smaller and more fragmented than those in North America and Asia. Early-stage funding instruments such as bank loans are essential for young businesses but they often face barriers to finance due to the sophistication of their proposed business models that are difficult to be understood and supported by banks.

One answer is to better familiarize Europe’s financial sector with industrial SMEs and startups so they can co-develop financial tools that support the growth of small and young businesses. Also, the narrow European definition of SME with staff headcount limited to 250 block innovative companies from access to financial tools exclusively provided to SMEs. By contrast, the United States defines SMEs as businesses with as many as 500 employees, placing their EU counterparts at distinct funding disadvantage. EU should ensure that its SME policy is aligned with global trends and industry needs.

6) Create a bigger and more diverse talent pipeline with a hybrid skills set 

Europe’s world-class education and research capabilities help supply the electronics industry with skilled workforce. Yet the blistering pace of technology innovation calls for rapidly evolving skills sets, a trend that has led to worker shortages at electronics companies and left the sector fighting to diversify its workforce and strengthen its talent pipeline. The deepening penetration of electronics in AI, IoT, AR/VR, high-performance computing (HPC), cybersecurity and smart verticals is giving rise to a new set of skills that blend production technologies, software and data analytics. As more technologies converge, the gap between university education and business needs continues to widen.

One solution is work-based learning – allowing students to build job skills in a setting related to their career pathway. Encouraging higher female participation in STEM education programs at the high school and university levels is also a must to overcome the traditionally low number of females entering high technology. To build on its reputation as “a place to work” in the eyes of the international job seekers, Europe also needs a more flexible immigration framework to attract skilled labour to high-tech jobs.

Save the Date: Industry leaders, research and government representatives will meet again next year at the ISS Europe organized by SEMI on 28-30 April 2019 in Milan, Italy. More details regarding the event will be published soon on www.semi.org/eu.

Research included in the April Update to the 2018 edition of IC Insights’ McClean Report shows that the world’s leading semiconductor suppliers significantly increased their marketshare over the past decade. The top-5 semiconductor suppliers accounted for 43% of the world’s semiconductor sales in 2017, an increase of 10 percentage points from 10 years earlier (Figure 1).  In total, the 2017 top-50 suppliers represented 88% of the total $444.7 billion worldwide semiconductor market last year, up 12 percentage points from the 76% share the top 50 companies held in 2007.

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Figure 1

As shown, the top 5, top 10, and top 25 companies’ share of the 2017 worldwide semiconductor market each increased from 10-12 percentage points over the past decade.  With the surge in mergers and acquisitions expected to continue over the next few years (e.g., Qualcomm and NXP), IC Insights believes that consolidation will raise the shares of the top suppliers to even loftier levels.

As shown in Figure 2, Japan’s total presence and influence in the IC marketplace has waned significantly since 1990, with its IC marketshare (not including foundries) residing at only 7% in 2017.  Once-prominent Japanese names missing from the top IC suppliers list are NEC, Hitachi, Mitsubishi, and Matsushita. Competitive pressures from South Korean IC suppliers—especially in the memory market—have certainly played a significant role in changing the look of the IC marketshare figures over the past 27 years. Moreover, depending on the outcome of the sale of Toshiba’s NAND flash division, the Japanese-companies’ share of the IC market could fall even further from its already low level.

Figure 2

Figure 2

With strong competition reducing the number of Japanese IC suppliers, the loss of its vertically integrated businesses, missing out on supplying ICs for several high-volume end-use applications, and its collective shift toward the fab-lite IC business model, Japan has greatly reduced its investment in new semiconductor wafer fabs and equipment.  In fact, Japanese companies accounted for only 5% of total semiconductor industry capital expenditures in 2017 (two points less than the share of the IC market they held last year), a long way from the 51% share of spending they represented in 1990.

SEMI, the global industry association representing the electronics manufacturing supply chain, today announced that after several years of incremental increases the worldwide semiconductor photomask market surged 13 percent to a record high $3.75 billion in 2017 and is forecast to exceed $4.0 billion in 2019. The mask market is expected to grow 5 percent and 4 percent in 2018 and 2019, respectively, according to the SEMI report. Key photomask market drivers remain advanced technology feature sizes (less than 45nm) and Asia-Pacific manufacturing growth. Taiwan is again the largest photomask regional market for the seventh year in a row and is expected to retain the top spot for the duration of the forecast. Korea rose in the rankings to claim the second spot.

With the $3.75 billion in revenues, photomasks accounted for 13 percent of the total wafer fabrication materials market, behind silicon and semiconductor gases, in 2017. By comparison, SEMI reports that photomasks represented 18 percent of the total wafer fabrication materials market in 2003. Reflecting their growing importance, captive mask shops, aided by intense capital expenditures in 2011 and 2012, continue to gain market share at merchant suppliers’ expense. Captive mask suppliers accounted for 65 percent of the total photomask market last year, up from 63 percent in 2016. In 2013, captive mask shops represented 31 percent of the photomask market.

The recently published SEMI report, 2017 Photomask Characterization Summary, provides details on the 2017 Photomask Market for seven regions of the world including North America, Japan, Europe, Taiwan, Korea, China, and Rest of World. The report also includes data for each of these regions from 2003 to 2019 and summarizes lithography developments over the past year.

Silicon solar cells dominate the global photovoltaic market today with a share of 90 percent. With ever new technological developments, research and industry are nearing the theoretical efficiency limit for semiconductor silicon. At the same time, they are forging new paths to develop a new generation of even more efficient solar cells.

The Fraunhofer researchers achieved the high conversion efficiency of the silicon-based multi-junction solar cell with extremely thin 0.002 mm semiconductor layers of III-V compound semiconductors, bonding them to a silicon solar cell. To compare, the thickness of these layers is less than one twentieth the thickness of a human hair. The visible sunlight is absorbed in a gallium-indium-phosphide (GaInP) top cell, the near infrared light in gallium-arsenide (GaAs) and the longer wavelengths in the silicon subcell. In this way, the efficiency of silicon solar cells can be significantly increased.

Silicon-based multi-junction solar cell consisting of III-V semiconductors and silicon. The record cell converts 33.3 percent of the incident sunlight into electricity. © Fraunhofer ISE/Photo: Dirk Mahler

Silicon-based multi-junction solar cell consisting of III-V semiconductors and silicon. The record cell converts 33.3 percent of the incident sunlight into electricity.
© Fraunhofer ISE/Photo: Dirk Mahler

“Photovoltaics is a key pillar for the energy transformation,” says Dr. Andreas Bett, Institute Director of Fraunhofer ISE. “Meanwhile, the costs have decreased to such an extent that photovoltaics has become an economically viable competitor to conventional energy sources. This development, however, is not over yet. The new result shows how material consumption can be reduced through higher efficiencies, so that not only the costs of photovoltaics can be further optimized but also its manufacture can be carried out in a resource-friendly manner.

Already in November 2016, the solar researchers in Freiburg together with their industry partner EVG demonstrated an efficiency of 30.2 percent, increasing it to 31.3 percent in March 2017. Now they have succeeded once again in greatly improving the light absorption and the charge separation in silicon, thus achieving a new record of 33.3 percent efficiency. The technology also convinced the jury of the GreenTec Awards 2018 and has been nominated among the top three in the category “Energy.”

The Technology

For this achievement, the researchers used a well-known process from the microelectronics industry called “direct wafer bonding” to transfer III-V semiconductor layers, of only 1.9 micrometers thick, to silicon. The surfaces were deoxidized in a EVG580® ComBond® chamber under high vacuum with a ion beam and subsequently bonded together under pressure. The atoms on the surface of the III-V subcell form bonds with the silicon atoms, creating a monolithic device. The complexity of its inner structure is not evident from its outer appearance: the cell has a simple front and rear contact just as a conventional silicon solar cell and therefore can be integrated into photovoltaic modules in the same manner.

EVG ComBond automated high-vacuum wafer bonding platform (Photo courtesy of EV Group).

EVG ComBond automated high-vacuum wafer bonding platform
(Photo courtesy of EV Group).

The III-V / Si multi-junction solar cell consists of a sequence of subcells stacked on top of each other. So-called “tunnel diodes” internally connect the three subcells made of gallium-indium-phosphide (GaInP), gallium-arsenide (GaAs) and silicon (Si), which span the absorption range of the sun’s spectrum. The GaInP top cell absorbs radiation between 300 and 670 nm. The middle GaAs subcell absorbs radiation between 500 and 890 nm and the bottom Si subcell between 650 and 1180 nm, respectively. The III-V layers are first epitaxially deposited on a GaAs substrate and then bonded to a silicon solar cell structure. Here a tunnel oxide passivated contact (TOPCon) is applied to the front and back surfaces of the silicon. Subsequently the GaAs substrate is removed, a nanostructured backside contact is implemented to prolong the path length of light. A front side contact grid and antireflection coating are also applied.

On the way to the industrial manufacturing of III-V / Si multi-junction solar cells, the costs of the III-V epitaxy and the connecting technology with silicon must be reduced. There are still great challenges to overcome in this area, which the Fraunhofer ISE researchers intend to solve through future investigations. Fraunhofer ISE’s new Center for High Efficiency Solar Cells, presently being constructed in Freiburg, will provide them with the perfect setting for developing next-generation III-V and silicon solar cell technologies. The ultimate objective is to make high efficiency solar PV modules with efficiencies of over 30 percent possible in the future.

Project Financing

Dr. Roman Cariou, the young scientist and first author, was supported through the European Union with a Marie Curie Stipendium (HISTORIC, 655272). The work was also supported by the European Union within the NanoTandem project (641023) as well as by the German Federal Ministry for Economic Affairs and Energy BMWi in the PoTaSi project (FKZ 0324247).

Correction: A previous version of this article incorrectly state “imec” in the headline, instead of Fraunhofer ISE. Solid State Technology regrets the error.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $36.8 billion for the month of February 2018, an increase of 21.0 percent compared to the February 2017 total of $30.4 billion. Global sales in February were 2.2 percent lower than the January 2018 total of $37.6 billion, reflecting typical seasonal market trends. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor market continued to demonstrate substantial and consistent growth in February, notching its 19th consecutive month of year-to-year sales increases and growing by double-digit percentages across all major regional markets,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Americas stood out once again, with sales increasing nearly 40 percent compared to last year, and sales were up year-to-year across all major semiconductor product categories.”

Year-to-year sales increased significantly across all regions: the Americas (37.7 percent), Europe (21.7 percent), China (16.4 percent), Asia Pacific/All Other (16.2 percent), and Japan (15.5 percent). Month-to-month sales increased slightly in Europe (0.9 percent), but fell somewhat in Japan (-0.9 percent), Asia Pacific/All Other (-1.5 percent), China (-2.6 percent), and the Americas (-4.3 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2017 SIA Databook.

Feb 2018

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

8.63

8.26

-4.3%

Europe

3.40

3.43

0.9%

Japan

3.21

3.18

-0.9%

China

12.01

11.70

-2.6%

Asia Pacific/All Other

10.35

10.19

-1.5%

Total

37.60

36.75

-2.2%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

6.00

8.26

37.7%

Europe

2.82

3.43

21.7%

Japan

2.75

3.18

15.5%

China

10.05

11.70

16.4%

Asia Pacific/All Other

8.77

10.19

16.2%

Total

30.38

36.75

21.0%

Three-Month-Moving Average Sales

Market

Sep/Oct/Nov

Dec/Jan/Feb

% Change

Americas

8.77

8.26

-5.8%

Europe

3.42

3.43

0.1%

Japan

3.21

3.18

-1.0%

China

11.90

11.70

-1.7%

Asia Pacific/All Other

10.39

10.19

-1.9%

Total

37.69

36.75

-2.5%

 

The semiconductor industry closed out 2017 in blockbuster fashion, posting the highest year-over-year growth in 14 years. Global semiconductor revenue grew 21.7 percent, reaching $429.1 billion in 2017, according to IHS Markit (Nasdaq: INFO).

Recording year-over-year growth of 53.6 percent, and its highest semiconductor revenue ever, Samsung replaced Intel as the new market leader of the semiconductor industry in 2017. Intel was followed by SK Hynix, in third position.

“2017 was quite a memorable year,” said Shaun Teevens, semiconductor supply chain analyst, IHS Markit. “Alongside record industry growth, Intel, which had led the market for 25 years, was supplanted by Samsung as the leading semiconductor supplier in the world.”

Among the top 20 semiconductor suppliers, SK Hynix and Micron enjoyed the largest year-over-year revenue growth, growing 81.2 percent and 79.7 percent, respectively. “A very favorable memory market with strong demand and high prices was mainly responsible for the strong growth of these companies,” Teevens said.

Qualcomm remained the top fabless company in 2017, followed by nVidia, which moved into the second position, after growing 42.3 percent over the previous year. Among the top 20 fabless companies, MLS enjoyed the highest market share gain, moving from number 20 to number 15 in the IHS Markit revenue ranking.

Figure 1

Figure 1

Memory was the strongest industry category

Memory integrated circuits proved to be the strongest industry category, growing 60.8 percent in 2017 compared to the previous year. Within the category, DRAM grew 76.7 percent and NAND grew 46.6 percent — the highest growth rate for both memory subcategories in 10 years. Much of the revenue increase was based on higher prices and increased demand for memory chips, relative to tight supply.

“The technology transition from planar 2D NAND to 3D NAND drove the market into an unbalanced supply-demand environment in 2017, driving prices higher throughout the year,” said Craig Stice, senior director, memory and storage, IHS Markit. “Entering 2018, the 3D NAND transition is now almost three-quarters of the total bit percent of production, and it is projected to provide supply relief for the strong demand coming from the SSD and mobile markets. Prices are expected to begin to decline aggressively, but 2018 could still be a record revenue year for the NAND market.”

Excluding memory, the remainder of the semiconductor industry grew 9.9 percent last year, largely due to solid unit-sales growth and strong demand across all applications, regions and technologies. Notably, semiconductors used for data processing applications expanded 33.4 percent by year-end. Intel remained the market leader in this category, with sales almost two times larger than second-ranked Samsung.

 

Combined sales for optoelectronics, sensors and actuators, and discrete semiconductors (known collectively as O-S-D) increased 11% in 2017—more than 1.5 times the average annual growth rate in the past 20 years—to reach an eighth consecutive record-high level of $75.3 billion, according to IC Insights’ new 2018 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes. Total O-S-D sales growth is expected to ease back in 2018 but still rise by an above average rate of 8% in 2018 to $81.1 billion, based on the five-year forecast of the new 375-page annual report, which became available this week.

In 2017, optoelectronics sales recovered from a rare decline of 4% in 2016, rising 9% to $36.9 billion, while the sensors/actuators market segment registered its second year in a row of 16% growth with revenues climbing to $13.8 billion, and discretes strengthened significantly, increasing 12% to $24.6 billion.  The new O-S-D Report forecast shows optoelectronics sales growing 8% in 2018, sensors/actuators rising 10%, and discretes growing 5% this year (Figure 1).

Figure 1

Figure 1

Between 2017 and 2022, sales in optoelectronics are projected to increase by a compound annual growth rate (CAGR) of 7.3% to $52.4 billion, while sensors/actuators revenues are expected to expand by a CAGR of 8.9% to $21.2 billion, and the discretes segment is seen as rising by an annual rate of 3.1% to $28.7 billion in the final year of the report’s forecast.  In the five-year forecast period, O-S-D growth will continue to be driven by strong demand for laser transmitters in optical networks and CMOS image sensors in embedded cameras, image recognition, machine vision, and automotive applications as well as the proliferation of other sensors and actuators in intelligent control systems and connections to the Internet of Things (IoT).  Power discretes (transistors and other devices) are expected to get a steady lift from the growth in mobile and battery-operated systems as well as good-to-modest global economic growth in most of the forecast years through 2022, the report says.

Combined sales of O-S-D products accounted for about 17% of the world’s $444.7 billion in total semiconductor sales compared to less than 15% in 2007 and under 13% in 1997.  Since the mid-1990s, total O-S-D sales growth has outpaced the much larger IC market segment because of strong and relatively steady increases in optoelectronics and sensors. However, this trend was reversed recently mostly due to a 77% surge in sales of DRAMs and 54% jump in NAND flash memory in 2017.

The 2017 increase for total O-S-D sales was the highest growth rate in the market group since the 37% surge in the strong 2010 recovery year from the 2009 semiconductor downturn.  In addition, 2017 was the first year since 2011 when all three O-S-D market segments reached individual record-high sales, says IC Insights’ new report.  The 2018 O-S-D Report also shows that sales of sensor and actuator products made with microelectromechanical systems (MEMS) technology grew 18% in 2017 to a record-high $11.5 billion.

There are many different situations in which special attention to color choices provide the potential to improve the manufacturing results of multi-patterned masks.

BY DAVID ABERCROMBIE and ALEX PEARSON, Mentor Graphics, Wilsonville, OR

Multi-patterning design rules don’t care about color (mask assignments). As long as all the spacing and alternation constraints are met, any coloring arrangement is legal. In the beginning of multi-patterning, all possible color combinations that passed the design rule checks (DRC) were considered and treated as equal. As the technology moves into more advanced nodes, however, that is no longer the case.

As it turns out, one legal coloring choice can, in fact, be significantly better than another when it comes to manufacturing success and chip performance. Designers working on multi-patterned layouts need to understand the issues and conditions that affect their color choices, so they can determine the optimal coloring scheme for their designs.

Color density

In multi-patterned designs, each color assignment represents a different manufacturing mask. Each mask is processed through a lithography operation, and the pattern is etched onto the wafer. Once all the masks are processed, the goal is to have all the shapes created from all the masks act as if they were all generated from one mask, with very similar process biases and variations.
To ensure that type of consistency, all the masks need to resemble each other in terms of the total area and distribution of shapes. Clumping shapes in one area of one mask, while distributing shapes evenly across another, is going to result in very different process bias behavior and results. Balancing the color density across each mask provides the best manufacturing result.

To explain why, let’s look at a standard cell library design. Because power rails are typically much wider than the routing tracks inside the cells, they constitute a large portion of the polygon area inside the standard cell design block. The number of tracks in the library force the power rails into certain color pairings (FIGURE 1). In the first case, the power rails are forced to opposite colors, while in the second, they are forced to the same color.

Screen Shot 2018-03-28 at 7.41.28 AM

The color ratio distribution charts tell the story of the two designs. When the power rails alternate color, the distribution of the color density ratio is well-centered around the 50% point. However, forcing the power rails to be a single color can dramatically shift the color ratio towards that single color. This distribution is more problematic to manufacture.

But uniform color density isn’t just a chip-wide, global issue—even local differences can have negative impacts, because local areas with excessive or insufficient color density can impact the biases of nearby shapes during processing. In FIGURE 2, both coloring options are legal, but the polygons within each connected component are not equal in area, so the choice of G-B-G-B vs. B-G-B-G affects how much area of each color ultimately exists within this local region. The second coloring choice results in a more uniform area density of each color.

Screen Shot 2018-03-28 at 7.41.35 AM

However, some layouts contain polygon configurations that inherently make it almost impossible to balance colors simply by changing color choices. For example, sometimes you have a very large area polygon in the midst of your layout (FIGURE 3). No matter what color you assign to the large polygon, it will dominate the color density in this region. Changing color selections in the nearby polygons doesn’t help, because they can’t all be assigned to the other color.

Screen Shot 2018-03-28 at 7.41.42 AM

In this case, a new (and perhaps unexpected) solution is needed. Placing evenly distributed polygons of the opposite color in a grid on top of the large area polygon (known as reverse tone overlay fill) adds shapes to the opposite color mask in a region that would otherwise have been empty (FIGURE 4). The smaller polygons on top don’t create openings (they merely “double” block the etch), so they have no real purpose in terms of the final wafer shape. In that regard, they are similar to dummy fill. This technique ensures the two masks have more similar color densities in this region.

Screen Shot 2018-03-28 at 7.41.49 AM

Color regularity

Specific configurations, such as those found in memory applications, may also need strongly controlled, repetitive coloring patterns to help the optical proximity correction (OPC) process generate more consistent results. FIGURE 5 shows three vertical instantiations of a repetitive pattern with horizontal color alternation constraints. On the left, a density-balanced legal coloring assignment is shown. However, by adding a few extra coloring constraints, you can also achieve a regular repetitive coloring pattern, as shown on the right. By introducing this color regularity, you can increase the chances of consistency in the post-OPC results.

Screen Shot 2018-03-28 at 7.41.58 AM

Layout symmetry is another aspect of design that benefits from color regularity. When there is a significant amount of symmetry around a central point, such as a sensitive analog circuit, the most desirable coloring solution maintains x and y axis symmetry around the central point. In FIGURE 6, the constrained coloring solution on the right adds constraints for x and y axis symmetry to generate a mirrored coloring pattern.

Screen Shot 2018-03-28 at 7.42.12 AM

DFM-aware coloring

In design for manufacturing (DFM) optimization, weak lithographic configurations are often captured as process hotspot patterns, which can be used with DFM and/or resolution enhancement technology (RET) processes to minimize the chance of a hotspot forming during manufacturing. As it turns out, the coloring of these patterns in multi-patterned designs can influence whether or not a pattern becomes a hotspot, or actually change the hotspot severity or impact of a particular pattern. If a hotspot pattern is consistently colored in all its instantiations, it may prevent that hotspot from forming, or allow a carefully tuned OPC recipe to be applied.

In FIGURE 7, a different, but still legal, coloring is applied to a rotated/reflected pattern. Because the OPC process will now affect each instance differently, the rotated pattern may become a lithographic hotspot, while the original pattern does not.

Screen Shot 2018-03-28 at 7.42.04 AM

FIGURE 8 shows the same legal coloring applied to both pattern instances, which allows the same OPC to be applied to the layout in both locations, because the coloring is the same, and the polygons that end up on each mask are consistent.

Screen Shot 2018-03-28 at 7.42.21 AM

Sometimes there are cases where information from other layers indicate a color preference for certain shapes. These preferences are typically the result of analysis on another layer, or from information the designer provides, such as for critical or high voltage nets. While these preferences may sometimes conflict with each other for neighboring shapes in the same component, applying these preferences whenever possible helps drive an optimal coloring solution. In FIGURE 9, the red markers indicate a preference for placing those shapes on the green mask. In this case, there is one component that cannot comply, but placing three of the four tagged polygons on the preferred mask maximizes the preferred placements, making this optimal coloring solution.

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Conclusion

In advanced process nodes, achieving the best performance and yield requires moving beyond the minimum requirements of the design rules to optimizing the layout. This optimization is a fundamental principle of all design for manufacturing (DFM) activities, including multi-patterning decomposition. There are many different situations in which special attention to color choices provide the potential to improve the manufacturing results of multi-patterned masks. Designers involved with generating the decomposed mask data before tapeout can expect to see more emphasis on color optimizations as the industry continues to refine and enhance multi-patterning processes.

By David W. Price, Douglas G. Sutherland and Jay Rathert

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection, metrology and data analysis—for the semiconductor industry. This article is the second in a five-part series on semiconductors in the automotive industry. In the first article, we introduced some of the challenges involved in the automotive supply chain and showed that the same defects that cause yield loss are also responsible for reliability issues. In this article, we discuss the connection between baseline yield and baseline reliability and present ways that both can be improved.

The strong correlation between semiconductor IC yield and reliability has been well studied and documented. The data shown in figure 1 demonstrates this relationship. Similar outcomes have been shown at the lot, wafer and die location level. Simply put, when yield is high, reliability follows suit. As discussed in the first article of the Process Watch Automotive series, this yield-reliability correlation is not unexpected, since the defect types that cause die failures are the same as those that cause early reliability problems. Yield and reliability defects differ primarily by their size and where they occur on the device pattern in the die.

Figure 1. Data demonstrating the strong correlation between IC device reliability and yield.1

Figure 1. Data demonstrating the strong correlation between IC device reliability and yield.1

It follows that reducing the number of yield-killing defects in the IC manufacturing process will increase baseline yield and simultaneously increase device reliability in the field. Recognizing this fact, fabs serving the automotive market are faced with two critical questions. The first is economic in nature: what is the appropriate level of investment of time, money and resources in yield improvement to create the needed reliability gains? The second question is technical: what are the best defect reduction methodologies for boosting the baseline yield to the necessary levels?

For fabs that make consumer devices (ICs for mobile phones, tablets, etc.), “mature yield” is defined as the point where further improvements in yield no longer warrant the investment of time and resources. As a product matures, yield tends to stabilize at some high value, but usually well below 100%. Instead of pursuing higher yield, it makes more economic sense for the consumer fab to reallocate resources to developing the next design node’s processes and devices, or to reducing costs to improve the profitability of their legacy node.

For automotive fabs, the economic decision on whether to invest more to increase yield extends beyond the typical marginal revenue determination. When there is a reliability issue, the automotive IC manufacturer will likely bear the cost of expensive and time-consuming failure analysis, and will be held financially liable for field warranty failures, recalls and potential legal liabilities. Given that automotive IC reliability requirements are as much as two to three orders of magnitude higher than consumer IC requirements, automotive fabs must achieve higher baseline yield levels. This requires a new way of thinking about what constitutes “mature yield.”

Figure 2 highlights the difference in mature yield between consumer and automotive fabs. As either type of fab moves up the yield curve, almost all systematic sources of yield loss have been resolved. The remaining yield loss is primarily due to random defectivity, contributed by either the process tools or the environment. A consumer fab may adopt a “good enough” approach to yield and reliability at this point. However, in the automotive industry, fabs employ a continuous improvement strategy to push the yield curve even higher. By driving down the incidence of yield-limiting defects, automotive fabs also reduce latent reliability defects, thereby optimizing their profits and mitigating risk.

Figure 2. In a consumer device fab (yellow line), the top of the yield curve (Yield versus Time) is limited by diminishing returns to profitability for increased investment in defect reduction. The automotive fab yield curve, shown by the blue dashed line, also factors in reliability. Additional improvement to baseline yield must be made by automotive fabs to meet the parts per billion quality requirements. The purple shaded area highlights the difference in yield between consumer and automotive fabs – a difference that’s primarily related to process tool defectivity.

Figure 2. In a consumer device fab (yellow line), the top of the yield curve (Yield versus Time) is limited by diminishing returns to profitability for increased investment in defect reduction. The automotive fab yield curve, shown by the blue dashed line, also factors in reliability. Additional improvement to baseline yield must be made by automotive fabs to meet the parts per billion quality requirements. The purple shaded area highlights the difference in yield between consumer and automotive fabs – a difference that’s primarily related to process tool defectivity.

The automotive supply chain – from OEMs to Tier 1 suppliers to IC manufacturers – is adopting a mindset that “every defect matters” in pursuit of a Zero Defect strategy. They recognize that when latent defects escape the fab, the cost of discovery and mitigation increases as much as 10x at every additional level of the supply chain. As such, the existing over-reliance on electrical test needs to be replaced by a strategy where latent failures are stopped in the fab where the cost is lowest. Only by implementing a methodical defect reduction program will a fab move towards the Zero Defect goal and be able to pass the stringent audits required by automobile manufacturers.

In addition to robust inline defect control capability, some of the defect reduction methods that automotive purchasing managers look for include:

  • Continuous Improvement Program (CIP) for baseline defect reduction
  • Golden Tool Work Flow
  • Dog Tool Programs

Continuous Improvement in Baseline Defect Reduction

The foundation of any rigorous baseline defect reduction plan is the inline defect strategy. To successfully detect the defects that affect yield and reliability of their design rules and device types, a fab’s inline defect strategy must include both an appropriate process control toolset and an adequate sample plan. The defect inspection systems utilized must produce the required defect sensitivity, be maintained to specifications and utilize well-tuned inspection recipes. The sample plan must be set for the right process steps at sufficient frequency to quickly flag process or tool excursions. Additionally, there should be sufficient inspection capacity to support a control plan that expedites excursion detection, root cause isolation and WIP-at-risk traceability. With these elements, an automotive fab should achieve a successful baseline defect reduction plan that can demonstrate positive yield trends over time, provide goals for further improvement, and equal industry best practices.

Within a baseline defect reduction plan, one of the biggest challenges is answering the question: where did this defect come from? The answer is often not straightforward. Sometimes the defect is detected many process steps away from the defect source. Sometimes the defect becomes apparent only after the wafer has gone through several other process steps that “decorate” it – i.e., make it more visible to inspection systems. A Tool Monitoring strategy helps resolve the question surrounding a defect’s origin.

In Tool Monitoring / Tool Qualification (TMTQ) applications, a bare wafer is inspected, run through a specific process tool (or chamber) and then inspected again (figure 3). Any new defects found on the wafer with the second inspection must have been added by that specific process tool. The results are unequivocal; there is no question about the defect’s origin. Automotive fabs pursuing a Zero Defect standard recognize the benefit of a Tool Monitoring strategy: with sensitive inspection recipes, appropriate control limits and out-of-control action plans (OCAP), the sources of random yield loss contributed by each process tool can be revealed and addressed.

Figure 3. After baselining the bare wafer with a “pre” inspection, it can be cycled through some or all process tool steps. The “post” inspection reveals defects added by the process tool.

Figure 3. After baselining the bare wafer with a “pre” inspection, it can be cycled through some or all process tool steps. The “post” inspection reveals defects added by the process tool.

Furthermore, when a process tool’s contribution of adder defects is plotted over time, as in figure 4, it provides a record of continuous improvement that can be audited and used to set future defect reduction goals. The defects from every tool in the fab can be classified to generate a defect library that can be referenced for failure analysis of field returns. This approach requires very frequent tool qualification – at least once per day – and is usually used in conjunction with a Golden Tool Work Flow or Dog Tool Programs, discussed below.

Figure 4. Continuous improvement in tool cleanliness over time. The source of the problem is unambiguous and objective defect reduction targets can be set on a quarterly or monthly basis. In addition, comparing the defectivity of two process tools can show which tool is cleaner. This helps guide tool maintenance activities to pinpoint the cause of the differences between the tools.

Figure 4. Continuous improvement in tool cleanliness over time. The source of the problem is unambiguous and objective defect reduction targets can be set on a quarterly or monthly basis. In addition, comparing the defectivity of two process tools can show which tool is cleaner. This helps guide tool maintenance activities to pinpoint the cause of the differences between the tools.

Golden Tool Work Flow

A Golden Tool Work Flow is another strategy used by fabs to reach the Zero Defect standard required by the automotive industry. With a Golden Tool Work Flow or Automotive Work Flow (AWF), the wafers for automotive ICs only go through the best process tools in the fab, requiring that the fab knows the best tool for any given process step. To reliability determine which tool is best, fabs leverage data from inline and tool monitoring inspections, and then only use those tools for the Automotive Work Flow. Restricting automotive wafers to a single tool at each process step can lead to longer cycle times. However, this is usually preferable to sending automotive wafers through process flows that suffer from higher defect levels that can lead to reliability issues. When coupled with a methodical continuous improvement program, most fabs can usually get multiple tools qualified for AWF at each step by setting quarterly targets for defect reduction.

Because it is a difficult method the scale up, the Golden Tool Work Flow is best suited for fabs where only a small percentage of WIP is automotive. For fabs in high volume automotive production, a more methodical continuous improvement program, such as the Dog Tool approach described below, is preferred.

Dog Tool Programs

A Dog Tool Program is the opposite of a Golden Tool Work Flow as it proactively addresses the worst process tool – the dog tool – at any given process step. Fabs that have been most successful in driving down baseline defectivity often have done so by adopting a Dog Tool Program. They first take down the dog tool at every process step and work on that tool until it is better than the average of the remaining tools in that set. They repeat this process over and over until all tools in the set meet some minimum standard. An effective Dog Tool program requires that the fab has a methodical Tool Monitoring strategy to qualify each process tool at each step. At a minimum, this qualification procedure should be done daily on each tool to ensure there is sufficient data so that an ANOVA or Kruskal-Wallis analysis can identify the best and worst tools in each set. A Dog Tool Program, with planned process tool downtime, is the one of the fastest ways known to bring an entire fab up to automotive standards. By increasing yield and reliability, this strategy ultimately improves an automotive fab’s effective capacity and profitability.

Summary

Automotive manufacturers who demand high reliability often require the fab to change their mindset about what really defines mature yield. In this article we have discussed several ways that fabs can reduce their baseline defectivity and improve reliability and yield. In the next article in this series we will discuss some of the technical considerations regarding the sensitivity of defect inspection tools and how that helps ensure chip reliability.

About the Authors:

Dr. David W. Price and Jay Rathert are Senior Directors at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 15 years, they have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall process control strategy for a variety of specific markets, including automotive reliability, legacy fab cost and risk optimization, and advanced design rule time-to-market BKMs. The Process Watch series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

References:

  1. Mann, “Wafer Test Methods to Improve Semiconductor Die Reliability,” IEEE Design & Test of Computers, vol. 25, pp. 528-537, November-December 2008. https://doi.org/10.1109/MDT.2008.174
  2. Price, Sutherland and Rathert, “Process Watch: The (Automotive) Problem With Semiconductors,” Solid State Technology, January 2018.

On-site production an option for supply.

BY DR. PAUL STOCKMAN, Linde Electronics, Taipei, Taiwan

Hydrogen usage at leading-edge logic and foundry fabs has steadily increased over the past 20 years. What was supplied in individual cylinders is now frequently delivered by specialized bulk trucks carrying over one ton of hydrogen per vehicle; some fabs require multiple deliveries per day. With EUV (extreme ultraviolet) lithography nearing commercial, high-volume use, the demand for hydrogen will experience another inflection. In this article, we explain the current and future applications driving this demand, the geographical variation in supply, and on-site production solutions for high-volume customers.

Existing process applications

Hydrogen has been adopted as a material in processes throughout the fab. Its unique chemical properties continue to expand its usefulness. These applications typically use flows of 100s to 1,000s of sccm (standard cubic centimeter per minute):

• Epitaxy: Hydrogen is used as a reducing agent during the epitaxial growth of crystalline thin-films. This is often used to make a starting silicon surface for semiconductor manufacturing by reacting newly cut and polished silicon wafers with trichlorosilane (SiHCl3) in an epi-house or end-user fab. The hydrogen reduces the gas-phase chlorine atoms, and the HCl product is removed from the reactor as a gas. Leading- edge channel materials like strained silicon, silicon- germanium, and germanium are also grown using hydrogen-mediated epitaxy.

• Deposition: Hydrogen can also be incorporated directly into thin-films to disrupt crystal lattices to make them less crystalline, more amorphous. This is often used with silicon thin-films, which need to be made more electrically insulating.

• Plasma etch: Hydrogen and hydrogen-containing plasmas are used to directly react with the surface of the wafer in order to clean or remove unwanted thin films, especially for removing unwanted fluorocarbon deposits on silicon oxides.

• Anneal: Silicon wafers are heated to temperatures over 1,000 C, often at elevated pressure, in order to repair their crystal structures. Hydrogen assists by transferring heat uniformly over the surface of the wafer, and also by penetrating into the crystal lattice to react with atomic impurities.

• Passivation: Hydrogen is used to react and remove native oxides on silicon surfaces and to mediate the reconstruction of silicon-silicon bonds in the final layers of the crystal.

• Ion implantation: With more precision than bulk annealing and passivation, protons produced from hydrogen gas can be implanted to specific depths and concentrations in a thin film using ion implanters. Not only can hydrogen atoms be inserted to modify a thin film, but in higher doses and implantation energies, it can be used to cleave slivers of silicon and sapphire wafers.

• Carrier gas: Hydrogen is used as a carrier gas to entrain (entrap) and transport less volatile chemicals— ordinarily liquids at atmospheric pressure and room temperature—into the reaction chamber. The hydrogen is heated and bubbled through the liquid chemicals. Because the mass of hydrogen is very light compared to entrained chemical vapor, specialized mass flow controllers can then be used to sense, measure, and precisely control the amount of chemical vapor dispensed.

• Material stabilization: The addition of hydrogen extends the shelf life of important electronic materials like diborane (B2H6) and digermane (Ge2H6), which otherwise slowly decompose.

• Polysilicon manufacturing: Although not part of the process flow in semiconductor fabs, hydrogen is used in large quantities in the upstream process of manufacturing polysilicon: thousands of Nm3 per hour hydrogen are used, and typically an on-site hydrogen plant is required. Polysilicon is the starting material for making crystallized silicon, from which silicon wafers are sliced.

Application for EUV

Extreme ultraviolet (EUV) lithography is the much- anticipated new application expected to simplify the process patterning complexity for critical dimensions in leading-edge devices. While it has taken a long time for this technology to come close to commercialization, top-tier manufacturers are coalescing their predictions for volume manufacturing adoption in the 2018-2020 window. Whereas other hydrogen-consuming applica- tions have a usage rate of 100s of sccm, EUV will require much larger flows of 100s of slm (standard liters per minute), or roughly 100 to 1,000x more per individual tool.

Deep ultraviolet (DUV) lithography, the current workhorse of the patterning tools, uses an electrical discharge in neon or krypton mixed with halogen gases like fluorine to produce UV light at 193 nm and 248 nm; EUV light production is much more complicated. Tin metal is heated above its melting point of 232 C, and small droplets of tin (~25 μm diameter) are rapidly (50,000 droplets per second) produced. These droplets are first vaporized and then excited with high-power CO2 lasers. The excited tin atoms emit EUV light at 13.5 nm, which is more than 14 times shorter than the DUV tools.

The light is emitted in all directions and is collected and collimated (aligned) by an array of mirrors. The light is then passed to the primary lithography tool for focusing and image transfer before illuminating the photoresist on the wafer. All materials heavily absorb EUV light. Absorption losses are minimized by using multi-layer reflective optics instead of the transmissive lenses used in DUV lithography, and the entire light source and patterning systems are housed in vacuum chambers. These highly complex tools are expected to cost end users around $100 million USD each, and when fully adopted, a leading-edge fab could require 20 or more of these tools.

Scattered tin debris from the vaporization of droplets is a major potential source of contamination of both the collector and focusing optics. Unmitigated, the lifetimes of these expensive components would be unacceptable. Hydrogen gas is used to shroud the tin excitation region, and tin vapor and aberrant droplets are reacted to form stannane (SnH4), which is then removed from that section of the housing by means of the vacuum line. Higher flows of hydrogen can be used in periodic plasma-based cleaning to remove tin that deposits on the collector optics.

Demand and supply

Even before the adoption of EUV technology, leading- edge logic and foundry processes have begun consuming several normal cubic meters (1,000 liters) of hydrogen per wafer processed. This usage trend is expected to continue increasing in the 10 nm and 7 nm nodes commercialized before wide-spread EUV use. Conse- quently, major fabs now use hundreds of Nm3 per hour. EUV, when fully extended to all of the critical layers, will roughly double the amount of hydrogen used in these fabs. In a related application, the largest LED fabs also use hundreds of Nm3 of hydrogen per hour, primarily as a carrier gas and diluent for the gallium, arsine, and phosphorus precursors used to make the light-emitting devices.

Supply of hydrogen to electronics customers has been historically driven by regional source types, engineering and transportation codes, and by end user preferences and process qualification. However, steep demand curves are causing users to consider new supply schemes for access to larger volumes, greater supply chain security, and lessening of local fab logistics.

Over 60 million metric tons of hydrogen are produced globally, almost exclusively from hydrocarbon feedstocks: natural gas, oil, and coal. Most of this is used as a chemical intermediate to make ammonia, methanol, and trans- portation fuels. Electronics uses much less than 1% of hydrogen, yet relies on industrial technologies and sources as supply origins.

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Hydrogen is supplied in the following modes (FIGURES 1 and 2):

• Cylinders: In smaller volumes, hydrogen is supplied in standard-sized gas cylinders, which hold about 7 m3 of gas pressurized at approximately 175 bar (250 cu ft at 2,500 psi). The largest fabs now consume this amount in less than one minute. Individual cylinders can be manifolded together to create larger packs of cylinders, which are typically mounted into metal pallets for easier handling. These packs can even be arrayed into full truck trailers of connected cylinders. Despite the increased volume, there is a limitation on the level of mass flow that can be safely achieved from this configuration.

• Compressed gaseous hydrogen (CGH) trailers: To improve on both mass distribution and packaging/handling costs, specialized trailers with much larger, pressurizable vessels are used. These CGH (compressed gaseous hydrogen) trailers can hold 10,000 Nm3 at pressures similar to smaller packages, yet are the distribution equiv- alent to over 1,400 individual cylinders. Just as importantly, fewer, larger vessels are faster to fill, and easier to maintain quality to the very high standards required by the semiconductor industry. Fewer components and human interactions also reduce safety risks.

• Liquefied hydrogen transport: In North America and much of Europe, liquefied hydrogen transport is allowed. This further increases the amount of hydrogen per truck to 40,000 Nm3 gas, or the equivalent of around 6,000 cylinders. In addition to increasing the volume, liquefication of hydrogen is also an added purification step. By cooling the material down to the boiling point of 21 K (-252 C), most impurities are solidified and can be reduced in concentration by absorption.

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These benefits come with a trade-off, however. Liquefying hydrogen to the very low required temperatures consumes a lot of energy, and mandates additional safety protocols. Moreover, there are fewer liquid hydrogen production sources versus gaseous facilities, and transportation distances and supply logistics can be substantially increased. It is important to note that liquid hydrogen transport is not allowed in the primary semiconductor producing countries of Asia (China[1], Japan, Singapore, South Korea, and Taiwan), and therefore not a consideration for users in that region.

On-site hydrogen production

A solution that is becoming appropriate for some fabs is on-site hydrogen production (FIGURES 3 and 4). All major fabs already have either direct on-site production of gaseous nitrogen, or are supplied via pipeline by local plants. On-site hydrogen production has similar consid- erations of planning, footprint, redundancy, and back-up.

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• Planning and footprint: On-site gas production should be planned at the outset of the entire fab concept. Like on-site nitrogen production, construction of the hydrogen facility usually begins at the same time as groundbreaking for the fab. The footprint of the plant and auxiliary equipment needs to be accounted for, either on the user’s property, or on an adjacent parcel reserved for the gas supplier. Pipeline delivery needs to be routed. And importantly for hydrogen, permits must be applied for which differ according to location.

• Redundancy and back-up: Continuous supply is essential for all semiconductor material supply chains. On-site production must ensure continuous supply for planned and unplanned equipment downtime, or in the case that fab demand grows past the on-site generating capacity. This can be accomplished by choosing from among three alternatives. If liquefication of on-site generated hydrogen is part of the production and purification scheme, excess hydrogen can be liquefied and stored in cryogenic tanks. Hydrogen generators appropriate to produce semiconductor-grade material are often modular, meaning that several will be used in parallel to make the full requirement of a fab. By installing an additional or redundant module, excess capacity is available in the event of planned maintenance or other event. Finally, off-site hydrogen is usually qualified as a supplement or temporary replacement. Often, this is the original source for the process of record for the manufacturer.

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On-site hydrogen technologies suitable for semiconductor processes are either electrolysis of water, or so-called “reforming” and “shifting” of hydrocarbon feedstocks.

• Electrolysis: Electrolysis uses direct current electricity to split a water molecule into elemental hydrogen and oxygen. Actually, the reaction takes place in two physically distinct electrical poles of the equipment – the anode and the cathode – as two separate half-reactions. The net reaction is

2H2O(l) → 2H2 (g) +O2 (g)

Electrolysis is relatively expensive at volume because of the energy needed to break water molecule bonds even though achieving purity in the feedstock water is relatively simple.

• Steam Reforming and Shifting: More economical are the industrial steam reforming and shifting processes, using hydrocarbon feedstocks like natural gas, LPG (liquefied petroleum gas – mostly propane and butane), and methanol. In fact, this is the process which produces most of the bulk hydrogen already used by existing semiconductor fabs, and is responsible for 95% of global hydrogen production. Natural gas (CH4) and steam are heated over a catalyst to form syngas (a mixture of hydrogen and carbon monoxide).

CH4 +H2O→CO+3H2

The syngas is then separated to give hydrogen. The carbon monoxide can then be further reacted (shifted) with the steam to yield additional hydrogen.

CO+H2O→CO2 +H2

Taken together, these process plants are known as steam methane reformers, or SMR plants. Choices for the exact plant technology depend upon the local feedstocks available and the customer quality profile requirements.

Regardless of whether the hydrogen is supplied in gaseous or liquefied containers or made on-site, semiconductor hydrogen supply schemes incorporate on-site, and often additional point-of-use, purification using various technologies: adsorption, gettering, and application of the unique property of hydrogen to diffuse through palladium metal membranes, which are impervious to most other molecules. In addition, hydrogen purity is monitored at several points in the distribution by multiple types of detectors.

Safety

As with all chemical supplies, safety is paramount. With hydrogen, the main safety risk is associated with its wide range of flammability and explosivity. Throughout production and packaging, multiple types of redundant protocols are used to ensure that no oxidizers are contacted or incorporated into the hydrogen and plant designs minimize the risk for leaks. Specialized clothing resistant to fire and static is worn in some hydrogen producing and using environments. Materials of construction and component qualification are also important to guard against a phenomenon known as hydrogen embrit- tlement, where at elevated temperatures and/or pressures, hydrogen can permeate and weaken certain metals and alloys. Finally, liquefied hydrogen introduces the additional risk associated with cryogenic materials and the need to use insulating vessels and personal protection.

Conclusion

Semiconductor manufacturing has long used hydrogen in an essential and expanding portfolio of applications. Already, hydrogen supply is considered a bulk material scheme, with source, transport, and logistic considerations. The adoption of EUV at leading-edge fabs in the next few years will accelerate the pace of hydrogen consumption, and drive the consideration of new supply schemes. End users should evaluate hydrogen supply options for future fabs as part of their advanced planning to ensure that their quality, supply and process integrity requirements will be met.

References

1. China is in the process of approving liquefied hydrogen transport at the time of this publication. The details are not yet defined.