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Research included in the March Update to the 2018 edition of IC Insights’ McClean Report shows that fabless IC suppliers accounted for 27% of the world’s IC sales in 2017—an increase from 18% ten years earlier in 2007.  As the name implies, fabless IC companies do not operate an IC fabrication facility of their own.

Figure 1 shows the 2017 fabless company share of IC sales by company headquarters location.  At 53%, U.S. companies accounted for the greatest share of fabless IC sales last year, although this share was down from 69% in 2010 (due in part to the acquisition of U.S.-based Broadcom by Singapore-based Avago). Broadcom Limited currently describes itself as a “co-headquartered” company with its headquarters in San Jose, California and Singapore, but it is in the process of establishing its headquarters entirely in the U.S. Once this takes place, the U.S. share of the fabless companies IC sales will again be about 69%.

Figure 1

Figure 1

Taiwan captured 16% share of total fabless company IC sales in 2017, about the same percentage that it held in 2010.  MediaTek, Novatek, and Realtek each had more than $1.0 billion in IC sales last year and each was ranked among the top-20 largest fabless IC companies.

China is playing a bigger role in the fabless IC market.  Since 2010, the largest fabless IC marketshare increase has come from the Chinese suppliers, which captured 5% share in 2010 but represented 11% of total fabless IC sales in 2017.  Figure 2 shows that 10 Chinese fabless companies were included in the top-50 fabless IC supplier list in 2017 compared to only one company in 2009. Unigroup was the largest Chinese fabless IC supplier (and ninth-largest global fabless supplier) in 2017 with sales of $2.1 billion. It is worth noting that when excluding the internal transfers of HiSilicon (over 90% of its sales go to its parent company Huawei), ZTE, and Datang, the Chinese share of the fabless market drops to about 6%.

Figure 2

Figure 2

European companies held only 2% of the fabless IC company marketshare in 2017 as compared to 4% in 2010. The loss of share was due to the acquisition of U.K.-based CSR, the second-largest European fabless IC supplier, by U.S.-based Qualcomm in 1Q15 and the purchase of Germany-based Lantiq, the third-largest European fabless IC supplier, by Intel in 2Q15.  These acquisitions left U.K.-based Dialog ($1.4 billion in sales in 2017) and Norway-based Nordic ($236 million in sales in 2017) as the only two European-based fabless IC suppliers to make the list of top-50 fabless IC suppliers last year.

The fabless IC business model is not so prominent in Japan or in South Korea.  Megachips, which saw its 2017 sales jump by 40% to $640 million, was the largest Japan-based fabless IC supplier.  The lone South Korean company among the top-50 largest fabless suppliers was Silicon Works, which had a 15% increase in sales last year to $605 million.

This work explores the effect of underlying metallic alloys and the influence of Cu loss under via bottom after dry etching and wet cleaning processes. To Improve the Cu loss under via bottom, effective approaches are proposed. The modified actions for via bottom improve not only wafer yield but also reliability of the device.

By CHENG-HAN LEE and REN-KAE SHIUE, Department of Materials Science and Engineering, National Taiwan University, Taiwan, ROC

With metal line dimensional shrinkage in advanced packaging, Cu voids in metal lines cause the failure of via-induced metal-island corrosion. It impacts not only yield loss but also device reliability, specifically electron migration (EM) and stress migration (SM). One of the Cu voids is located under via bottom which is more unpredictable than others. The Cu void under via bottom is caused by integrated processes such as via etch and Cu electro-chemical plating (ECP). It is not similar to the Cu void caused by barrier Cu-seed and ECP Cu. The mechanism of Cu voids under via bottom formation from dry etching and wet cleaning are related to Cu dual-damascene interconnection. Both plasma damage and chemical reaction are proposed to explain its failure mechanism. In the integrated process of Cu interconnects, we can design not only the safety dimension of Cu line via depth but also process criteria with less damage and oxidation in dry etching and wet clean based on Cu loss amount (Cu recess) in TEM inspection. The modified actions for via bottom improve not only wafer yield but also reliability of device.

Introduction

For deep sub-micrometer CMOS integrated circuit, copper (Cu) metallization has been applied in semi- conductor metallization processes of ULSI beyond 0.13 μm technology because of its lower resistivity and better reliability, especially better electron migration resistance than that of aluminum (Al) [1–4]. Under 10 nm technology, front end-of-line (FEOL) device process had already transferred from planar to fin-fet MOS, but the Cu formation process only have slight change in backend-of-line (BEOL) metallization. There are two kinds of schemes, single- and dual- damascene processes. In fact, the main body of Cu interconnection in dual- damascene process includes metal trench and via etching, post etching, wet clean, deposition of barrier films and Cu-seed layer, Cu ECP and Cu chemical mechanical polishing (CMP). They are all similar technologies.

Even though many well-known modifications were implemented in both mature and advanced processes, a few lethal defects which significantly damage wafer yield and device reliability, such as Cu voids and scratches, always exist after Cu-CMP process due to the Cu metal corrosion. Most previous studies in Cu voids, such as Lu et al. [5], Song et al. [6], Wrschka et al. [7] and T.C. Wang et al. [8], were focused on Cu voids on metal line due to wafer yield concern. It meant that Cu voids on metal line could be detected by on-line electron-beam inspection as demonstrated by Guldi et al. [9].

Although Reid et al. [10] have described that the formation of Cu voids could be resulted from step coverage of Cu-seed, waveform function and additives (Accelerator, Suppressor and Leveler), chemical formulation of ECP. However, the mechanism of Cu voids during the via-formation process is still unclear. Coverage or quality of seed layers being poor, thin and/or discontinuous will induce via bottom void which results in deteriorating the plating process. A systematic study of Cu void effects has not been reported. For the mature technology to reduce via resistance, a Cu surface cleaning (pre-cleaning) process prior to deposit the diffusion barrier metal to remove the CuOx on via bottom in order to improve yield was mentioned by Wang et al. [8]. However, it caused a significant Cu loss under via bottom as well as deteriorating reliability window of the process.

With the metal line shrinkage in advanced CMOS process, Cu void under via bottom becomes much crucial than before. Actually, it perhaps is the most important defect in device reliability concern. Unlike Cu voids or pits on metal line, such defects cannot be easily detected by on-line defect screen methodology, neither electrical test nor wafer yield testing. The reason is that Cu interconnection is still valid at that time. The most decisive step of Cu void detection under via bottom is the reliability test. Alers et al. [11] showed that Cu voids affected electron migration resistance. Wang et al. [12] had pointed out that Cu voids under via bottom were the major factor resulting in failure during stress and/or electron migration tests. In our exper- iment, Cu loss under via bottom was strongly related to high temperature storage (HTS) and high temperature operation life (HTOL) reliability tests. Thermal and/or electronic stresses may resulted from many processes, including Si manufacturing, bumping, wafer yield test and even early failure rate (EFR) stage in reliability test. It should be further clarified.

Experimental procedures

A. Cu scheme and process

A via structure consisted of metal chains and via holes as displayed in FIGURE 1. Dual Cu damascene with “via first” process was applied to prepare the test sample. The Cu interconnection was made by BEOL Cu dual-damascene process which included an etching stop layer, dielectric deposition, metal line/via lithography, metal line/via dry etching, post etching wet clean containing deionized water (DIW) with discharging gas, deposition of barrier films and Cu-seed layer, Cu ECP and Cu CMP.

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In advanced technology, EM resistance decreasing with metal line shrinkage of Cu interconnects was a major concern, specifically for dimensions of metal line and via bottom less than 30 nm. As the interconnect dimension shrunk, the EM resistance of Cu interconnects was deteriorated and decreasing the service life of device. In order to improve EM resistance of Cu damascene, doping the Cu interconnects with appropriate elements was one of engineering approaches. Manganese (Mn) is one of the most popular element applied in Cu dopping. Mn could diffuse through the Cu interconnects and segregate along the interface between Cu and low-k dielectric layer. It was served as the barrier layer, adhesion promoter and oxidation retardant because the diffusivity of Mn in Cu was much faster than self-diffusivity of Cu, approximately one order of magnitude higher. It indicated that Mn atoms initially alloyed in Cu were migrated into surface and interface, and formed an oxide layer leaving the pure Cu behind after annealing step. In addition, Mn could also repair discontinuous barrier layer (Ta/TaN) by forming a local manganese silicate diffusion barrier layer. It was so called self-forming Cu-Mn diffusion barriers [13,14].

In this research, both Cu/1% Mn and Cu/1% Al served as underlying alloys were evaluated by Cu recess. The introduction of Cu/1% Al in the test was for the purpose of comparison. The main body of Cu interconnection of dual-damascene process included via etching, post etching wet clean, deposition of barrier films and Cu-seed layer and ECP. They were separated by different key process variables, such as dry etching power split, post etching as well as wet clean discharging gas flow rate split. The effect of these process variables on Cu loss under via bottom was evaluated in the experiment.

B. Methodology

FIGURE 2 illustrated a schematic diagram of Cu recess in the device. The Cu recess of via bottom was observed using the step-by-step TEM followed by dry etch and wet clean processes. The Cu line was receded back into the bottom of Cu metal after the process. The Cu recess data were helpful to define which stage played the crucial role in Cu loss of via bottom. Electrical and wafer yield tests were applied in order to locate any abnormality after all processes were completed.

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To unveil the effects of thermal/electronic stresses on Cu voids under via bottom, HTS (175oC) and HTOL (175oC with double device operation voltages) were performed to evaluate wafer yield swap after HTS and HTOL. Wafer yield swap was able to exam the yield before/after HTS and HTOL. The good die was failed if the Cu loss under via bottom occurred. After wafer yield swap dice was confirmed, failure analysis was performed by focus ion beam (FIB), scanning electron microscope (SEM) and transmission electron microscope (TEM). In addition, the chemical analysis was examined using energy dispersive spectroscope (EDS).

Results and discussion

A special design of metal line via structure with high aspect ratio of approximately 5 was performed in order to deteriorate Cu loss under via bottom. We inspected Cu recess of two different underlying metals, Cu/1% Mn and Cu/1% Al. FIGURE 3 displayed Cu recesses of Cu/1% Al and Cu/1% Mn underlying metals, respectively. Under the same process condition, the Cu recess of Cu/1% Mn was only half of Cu/1% Al, so Cu/1% Mn was more protective than Cu/1% Al. There was a strong correlation between EM cumulative failure rate and the type of underlying metals. Cu/1% Al showed much lower time to failure (TTF) and deteriorated EM performance as compared with that of Cu/1% Mn. It clearly demonstrated that Cu/1% Mn was more protective than Cu/1% Al, and failure rate of Cu/1% Mn was only 1/30 of Cu/1%. The performance of Cu/1% Al was significantly inferior to that of Cu/1% Mn. Therefore, Cu/1% Al was selected in following tests in order to enhance the differences of other key process variables.

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In the standard (STD) condition, Cu recess was inspected by step-by-step TEM of dry etching and post etching wet clean with discharging gas process, and there were approximately 5nm and 7nm (12nm–5nm=7nm)in depth of Cu loss as shown in FIGURE 4. The following barrier films and Cu-seed process only slightly consumed underlying Cu. The Cu recess only slightly increased 0.3 nm in barrier film deposition process. The pre-cleaning process was necessary before barrier film deposition in order to remove CuO on Cu surface for improved adhesion. Based on observations of Cu recess results in step-by-step TEM, post etching wet clean process also played an important role in Cu recess of via bottom.

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Dry etching by plasma not only eroded about 5nm in depth of Cu under the via bottom but also oxidized the underlying Cu which was supposed to be removed in subsequent wet cleaning process. Post etching wet clean included applying chemical solvent to clean by-product of dry etching and DI water clean to remove the chemical solvent. The DI water was with aid of discharging gas, such as CO2, in order to neutralize the accumulated charge generated by the plasma in previous dry etching. However, the discharging gas acidified the DI water and resulted in Cu loss in post etching wet cleaning process.

FIGURE 5 shows Cu recesses with different dry etching power splits. The change of plasma power split changed the degree of Cu recess. At the condition of 200 W less than STD, i.e., STD-200W, the Cu recess was less than 3nm. Although the structure looks good in shape, poor performance was observed from electrical test and wafer yield after the process was completed. Via open resulted in upper Cu disconnected from underlying Cu as demonstrated by TEM observation (Fig. 5). It was deduced that dry etching process did not etch entire via hole, especially for the dielectric layer. Although post wet cleaning slightly extended the open area under via bottom, barrier films were not well deposited on the via hole. Therefore, poor coating was obtained from the subsequent ECP process. The via resistance marked up significantly as the dry etching power decreased to 200 W less than STD, i.e., STD-200W.

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FIGURE 6 shows wafer yields after open/short tests with different dry etching power splits. In the open/short tests, the failure rate was decreased with decreasing the dry etching power from STD+100W to STD-100W due to less damage to the Cu substrate for lower dry etching power. The Cu recess was decreased from 17.9 nm (STD+100W) to 8.7 nm (STD-100W) as demonstrated in FIGURE 5. However, dramatically increased failure rate was observed when the dry etching power was decreased to 200 W less than STD (STD-200 W). Because the lowest dry etching power, STD-200W, was insufficient to enlarge the via hole, and resulted in increasing the via resistance. Therefore, the failure rate of STD-200W was as high as 10% as displayed in Fig. 6. There was an optimal dry etching power of STD-100W in order to maximize the wafer yield in the experiment.

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FIGURE 7 showed the variation of Cu recess with different discharging gas flow splits in the post etching wet cleaning process. The discharging gas flow was strongly related to the Cu recess, and it demonstrated that the chemical property of wet clean also played a crucial role in Cu recess. FIGURE 8 showed that the wafer yield failure rate was decreased with decreasing the post wet clean discharging flow from STD+200 sccm to STD-400 sccm. The major function of discharging gas, CO2, neutralized the accumulated charge generated by the plasma in previous dry etching. It was necessary in post etching wet cleaning process. However,it should be kept below STD-300sccm in order to improve wafer yield in the experiment.

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The reliability test result of HTOL with thermal and electronic stresses over 168 hours showed several good chips transferred to bad ones with open short bin, which was called bin swap. FIB, SEM, TEM and EDS were used in failure analyses. FIGURE 9 showed the comparison of Cu recesses before and after HTOL tests for 168 hours. It was obvious that a deeper Cu recess was observed after stress applied. Before the stress applied, the via interconnect linked with underlying metal line. This is the key reason why it was difficult to detect this type of failure in the electrical test. In Fig. 9, the Cu recess before stress applied was 23.3 nm and it extended into 42.4 nm after HTOL test for 168 hours. The Cu recess extended into twice or even triple after thermal and electronic stresses applied. Therefore, quality of the via bottom joint was greatly deteriorated if there were Cu voids under the via bottom. With increasing applied thermal and electrical stresses to via bottom, the crack propagated to entire via bottom. The via bottom finally was disconnected from underlying metal line. It was so-called via open in semiconductor industry.

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FIGURE 10 showed TEM bright field and EDS mapping of Ta at the failure location after HTOL for 168 hours. Taking a close look at the via bottom next to the interface of underlying metal line, the non-uniform barrier film was widely observed as shown in Fig. 10(a). It was the original failure location. In Fig. 10(a), TEM inspection of the failure location after HTOL test for 168 hours showed significant Cu loss, more than 30 nm, under via bottom. It was much greater than the Cu recess before thermal and electrical stress applied (12 nm). Based on the EDS mapping of Ta (Fig. 10(b)), the barrier film, TaN, was formed adjacent to the Cu loss of via bottom. It was important to note that the TaN was almost disappeared from corner of the via bottom. The disconnection of barrier film from the corner resulted in deteriorated Cu interface, and the Cu began to degen- erate and shrink under applied thermal and electronic stresses. It finally resulted in separation of the upper and underlying Cu. The via bottom was completely opened and caused the failure of device.

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Summary

With the metal line dimensional shrinkage in advanced packaging, Cu metallization has increased the concerns on long-term reliability of devices caused by Cu loss under via bottom. This work explores the effect of underlying metallic alloys and the influence of Cu loss under via bottom after dry etching and wet clean. Important conclusions are listed below:

1. Cu/1% Mn is more protective than original Cu/1% Al. The application of Cu/1% Mn improves both EM and SM resistances of via bottom.

2. Both plasma power of dry etching and the discharging gas flow of wet clean play important roles in the Cu loss under via bottom. Cu loss was initiated first after dry etching due to plasma damage. The plasma not only etched the underlying Cu of via bottom, but also oxidized the underlying Cu surface. Subsequent post etching wet clean with acidic water generated by discharging gas removes CuO at interface, and causes more Cu loss in subsequent wet cleaning process. They are the major mechanism of Cu loss under via bottom. Pre-cleaning of barrier films to remove superficial CuO on Cu for better adhesion is only a minor factor in Cu loss under via bottom.

3. To Improve the Cu loss under via bottom, effective approaches include applying protective metal line, such as Cu/ 1% Mn, minimizing interfacial damage by decreasing the power of dry etching, and the discharge gas flow of post etching.

Acknowledgement

Authors greatly acknowledge the support of Taiwan Semiconductor Manufacturing Company (TSMC) for this study.

References

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4. M.H. Tsai, R. Augur, V. Blaschke, R.H. Havemann, E.F. Ogawa, P.S. Ho, W.K. Yeh, S.L. Shue, C.H Yu, M.S. Liang, “Electromigration reliability of dual damascene Cu/CVD SiOC interconnects”, in: Proceedings of the 2001 International Interconnect Technology Conference, IEEE (2001).
5. J.P. Lu, L. Chen, D. Gonzalez, H.L. Guo, D.J. Rose, M. Marudachalam, W.U. Hsu, H.Y. Liu, F. Cataldi, B. Chatterjee, P.B. Smith, P. Holverson, R.L. Guldi, N.M. Russell, G. Shinn, S. Zuhoski, J.D. Luttmer, “Understanding and eliminating defects in electroplated Cu films”, in: Interconnect Technology Conference, Proceedings of the IEEE 2001 International (2001), p. 280.
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9. R.L. Guldi, J.B. Shaw, J. Ritchison, S. Oestreich, K. Davis, R. Fiordalice, “Characterization of copper voids in dual damascene processes”, in: Proceedings of Advanced Semiconductor Manufac- turing 2002 IEEE/SEMI Conference and Workshop (2002), p. 351.
10. J. Reid, V. Bhaskaran, R. Contolini, E. Patton, R. Jackson, E. Broadbent, T. Walsh, S. Mayer, R. Schetty, J. Martin, M. Toben, S. Menard, “Optimization of damascene feature fill for copper electro- plating process”, in: Proceedings of Interconnect Technology, IEEE International Conference (1999), p. 284.
11. G.B. Alers, D. Dornisch, J. Siri, K. Kattige, L. Tam, E. Broadbent, G.W. Ray, “Trade-off between reliability and post-CMP defects during recrystallization anneal for copper damascene interconnects”, in: Reliability Physics Symposium, 2001. Proceedings of the 39th Annual 2001 IEEE International (2001), p. 350.
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By Jay Chittooran, SEMI Public Policy

Following through on his 2016 campaign promise, President Trump is implementing trade policies that buck conventional wisdom in Washington, D.C. and among U.S. businesses. Stiff tariffs and the dismantling of longstanding trade agreements – cornerstones of these new actions – will ripple through the semiconductor industry with particularly damaging effect. China, a chief target of criticism from President Trump, has again found itself in the crosshairs of the administration, with trade tensions rising to a fever pitch.

The Trump Administration has long criticized China for what it considers unfair trade practices, often zeroing in on intellectual property. In August 2017, the Office of the U.S. Trade Representative (USTR), charged with developing and recommending U.S trade policy to the president, launched a Section 301 investigation into whether China’s practice of forced technology transfer has discriminated against U.S. firms. As the probe continues, it is becoming increasingly clear that the United States will impose tariffs on China based on its current findings. Reports suggest that the tariffs could come soon, hitting a range of products from consumer electronics to toys. Other measures could include tightening restrictions on the trade of dual-use goods – those with both commercial and military applications – curbing Chinese investment in the United States, and imposing strict limits on the number of visas issued to Chinese citizens.

With China a major and intensifying force in the semiconductor supply chain, raising tariffs hangs like the Sword of Damocles over the U.S. and global economies. A tariff-ignited trade war with China could stifle innovation, undermine the long-term health of the semiconductor industry, and lead to unintended consequences such as higher consumer prices, lower productivity, job losses and, on a global scale, a brake on economic growth.

Other recently announced U.S. trade actions could also cloud the future for semiconductor companies. The Trump administration, based on two separate Section 232 investigations claiming that overproduction of both steel and aluminum are a threat to U.S. national security, recently levied a series of tariffs and quotas on every country except Canada and Mexico. While these tariffs have yet to take effect, the mere prospect has angered U.S. trading partners – most notably Korea, the European Union and China. Several countries have threatened retaliatory action and others have taken their case to the World Trade Organization.

Trade is oxygen to the semiconductor industry, which grew by nearly 30 percent last year and is expected to be valued at an estimated $1 trillion by 2030. Make no mistake: SEMI fully supports efforts to buttress intellectual property protections. However, the Trump administration’s unfolding trade policy could antagonize U.S. trade partners.

For its part, SEMI is weighing in with USTR on these issues, underscoring the critical importance of trade to the semiconductor industry as we educate policymakers on trade barriers to industry growth and encourage unobstructed cross-border commerce to advance semiconductors and the emerging technologies they enable. On behalf of our members, we continue our work to increase global market access and lessen the regulatory burden on global trade. If you are interested in more information on trade, or how to be involved in SEMI’s public policy program, please contact Jay Chittooran, Public Policy Manager, at [email protected].

Originally published on the SEMI blog.

The ConFab — an executive invitation-only conference now in its 14th year — brings together influential decision-makers from all parts of the semiconductor supply chain for three days of thought-provoking talks and panel discussions, networking events and select, pre-arranged breakout business meetings.

In the 2018 program, we will take a close look at the new applications driving the semiconductor industry, the technology that will be required at the device and process level to meet new demands, and the kind of strategic collaboration that will be required. It is this combination of business, technology and social interactions that make the conference so unique and so valuable. Browse this slideshow for a look at this year’s speakers, keynotes, panel discussions, and special guests.

Visit The ConFab’s website for a look at the full, three-day agenda for this year’s event.

KEYNOTE: How AI is Driving the New Semiconductor Era

Rama Divakaruni_June_2014presented by Rama Divakaruni, Advanced Process Technology Research Lead, IBM

The exciting results of AI have been fueled by the exponential growth in data, the widespread availability of increased compute power, and advances in algorithms. Continued progress in AI – now in its infancy – will require major innovation across the computing stack, dramatically affecting logic, memory, storage, and communication. Already the influence of AI is apparent at the system-level by trends such as heterogeneous processing with GPUs and accelerators, and memories with very high bandwidth connectivity to the processor. The next stages will involve elements which exploit characteristics that benefit AI workloads, such as reduced precision and in-memory computation. Further in time, analog devices that can combine memory and computation, and thus minimize the latency and energy expenditure of data movement, offer the promise of orders of magnitude power-performance improvements for AI workloads. Thus, the future of AI will depend instrumentally on advances in devices and packaging, which in turn will rely fundamentally on materials innovations.

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IC Insights’ latest market, unit, and average selling price forecasts for 33 major IC product segments for 2018 through 2022 is included in the March Update to the 2018 McClean Report (MR18).  The Update also includes an analysis of the major semiconductor suppliers’ capital spending plans for this year.

The biggest adjustments to the original MR18 IC market forecasts were to the memory market; specifically the DRAM and NAND flash segments.  The DRAM and NAND flash memory market growth forecasts for 2018 have been adjusted upward to 37% for DRAM (13% shown in MR18) and 17% for NAND flash (10% shown in MR18).

The big increase in the DRAM market forecast for 2018 is primarily due to a much stronger ASP expected for this year than was originally forecast.  IC Insights now forecasts that the DRAM ASP will register a 36% jump in 2018 as compared to 2017, when the DRAM ASP surged by an amazing 81%.  Moreover, the NAND flash ASP is forecast to increase 10% this year, after jumping by 45% in 2017.  In contrast to strong DRAM and NAND flash ASP increases, 2018 unit volume growth for these product segments is expected to be up only 1% and 6%, respectively.

At $99.6 billion, the DRAM market is forecast to be by far the largest single product category in the IC industry in 2018, exceeding the expected NAND flash market ($62.1 billion) by $37.5 billion.  Figure 1 shows that the DRAM market has provided a significant tailwind or headwind for total worldwide IC market growth in four out of the last five years.

The DRAM market dropped by 8% in 2016, spurred by a 12% decline in ASP, and the DRAM segment became a headwind to worldwide IC market growth that year instead of the tailwind it had been in 2013 and 2014.  As shown, the DRAM market shaved two percentage points off of total IC industry growth in 2016.  In contrast, the DRAM segment boosted total IC market growth last year by nine percentage points. For 2018, the expected five point positive impact of the DRAM market on total IC market growth is forecast to be much less significant than it was in 2017.

Figure 1

Figure 1

Qualcomm Incorporated (NASDAQ: QCOM) received a Presidential Order to immediately and permanently abandon the proposed takeover of Qualcomm by Broadcom Limited (NASDAQ: AVGO). Under the terms of the Presidential Order, all of Broadcom’s director nominees are also disqualified from standing for election as directors of Qualcomm.

Qualcomm was also ordered to reconvene its 2018 Annual Meeting of Stockholders on the earliest possible date, which based on the required 10-day notice period, is March 23, 2018. Stockholders of record on January 8, 2018 will be entitled to vote at the meeting.

Broadcom’s official statement after receiving the order was to strongly disagree that its proposed acquisition of Qualcomm raises any national security concerns.

“This should be viewed as a very positive event not only for Qualcomm but also for the market as a whole,” said Stuart Carlaw, Chief Research Officer at ABI Research. “The combined entity would have had dangerously dominant positions in some core markets such as location technologies, Wi-Fi, Bluetooth, RF hardware and automotive semiconductors. A diverse supplier ecosystem will be key to supporting the IoT as well as vertical market developments such as smart mobility and smart manufacturing.”

The Presidential Order is available at: https://www.whitehouse.gov/presidential-actions/presidential-order-regarding-proposed-takeover-qualcomm-incorporated-broadcom-limited/.

 

“Si photonics growth is now confirmed,” announced Dr. Eric Mounier from Yole Développement (Yole). “Therefore, the development of Si photonics technologies is especially driven by the intra & inter data center applications. Silicon photonics is today one of the most valuable answers to high data rate/low cost for distances beyond VCSEL’s reach.”

The market research and strategy consulting company, Yole investigates the Si photonics sector for years now and was already announcing its take-off in 2017. This year, the trend is confirmed, strongly supported by the needs of data management and performances. Si photonics market forecasts are impressive: Yole’s analysts announce a US$560 million market value at chip level and an almost US$4 billion market at transceiver level, both in 2025. The Si photonics technology has reached its tipping point with lot of positive signs: Yole announces transceiver volume-shipping via two major players, Luxtera and Intel as well as a maturing supply chain. In addition, Yole’s analysts highlights the development of new startups and additional products reaching the market, mostly for 100G but soon for 200/400G. At the end, the market is showing very encouraging signs in terms of growing investments from the VC community.

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Yole, in collaboration with Jean-Louis Malinge, former CEO of Kotura, now at ARCH Venture Partners proposes a comprehensive analysis of the Si photonic industry, Silicon Photonics. It is a high added-value introduction to the silicon photonics technology, including market forecasts, description of applications and supply chain as well as manufacturing trends and challenges. Jean-Louis Malinge will attend OFC 2018 taking place this week in San Diego to meet the Si photonics companies.

The tipping point of the Si photonic industry is only at the very beginning, since there is massive, ongoing global development geared towards further integration. Indeed, Si Photonics today is restricted to the data center market and still competes with VCSEL, which continues to improve In parallel, metropolitan/long-haul applications are not still the main Si photonic targets since the cost is still too high. Long-haul require reliable components and volumes that are not interesting for SiPh. However, as FTTH specifications would converge to Metropolitan networks, this application could also be accessible to Si photonic solutions:

  •  The recent involvement of large IC foundries is a very encouraging sign that portends big things for Si photonics. They include: TSMC with Luxtera, GlobalFoundries with Ayar Labs…
•  The “zero-change”: it means manufacturing optical components without making any changes to a CMOS process. This processes currently in development target future inter-chip optical interconnects that could represents a huge market volume.
•  Datacom and telecom are not the only applications. As silicon photonics is an integration technology platform, it can also be used for sensing application where volume/small form factor are required: medical and automotive applications.

The analysis will not be completed if GAFAMs were not part of the game. Therefore, in development for years, Si photonics is still pushed hard by these major companies, due to their impressive advantages including low cost, higher integration, more embedded functionalities, higher interconnect density, lower power consumption, and better reliability compared with legacy optics and more. Big OEMs like Facebook, Google, and Amazon develop their own optical data center technology in partnership with chip firms. Indeed, while traffic continues to increase between users and data centers across the internet, more and more data communication is taking place within the data center. Current data center switching and interconnects make it difficult and costly to cope with this increasing flow. In this context, new approaches are necessary.

To identify the evolution of this industry and identify latest innovations, the consulting company is daily discussing with Si photonics players.

The latest update to the SEMI World Fab Forecast report, published on February 28, 2018, reveals fab equipment spending will increase at 5 percent in 2019 for a remarkable fourth consecutive year of growth as shown in figure 1. China is expected to be the main driver of fab equipment spending growth in 2018 and 2019 absent a major change in its plans. The industry had not seen three consecutive years of growth since the mid-1990s.

Figure 1

Figure 1

SEMI predicts Samsung will lead in fab equipment spending both in 2018 and 2019, with Samsung investing less each year than in 2017.  By contrast, China will dramatically increase year-over-year fab equipment spending by 57 percent in 2018 and 60 percent in 2019 to support fab projects from both multinationals and domestic companies. The China spending surge is forecast to accelerate it past Korea as the top spending region in 2019.

After record investments in 2017, Korea fab equipment spending will decline 9 percent, to US$18 billion, in 2018 and an additional 14 percent, to US$16 billion, in 2019. However both years will outpace pre-2017 spending levels for the region. Fab equipment spending in Taiwan, the third-largest region for fab investments, will fall 10 percent to about US$10 billion in 2018, but is forecast to rebound 15 percent to over US$11 billion in 2019. (Details about other regions’ spending trends are available in SEMI’s latest World Fab Forecast.)

As expected, China’s fab equipment spending is increasing as projects shift to equipment fabs constructed earlier in this cycle.  The record 26 volume fabs that started construction in China in 2017 will begin equipping this year and next.  See figure 2.

Figure 2

Figure 2

Non-Chinese companies account for the largest share of fab equipment investment in China. However, Chinese-owned companies are expected to ramp up fabs in 2019, increasing their share of spending in China from 33 percent in 2017 to 45 percent in 2019.

Product Sector Spending

3D NAND will lead product sector spending, growing 3 percent each in 2018 and 2019, to US$16 billion and US$17 billion, respectively. DRAM will see robust growth of 26 percent in 2018, to US$14 billion, but is expected to decline 14 percent to US$12 billion in 2019.  Foundries will increase equipment spending by 2 percent to US$17 billion in 2018 and by 26 percent to US$22 billion in 2019, primarily to support 7nm investments and ramp of new capacity.

Most people have felt that sting from grabbing a doorknob after walking across a carpet or seen how a balloon will stick to a fuzzy surface after a few moments of vigorous rubbing.

While the effects of static electricity have been fascinating casual observers and scientists for millennia, certain aspects of how the electricity is generated and stored on surfaces have remained a mystery.

Now, researchers have discovered more details about the way certain materials hold a charge even after two surfaces separate, information that could help improve devices that leverage such energy as a power source.

“We’ve known that energy generated in contact electrification is readily retained by the material as electrostatic charges for hours at room temperature,” said Zhong Lin Wang, Regents’ Professor in the School of Materials Science and Engineering at the Georgia Institute of Technology. “Our research showed that there’s a potential barrier at the surface that prevents the charges generated from flowing back to the solid where they were from or escaping from the surface after the contacting.”

Georgia Tech professor Zhong Lin Wang poses with an array of 1,000 LED lights that can be illuminated by power produced by the force of a shoe striking a triboelectric generator placed on the floor. (Credit: Rob Felt, Georgia Tech).

Georgia Tech professor Zhong Lin Wang poses with an array of 1,000 LED lights that can be illuminated by power produced by the force of a shoe striking a triboelectric generator placed on the floor. (Credit: Rob Felt, Georgia Tech).

In their research, which was reported in March in the Advanced Materials, the researchers found that electron transfer is the dominant process for contact electrification between two inorganic solids and explains some of the characteristics already observed about static electricity.

“There has been some debate around contact electrification – namely, whether the charge transfer occurs through electrons or ions and why the charges retain on the surface without a quick dissipation,” Wang said.

It’s been eight years since Wang’s team first published research on triboelectric nanogenerators, which employ materials that create an electric charge when in motion and could be designed to harvest energy from a variety of sources such as wind, ocean currents or sound vibrations.

“Previously we just used trial and error to maximize this effect,” Wang said. “But with this new information, we can design materials that have better performance for power conversion.”

The researchers developed a method using a nanoscale triboelectric nanogenerator – composed of layers either of titanium and aluminum oxide or titanium and silicone dioxide – to help quantify the amount of charge accumulating on surfaces during moments of friction.

The method was capable of tracking the accumulated charges in real time and worked over a wide range of temperatures, including very high ones. The data from the study indicated that the characteristics of the triboelectric effect, namely, how electrons flowed across barriers, were consistent with the electron thermionic emission theory.

By designing triboelectric nanogenerators that could withstanding testing at high temperatures, the researchers also found that temperature played a major role in the triboelectric effect.

“We never realized it was a temperature dependent phenomenon,” Wang said. “But we found that when the temperature reaches about 300 Celsius, the triboelectric transfer almost disappears.”

The researchers tested the ability for surfaces to maintain a charge at temperatures ranging from about 80 degrees Celsius to 300 degrees Celsius. Based on their data, the researchers proposed a mechanism for explaining the physics process in triboelectrification effect.

“As the temperature rises, the energy fluctuations of electrons become larger and larger,” the researchers wrote. “Thus, it is easier for electrons to hop out of the potential well, and they either go back to the material where they came from or emit into air.”

By Emmy Yi

The solar energy sector shined in a global renewable energy market that maintained steady growth last year despite the United States’ shocking withdrawal from the Paris Agreement. Solar panel costs dropped to an all-time low, driving global demand that surpassed the 100GW mark for the first time on the strength of standout annual 26 percent growth.

Taiwan has vigorously pursued a transition to renewable energy since 2016. Most notably, Taiwan is phasing out nuclear power as it increases its reliance on climate-friendly energy sources and seeks more foreign investment. The hope is also to boost economic growth and create more jobs.

With its limited land space, the region is fertile ground for rooftop photovoltaic system (PV) systems. In 2016, the Taiwan government set out on an ambitious plan to achieve 3,000MW of installed capacity by 2020 – enough to supply electricity for 1 million households while improving air quality, help spruce up the urban landscape and generate jobs.

The SEMI Taiwan Energy Group fully backs the government renewable-energy policy. Earlier this year, the group gathered more than 200 industry professionals and government officials to explore challenges and opportunities in deploying more rooftop PV systems. Here are some key takeaways:

Infrastructure Reliability Key to High Return on Investment

Size, reliability and safety are paramount in rooftop PV system design. To make the best use of space, reduce the cost per kWh, and ensure a long-term, stable supply of electric energy, the PC modules must be:

  • Compact to fit within limited rooftop space
  • Robust to endure extreme temperatures over long periods; resist fire, salt and water damage; and ensure safe, reliable operation

Financial Institutions Play an Important Role

In response to the government energy policy, domestic financial institutions have funded select projects or issued bonds and derivative products to support the development of Taiwan’s renewables industry. A key part of these efforts is to evaluate risks in areas such as system module safety, maturity of technologies and designs, energy-generating efficiency and maintenance costs.

A Truly Green Industry: Circular Economy

Energy storage systems are maturing rapidly to support expanding markets for renewable energy products. The market for home renewable energy systems is growing, fueled in part by low prices, and the adoption of electric vehicles continues to rise as advances in energy storage technology drive down costs and enable longer ranges. At the current pace of technological development, the world could be using 100 percent renewable energy to achieve the goal of zero emission by 2025. However, to achieve a truly pollution-free environment, a circular economy – marked by the regeneration and reuse of resources – must be established.

For its part, the SEMI Taiwan Energy Group this year will transform the 11-year-old PV Taiwan exhibition into Energy Taiwan, Taiwan’s largest international platform for facilitating communication and collaboration of the entire renewable energy ecosystem. Exhibition themes will range from solar energy, wind energy, hydrogen energy and fuel cells to green transportation, smart energy storage and green finance. The event reflects the consolidation of the SEMI Taiwan Energy Group’s growing resources and its commitment to a circular economy free of fossil fuels.

Originally published on the SEMI blog.