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Each year, Solid State Technology turns to industry leaders to hear viewpoints on the technological and economic outlook for the upcoming year. Read through these expert opinions on what to expect in 2018.

Enabling the AI Era with Materials Engineering

Screen Shot 2018-03-05 at 12.24.49 PMPrabu Raja, Senior Vice President, Semiconductor Products Group, Applied Materials

A broad set of emerging market trends such as IoT, Big Data, Industry 4.0, VR/AR/MR, and autonomous vehicles is accelerating the transformative era of Artificial Intelligence (AI). AI, when employed in the cloud and in the edge, will usher in the age of “Smart Everything” from automobiles, to planes, factories, buildings, and our homes, bringing fundamental changes to the way we live

Semiconductors and semiconductor processing technol- ogies will play a key enabling role in the AI revolution. The increasing need for greater computing perfor- mance to handle Deep Learning/Machine Learning workloads requires new processor architectures beyond traditional CPUs, such as GPUs, FPGAs and TPUs, along with new packaging solutions that employ high-density DRAM for higher memory bandwidth and reduced latency. Edge AI computing will require processors that balance the performance and power equation given their dependency on battery life. The exploding demand for data storage is driving adoption of 3D NAND SSDs in cloud servers with the roadmap for continued storage density increase every year.

In 2018, we will see the volume ramp of 10nm/7nm devices in Logic/Foundry to address the higher performance needs. Interconnect and patterning areas present a myriad of challenges best addressed by new materials and materials engineering technologies. In Inter- connect, cobalt is being used as a copper replacement metal in the lower level wiring layers to address the ever growing resistance problem. The introduction of Cobalt constitutes the biggest material change in the back-end-of-line in the past 15 years. In addition to its role as the conductor metal, cobalt serves two other critical functions – as a metal capping film for electro- migration control and as a seed layer for enhancing gapfill inside the narrow vias and trenches.

In patterning, spacer-based double patterning and quad patterning approaches are enabling the continued shrink of device features. These schemes require advanced precision deposition and etch technologies for reduced variability and greater pattern fidelity. Besides conventional Etch, new selective materials removal technologies are being increasingly adopted for their unique capabilities to deliver damage- and residue-free extreme selective processing. New e-beam inspection and metrology capabilities are also needed to analyze the fine pitch patterned structures. Looking ahead to the 5nm and 3nm nodes, placement or layer-to-layer vertical alignment of features will become a major industry challenge that can be primarily solved through materials engineering and self-aligned structures. EUV lithography is on the horizon for industry adoption in 2019 and beyond, and we expect 20 percent of layers to make the migration to EUV while the remaining 80 percent will use spacer multi- patterning approaches. EUV patterning also requires new materials in hardmasks/underlayer films and new etch solutions for line-edge-roughness problems.

Packaging is a key enabler for AI performance and is poised for strong growth in the coming years. Stacking DRAM chips together in a 3D TSV scheme helps bring High Bandwidth Memory (HBM) to market; these chips are further packaged with the GPU in a 2.5D interposer design to bring compute and memory together for a big increase in performance.

In 2018, we expect DRAM chipmakers to continue their device scaling to the 1Xnm node for volume production. We also see adoption of higher perfor- mance logic technologies on the horizon for the periphery transistors to enable advanced perfor- mance at lower power.

3D NAND manufacturers continue to pursue multiple approaches for vertical scaling, including more pairs, multi-tiers or new schemes such as CMOS under array for increased storage density. The industry migration from 64 pairs to 96 pairs is expected in 2018. Etch (high aspect ratio), dielectric films (for gate stacks and hardmasks) along with integrated etch and CVD solutions (for high aspect ratio processing) will be critical enabling technologies.

In summary, we see incredible inflections in new processor architectures, next-generation devices, and packaging schemes to enable the AI era. New materials and materials engineering solutions are at the very heart of it and will play a critical role across all device segments.

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BY RYAN PEARMAN, D2S, Inc., San Jose, CA

There are big changes on the horizon for semiconductor mask manufacturing, including the imminent first production use of multi-beam mask writers, and the preparation of all phases of semiconductor manufacturing for the introduction of extreme ultra-violet (EUV) lithography within the next few years. These changes, along with the increasing use of multiple patterning and inverse- lithography technology (ILT) with 193i lithography, are driving the need for more detailed and more accurate modeling for mask manufacturing.

New solutions bring new mask modeling challenges

Both EUV and multi-beam mask writing provide solutions to many long-standing challenges for the semiconductor industry. However, they both create new challenges for mask modeling as well. Parameters once considered of negligible impact must be added to mask models targeted for use with EUV and/or multi-beam mask writers. In particular, the correct treatment of dose profiles has emerged as a critical component for mask models targeting these new technologies. This is in addition to scattering effects, such as the well-known EUV mid-range scatter, that must be included in mask models to accurately predict the final mask results. Gaussian models, which form the basis for most traditional mask models, will not be sufficient as many of these new parameters are more properly represented with arbitrary point-spread functions (PSFs).

The most obvious – and most desperately needed – benefit of EUV lithography is greater accuracy due to its enhanced resolution. However, this benefit comes along with a mask-making challenge: wafer-printing defects due to mask errors will appear more readily because of this enhanced resolution. Therefore, the introduction of EUV will require the mean-to-target (MTT) variability on photomasks to become smaller. From a mask manufacturability perspective, all sources of printing errors, systematic and random, must be improved. This means that mask models must also be more accurate, not only in predicting measurements, but also in predicting variability.

A well-known challenge for EUV mask modeling is the EUV mid-range scatter effect. The more complex topology of EUV masks leads to broader scattering effects. In addition to “classical” forward- and back-scatter effects, which dominate 193i lithography, there is a mid-range (1μm) scatter that now requires modeling. This phenomenon is non-Gaussian in nature, so cannot be simulated accurately with simple Gaussian (“1G”) models. In combination with better treatment of resist effects, a PSF-based model is a much better represen- tation of the critical lithography process.

The eagerly anticipated introduction of EUV will demand a lower-sensitivity resist to be used for EUV masks due to the smaller size of EUV features. This is one of the reasons why multi-beam mask writers have emerged as the replacement for variable shaped beam (VSB) tools for the next generation of mask writers. Slower resists require higher currents, and VSB tools today are limited thermally in ways the massively parallel multi-beam tools are not. In addition to thermal effects, VSB mask writers are runtime-limited by shot count; we are already approaching the practical limit for many advanced masks. Shot count is only expected to grow in the future as pitches shrink and complex small features become prevalent in EUV masks – and even in 193i masks due to increased use of ILT to improve process windows for 193i lithography.

In contrast to VSB mask writers, which use shaped apertures to project the shapes (usually rectangles) created by optical-proximity correction (OPC) onto the mask, multi-beam mask writers rasterize the desired mask shapes into a field of pixels, each of which are written by one of hundreds of thousands of individual beamlets (FIGURE 1). This enables multi-beam mask writers to write masks in constant time, no matter how complicated the mask shapes. Each of these beamlets can be turned on and off independently to create the desired eBeam input, which enables the fine resolution of smaller shapes. However, it also means that the dose profiles for the multi-beam writers are far more complex, leading to the need for more advanced, separable dose and shape modeling.

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Since the beamlets of a multi-beam tool are smaller than the primary length-scale of the dose blur, a key second advantage of multi-beam writers emerges: the patterns written are intrinsically curvilinear. In contrast, VSB mask writers can only print features with limited shapes – principally rectangular and 45-degree diagonals, although some tools enable circular patterns. The critical process-window enhancements for ILT also rely on curvilinear mask shapes, so a synergy appears: better treatment of curved edges at the mask writing step will lead to better wafer yield.

Dose and shape: New requirements for multi- beam and EUV mask models

Multi-beam mask writers, EUV masks, and even the proliferation of ILT will require mask models to change substantially. Until very recently, curvi-linear mask features have been ignored when characterizing masks, and models, when used, have assumed simplicity. Primary electron blur (“forward scattering”), including chemically amplified resist (CAR) effects, historically have been assumed to be a set of Gaussians, with length scales between 15nm and 300nm. All other effects of the mask making processes – long-range electron scattering (“back-scatter” and “fogging”), electron charging, devel- opment, and plasma-etching effects – have either been assumed to be constant regardless of mask shape or the dose applied, or have been accounted for approxi- mately by inline corrections in the exposure tool.

To meet the challenges posed by both EUV and multi- beam writing – especially since they are likely to be employed together – mask models will need to treat dose and shape separately, and to explicitly account for the various scattering, fogging, etch, and charging effects (FIGURE 2).

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When masks were written entirely at nominal dose, dose-based effects could be handled together with shape-based effects as a single term. Several years ago, overlapping shots were introduced by D2S for VSB tools to both improve margins and reduce shot-count for complex mask shapes. At this time, it became clear that dose modulation (including overlapping shots) required specific modeling. Some effects (like etch) varied only with respect to the resist contour shapes, while other print bias effects were based on differences in exposure slope near the contour edge. For all the complexity of VSB overlapping shots, all identical patterns were guaranteed to print in the same way. Today, with multi-beam writers, there are significant translational differences in features due to dose-profile changes as they align differently with the multi-beam pixel grid.

We discussed earlier that multi-beam tools print curvi-linear shapes. We should point out that even Manhattan designs become corner-rounded on the actual masks at line ends, corners, and jogs. Why? Physics is almost never Manhattan, and treating it as such will be inaccurate, as in the case of etching effects computed in the presence of Manhattan jogs. We need to embrace the fact that all printed mask shapes will be curvilinear and ensure that any shape-based simulation is able to predict effects at all angles, not just 0 and 90.

Increasing mask requirements drive the need for mask model accuracy

As we continue to move forward to more advanced processes with ever-smaller feature sizes, the requirement for better accuracy increases. There is quite literally less room for any defects. This increased emphasis on accuracy and precision is what drives the adoption of new technologies such as EUV and multi-beam mask writing; it drives the increased need for better model performance as well.

We have already discussed several model parameters that will need to be re-evaluated and handled differently in order to achieve greater accuracy. Accuracy also requires a more rigorous approach to the calibration and validation of models with test chips that isolate specific physics effects with specific test structures. For example, masks that include complex shapes require 2D validation. Today’s VSB mask writers are Manhattan (1D) writing instruments, so models built using these tools are by definition 1D-centric. Inaccuracies in 1D models are exacerbated when tested against a 2D validation. Physics-based models are far more likely to extrapolate to 2D shapes, and are better for ILT.

As features shrink, the accuracy of individual shapes on the mask is impacted increasingly by their proximity to other shapes. The context for each shape on the mask becomes as important as the shape itself. The solution is to model each shape within the context of its surroundings. This is driving the need for simulation-based modeling and mask-correction methodologies.

GPU acceleration: Making simulation-based mask modeling practical

Historically, simulation-based processing of mask models resulted in unacceptably long simulation runtimes. The most common approach until recently has been to use model-based or rules-based methodologies that, while providing less accuracy, result in faster runtimes. The advent of GPU-accelerated mask simulation has changed this picture. GPU acceleration is particularly suited to “single instruction, multiple data” (SIMD) computing, which makes it a very good fit for simulation of physical phenomena, and enables full- reticle mask simulation within reasonable runtimes.

An additional advantage of GPU acceleration is the ability to employ PSFs without runtime impact (FIGURE 3). As we’ve already discussed, PSFs are a natural choice for the mask-exposure model, including EUV mask mid-range scattering effects, forward-scattering details, and modeling back-scattering by construction. Using PSFs, any dose effect of any type can be exactly modeled during simulation-based processing.

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GPU acceleration opens the door for simulation-based correction of a multitude of complex mask effects based on physics-based models, affording practical simulation run times for these more complex models.

PLDC: New mask models at work in multi-beam mask writers

As with any big changes to the semiconductor manufacturing process, the industry has been preparing for EUV and multi-beam mask writing for several years. These preparations have required various members of the supply chain to work together to deploy effective solutions. One example of this collaboration in the mask-modeling realm is the introduction by NuFlare Technology of pixel-level dose correction (PLDC) in its MBM-1000 multi-beam mask writer. At the 2017 SPIE Photomask Japan conference, NuFlare and D2S jointly presented a paper [2] detailing the mask modeling – and GPU acceleration – used in this new inline mask correction.

PLDC manipulates the dose of pixels to perform short- range (effects in the 10nm scale to 3-5μm scale) linearity correction while improving the overall printability of the mask. In addition to the traditional four-Gaussian (4G) PEC model, PLDC combines for the first time an inline 10nm-100nm short-range linearity correction with a 1μm scale mid-range linearity correction (FIGURE 4). This mid-range correction is particularly useful for EUV mid-range scatter correction.

Screen Shot 2018-03-01 at 1.40.49 PM

The dose-based effects portion of the D2S mask model, TrueModel, are expressed as a PSF for an interaction range up to 3-5μm, and with a 4G PEC model for interaction range up to 40-50μm. Being able to express any arbitrary PSF as the correction model allows smoothing of “shoulders” that are often present on multiple Gaussian models, and allows proper modeling of effects that are not fundamentally Gaussian in nature (such as the EUV mid-range scatter). This ability to model physical effects and correct for them inline with mask writing results in more accurate masks, including for smaller EUV shapes and for curvilinear ILT mask shapes.

PLDC is simulation-based, so it has the ability to be very accurate regardless of targeted shape, regardless of mask type (e.g., positive, negative EUV, ArF, NIL master) with the right set of mask modeling parameters.

GPU acceleration enables fast computing of PSF convo- lutions for all dose-based effects up to 3-5μm range, performed inline in the MBM-1000, which helps to maintain turnaround time in the mask shop.

Conclusions

Mask models need some significant adaptations to meet the coming challenges. The new EUV/multi-beam mask writer era will require mask models to be more detailed and more accurate. More complex dose profiles and more complex electron scattering require PSFs be added to the industry-standard Gaussian models. More rigorous mask models with specific dose and specific shape effects are now needed. Simulation-based mask processing, made practical by GPU acceleration, is necessary to take context-based mask effects into account.

The good news is that the mask industry has been preparing for these changes for several years and stands ready with solutions to the challenges posed by these new technologies. Big changes are coming to the mask world, and mask models will be ready.

References

1. Pearman, Ryan, et al, “EUV modeling in the multi-beam mask writer era,” SPIE Photomask Japan, 2017.

2. “GPU-accelerated inline linearity correction: pixel-level dose correction (PLDC) for the MBM-1000,” Zable, Matsumoto, et al, SPIE Photomask Japan, 2017.

BY SYAHIRAH MD ZULKIFLI, BERNICE ZEE AND WEN QIU, Advanced Micro Devices, Singapore; ALLEN GU, ZEISS, Pleasanton, CA

3D integration and packaging has challenged failure analysis (FA) techniques and workflows due to the high complexity of multichip architectures, the large variety of materials, and small form factors in highly miniaturized devices [1]. The drive toward die stacking with High Bandwidth Memory (HBM) allows the ability to move higher bandwidth closer to the CPU and offers an oppor- tunity to significantly expand memory capacity and maximize local DRAM storage for high throughput in the data center. However, the integration of HBM results in more complex electrical communications, due to the emerging use of a physical layer (PHY) design to connect the chip and subsystems. FIGURE 1 shows the schematic of a 2.5D stacked die package designed so that some HBM μbumps are electrically connected to the main CPU through a PHY connection. In general, the HBM and CPU signal length needs to be minimized to reduce drive strength requirements and power consumption at the PHY.

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This requirement poses new challenges in FA fault isolation. A traditional FA workflow using electrical fault isolation (EFI) techniques to isolate the defect becomes less effective for chip-to-chip interconnects because there are no BGA balls for electrically probing the μbumps at the PHY. As a result, new defect localization techniques and FA flows must be investigated.

XRM theory

X-ray imaging is widely employed for non-destructive FA inspection because it can explore interior structures of chips and packages, such as solder balls, silver paste and lead frames. Thus, many morphological failures, such as solder-ball crack/burn-out and bumping failure inside IC packages, can be imaged and analyzed through X-ray tools. In 2D X-ray inspection, an X-ray irradiates samples and a 2D detector utilizes the projection shadow to construct 2D images. This technique, however, is not adequate for revealing true 3D structures since it projects 3D structures onto a 2D plane. As a result, important information, such as internal faulty regions of electronic packages, may remain hidden. This disadvantage can be overcome by using 3D X-ray microscopic technology, derived from the original computed tomography (CT) technique. In a 3D imaging system, a series of 2D X-ray images are captured at different angles while a sample rotates.

These 2D images are used to reconstruct 3D X-ray tomographic slices using mathematic models and algorithms. The spatial resolution of the imaging technique can be improved through the integration of an optical microscopy system. This improved technology is called 3D X-ray microscopy (XRM) [2]. FIGURE 2 shows an example 3D XRM image for a stacked die. The image clearly shows the internal structures – including the TSV, C4 bumps and μbump of the electronic components – without physically damaging or altering the sample. The high resolution and quality shown here are essential to inspect small structural defects inside electronic devices. With its non-destructive nature, 3D XRM has been useful for non-destructive FA for IC packaging devices.

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Failure analysis approach

The purpose of an FA workflow is to have a sequence of analytical techniques that can help to effectively and quickly isolate the failure and determine the root cause. Typical FA workflows for flip-chip devices consist of non-destructive techniques such as C-Mode scanning acoustic microscopy (C-SAM) and time domain reflectometry (TDR) to isolate the failure, followed by destructive physical failure analysis (PFA). However, there are limitations to each of these techniques when posed with the failure analysis of a more complex stacked die package.

C-SAM allows the inspection of abnormal bumps, delamination and any mechanical failure. A focused soundwave is directed from a transducer to a small point on a target object and is reflected when it encounters a defect, inhomogeneity or a boundary inside the material. The transducer transforms the reflected sound pulses into electromagnetic pulses, which are displayed as pixels with defined grey values thereby creating an image [3]. However, stacked die composed of a combination of multiple thin layers may complicate C-SAM analysis. This is because the thin layers have smaller spacing between the adjacent interface, and shorter delay times for ultrasound traveling from one interface to another. Therefore, failures between the die and die attach may not be easily detected, and false readings may even be expected.

TDR is an electrical fault isolation tool that enables failure localization through electrical signal data. The TDR signal carries the impedance load information of electrical circuitry; hence, the reflected signals show the discontinuity location that has caused the mismatch of impedance. In-depth theory on TDR is further discussed in Chin et al [4]. However, TDR can only estimate where the failure lies, whether it is in the substrate, die or interposer region. To pin point the exact location within the area of failure is difficult, due to limitations in separating the various small structures through the TDR signal. Additionally, some of the pulse power is reflected for every impedance change, posing challenges regarding unique defect isolation and signal complexity – especially for stacked die [5]. In cases where the failure pins reside in the HBM μbump region, no BGA ball out is available to probe and send an electrical pulse through.

Physical Failure Analysis (PFA) is a destructive method to find and image the failure once non-destructive fault isolation is complete. PFA can be done both mechanically and by focused ion beam (FIB). For stacked dies, FIB is predominantly used to image smaller interconnect structures such as TSVs and μbumps. However, the drawback is that the success of documenting the failure through PFA is largely dependent on how well the non-destructive FA techniques can isolate the failure region. Without good clear fault isolation direction, the failure region might be destroyed or missed during the PFA process, and thus no root cause can be derived.

The integration of XRM into the FA flow can help to overcome the limitations of the various analysis techniques to isolate the failure. It is a great advantage to image small structures and failures with the high spatial resolution and contrast provided by XRM and without destroying the sample. For failures in stacked die, XRM can be integrated into the FA flow for further fault isolation with high accuracy. The visualization of defects and failed material prior to destructive analysis increases FA success rates. However, the trade-off for imaging small defects at high resolution is time. For stacked die failures, C-SAM and TDR can first be performed to isolate the region of failure. With a known smaller region of interest to focus on, the time taken for XRM to visualize the area at high resolution is significantly reduced.

In cases where failures are identified in the HBM μbump, XRM is an effective technique to isolate the failure through 3D defect visualization. With the failure region isolated, XRM can then act as a guide to perform further PFA. Following are three case studies where XRM was used to image HBM packages with stacked dies.

Case studies

In the first case study, we explore the application of XRM as the primary means of defect visualization where other non-destructive testing and FA techniques are not possible. An open failure was reported for non-underfilled stacked die packages during a chip package interaction (CPI) study. The suspected open location was within the μbump joints at the HBM stack/ interposer interface. The initial approach exposed the bottom-most die of the HBM stack, followed by FIB cross-sectioning at the specified location. Performing the destructive approach to visualize the integrity of μbump joints in non-underfilled stack die packages was virtually impossible due to the fragility of silicon. The absence of underfill (UF) means that the HBM does not properly adhere to the interposer and is susceptible to peel off. In addition, there was no medium to release shear stresses experienced by the μbump joints upon bending stresses, which could not be absorbed by the package. As seen in FIGURE 3, parallel lapping of the HBM stack without UF caused die crack and peeling.

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Consequently, to avoid aggravating the damage on the sample, 3D XRM was performed to inspect and visualize the suspected location using a 0.7μm/voxel and 4X objective without any sample preparation. FIGURE 4 shows an example virtual slice where the micro-cracks throughout the row of μbump joints are visualized. The micro-cracks are measured a few microns wide. It is worth noting that the micro-cracks were visible with a short scan time of 1.5 hrs.

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With the critical defect information in 3D, PFA was performed on a sample that was underfilled to facilitate ease of sample preparation. SEM images in FIGURE 5 validated the existence of μbump micro-cracks observed by 3D XRM inspection.

In the second case study, the 3D XRM technique was applied to a stacked die package with a failure at a specific HBM/XPU physical interface (PHY) μbump connection. This μbump connection provides specific communication between the HBM stack and XPU die, and there is no package BGA ball out to enable electrical probing. Accordingly, it was not possible to verify if the failure type was an open or short. In addition, there was no means to determine if the failure was at the HBM or XPU die. Since defects from previous lots were open failures at the PHY μbump of the HBM, 3D XRM was performed at the suspected HBM open region using a 0.85μm/voxel and 4X objective.

As no defect was observed, XRM was then applied to the corresponding XPU PHY μbump. Contrary to the anticipated μbump open, a short was observed between two μbumps as shown in FIGURES 6a and 6b.

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The μbump short resulted from a solder extrusion bridging two adjacent μbumps. If 3D XRM had not been performed, a blind physical cross-section likely would have been performed on the initially suspected open region. As a result, the actual failure region may have been missed and/or destroyed.

In the final case study, an open failure was reported at a signal pin of a stack die package. As per the traditional FA flow, C-SAM and TDR techniques were applied to isolate the fault. C-SAM results showed an anomaly, and TDR suggested an open in the substrate as demonstrated in FIGURE 7a and 7b respectively.

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To verify the observations made by C-SAM and TDR non-destructive techniques, 3D XRM was performed using a 0.80μm/voxel and 4X objective at the region of

FIGURE 8 revealed a crack between the failure C4 bump and associated TSV. A physical cross-section was performed and the passivation cracks between the TSV and interposer backside redistribution layer (RDL) was observed as shown in FIGURE 9.

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In this case, 3D XRM provided 3D information for the FA engineer to focus on. Without the visual knowledge on the defect’s nature and location, the defect would have been missed during PFA.

Summary and conclusions

3D integration and packaging have brought about new challenges for effective defect localization, especially when traditional electrical fault isolation is not possible. 3D XRM enables 3D tomographic imaging of internal structures in chips, interconnects and packages, providing 3D structural information of failure areas without the need to destroy the sample. 3D XRM is a vital and powerful tool that helps failure analysis engineers to overcome FA challenges for novel 3D stacked-die packages.

Acknowledgement

This article is based on a paper that was presented at the 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2017).

References

  1. F. Altmann and M. Petzold, “Innovative Failure Analysis Techniques for 3-D Packaging Developments,” IEEE Design & Test, Vol. 33, No. 3, pp. 46-55, June 2016.
  2. C. Y. Liu, P. S. Kuo, C. H. Chu, A. Gu and J. Yoon, “High resolution 3D X-ray microscopy for streamlined failure analysis workflow,” 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 2016, pp. 216-219.
  3. M. Yazdan Mehr et al., “An overview of scanning acoustic microscope, a reliable method for non-destructive failure analysis of microelectronic components,” 2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro- electronics and Microsystems, Budapest, 2015, pp.1-4.
  4. J. M. Chin et al., “Fault isolation in semiconductor product, process, physical and package failure analysis: Importance and overview,” Microelectronics Reliability, Vol. 51, Issue 9, pp. 1440-8, Nov. 2011.
  5. W. Yuan et al., “Packaging Failure Isolation with Time-Domain Reflectometry (TDR) for Advanced BGA Packages,” 2007 8th International Conference on Electronic Packaging Technology, Shanghai, 2007, pp. 1-5.

Samsung Electronics today announced that it broke ground on a new EUV (extreme ultraviolet) line in Hwaseong, Korea.

With this new EUV line, Samsung will be able to strengthen its leadership in single nanometer process technology by responding to market demand from various applications, including mobile, server, network, and HPC (high performance computing), for which high performance and power efficiency are critical.

The new facility is expected to be completed within the second half of 2019 and start production ramp-up in 2020. The initial investment in the new EUV line is projected to reach USD 6 billion by 2020 and additional investment will be determined depending on market circumstances.

“With the addition of the new EUV line, Hwaseong will become the center of the company’s semiconductor cluster spanning Giheung, Hwaseong and Pyeongtaek in Korea,” said Kinam Kim, President & CEO of Device Solutions at Samsung Electronics. “The line will play a pivotal role as Samsung seeks to maintain a competitive edge as an industry leader in the coming age of the Fourth Industrial Revolution.”

Samsung has decided to utilize cutting-edge EUV technology starting with its 7-nanometer (nm) LPP (Low Power Plus) process. This new line will be set up with EUV lithography equipment to overcome nano-level technology limitations. Samsung has continued to invest in EUV R&D to support its global customers for developing next-generation chips based on this leading-edge technology.

Samsung Electronics Hwaseong Campus EUV line bird’s eye view

Samsung Electronics Hwaseong Campus EUV line bird’s eye view

The top five semiconductor metrology/inspection equipment vendors grew 17.7% in 2017 according to the report “Metrology, Inspection, and Process Control in VLSI Manufacturing”, recently published by The Information Network, (www.theinformationnet.com) a New Tripoli, PA-based market research company.

The top three metrology/inspection suppliers were KLA-Tencor, Applied Materials Hitachi High Tech, Nanometrics, and Rudolph Technologies. These five companiesincreased their collective share of the overall global market to 87.0% in 2017, up from 82.4% in 2016.

metrology market

The report covers 27 different sectors and subsectors. With its large market share, KLA-Tencor led most of the sectors and subsectors. Applied Materials led the Defect Review Sector, Hitachi High Tech led the CD Inspection sector, Nanometrics held a large share of the Thin Film Metrology Sector, and Rudolph Technology led the Back-End Inspection market.

China and memory (DRAM and 3D NAND) are currently driving demand for the global wafer fab equipment market.

Orders for KLA-Tencor equipment from native Chinese customers nearly tripled in 2017 and this strong momentum is expected to continue into 2018.

China continues to be a strong focus for Rudolph Technologies. Revenue from China has more than doubled in the last two years. Rudolph’s revenue from advanced memory applications in both three DRAM and 3D NAND grew by 80% year-over-year as customers in Korea increased capacity to meet growing global demand for advanced memory used in cloud computing and mobile applications.

Entering 2018 on solid ground


February 22, 2018

By Walt Custer, Custer Consulting Group

2017 finished on an upturn – both in the USA and globally.  Based on consolidated fourth-quarter actual and estimated revenues of 213 large, global electronic manufactures, sales rose in excess of 7 percent in 4Q’17 vs. 4Q’16 (Chart 1).  This was the highest global electronic equipment sales growth rate since the third quarter of 2011. Because some companies in our sample didn’t close their financial quarter until the end of January, final results will take a few more weeks – but all evidence points to a very strong fourth quarter of last year.

Custer1-Electronic-Equipment

 

Using regional (country specific) data (Chart 2), the normal, consumer electronics driven seasonal downturn began again in January.  However the recent year-over-year growth is still substantial.  On a total electronic equipment revenue basis, January 2018 was up almost 19.5 percent over January 2017.

Custer2-World-Electronic

Because this regional data in local currencies was converted to U.S. dollars at fluctuating exchange, the dollar denominated-growth was amplified by currency exchange effects.  At constant exchange the January growth was only 14 percent.   That is, when the stronger non-U.S. currencies were converted to weakening dollars, the dollar-denominated January 2018 fluctuating exchange growth was amplified by 5.5 percent.

Chart 3 shows 4Q’17/4Q’16 growth of the domestic electronic supply chain.  U.S. electronic equipment shipments were up 9.1 percent.  Only computer equipment and non-defense aircraft sales declined in the fourth quarter.  And of note, SEMI equipment shipments to North America rose almost 31 percent!

Custer3-US-Electronic-Supply

 

Chart 4 shows estimated fourth-quarter growth for the world electronic supply chain.  Only “Business & Office” equipment revenues declined in 4Q’17 vs. 4Q’16.

Custer4-Global-Electronic

Total global electronic equipment sales increased more than 7 percent in the fourth quarter and SEMI equipment revenues rose 32 percent.

2017 was a strong year and 2018 is off to a good start!  The 2017 lofty growth rates will temper, but this current expansion will likely continue.  Watch the monthly numbers!

Originally published on the SEMI blog.

The success and proliferation of integrated circuits has largely hinged on the ability of IC manufacturers to continue offering more performance and functionality for the money.  Driving down the cost of ICs (on a per-function or per-performance basis) is inescapably tied to a growing arsenal of technologies and wafer-fab manufacturing disciplines as mainstream CMOS processes reach their theoretical, practical, and economic limits. Among the many levers being pulled by IC designers and manufacturers are: feature-size reductions, introduction of new materials and transistor structures, migration to larger-diameter silicon wafers, higher throughput in fab equipment, increased factory automation, three-dimensional integration of circuitry and chips, and advanced IC packaging and holistic system-driven design approaches.

For logic-oriented processes, companies are fabricating leading-edge devices such as high-performance microprocessors, low-power application processors, and other advanced logic devices using the 14nm and 10nm generations (Figure 1).  There is more variety than ever among the processes companies offer, making it challenging to compare them in a fair and useful way.  Moreover, “plus” or derivative versions of each process generation and half steps between major nodes have become regular occurrences.

For five decades, the industry has enjoyed exponential improvements in the productivity and performance of integrated circuit technology.  While the industry has continued to surmount obstacles put in front of it, the barriers are getting bigger.  Feature size reduction, wafer diameter increases, and yield improvement all have physical or statistical limits, or more commonly…economic limits.  Therefore, IC companies continue to wring every bit of productivity out of existing processes before looking to major technological advances to solve problems.

The growing design and manufacturing challenges and costs have divided the integrated circuit world into the haves and have-nots.  In the June 1999 Update to The McClean Report, IC Insights first described its “Inverted Pyramid” theory, where it was stated that the IC industry was in the early stages of a new era characterized by dramatic restructuring and change.  It was stated that the marketshare makeup in various IC product segments was becoming “top heavy,” with the shares held by top producers leaving very little room for remaining competitors. Although the Update described the emerging inverted pyramid phenomenon from a marketshare perspective, an analogous trend can be seen regarding IC process development and fabrication capabilities. The industry has evolved to the point where only a very small group of companies can develop leading-edge process technologies and fabricate leading-edge ICs.

Figure 1

Figure 1

The ten largest semiconductor R&D spenders increased their collective expenditures to $35.9 billion in 2017, an increase of 6% compared to $34.0 billion in 2016. Intel continued to far exceed all other semiconductor companies with R&D spending that reached $13.1 billion.  In addition to representing 21.2% of its semiconductor sales last year, Intel’s R&D spending accounted for 36% of the top 10 R&D spending and about 22% of total worldwide semiconductor R&D expenditures of $58.9 billion in 2017, according to the 2018 edition of The McClean Report that was released in January 2018.  Figure 1 shows IC Insights’ ranking of the top semiconductor R&D spenders, including both semiconductor manufacturers and fabless suppliers.

Figure 1

Figure 1

Intel’s R&D expenditures increased just 3% in 2017, below its 8% average annual growth rate since 2001, according to the new report.  Still, Intel’s R&D spending exceeded the combined R&D spending of the next four companies—Qualcomm, Broadcom, Samsung, and Toshiba—listed in the ranking.

Underscoring the growing cost of developing new IC technologies, Intel’s R&D-to-sales ratio has climbed significantly over the past 20 years.  In 2017, Intel’s R&D spending as a percent of sales was 21.2%, down from an all-time high of 24.0% in 2015.  In 2010, the ratio was 16.4%, 14.5% in 2005, 16.0% in 2000, and just 9.3% in 1995.

Qualcomm—the industry’s largest fabless IC supplier—was again ranked as second-largest R&D spender, a position it first achieved in 2012.  Qualcomm’s semiconductor-related R&D spending was down 4% in 2017, after a 7% drop in 2016, and it was close to being passed up by third place Broadcom and fourth placed Samsung, whose R&D spending increased 4% and 19%, respectively.

Despite increasing its R&D expenditures by 19% in 2017, Samsung had the lowest investment-intensity level among the top-10 R&D spenders with research and development funding at 5.2% of sales last year.  Samsung’s 49% increase in semiconductor revenue in 2017 (driven by strong growth in DRAM and NAND flash memory) lowered its R&D as a percent of sales ratio from 6.5% in 2016.  Micron Technology’s revenues surged 77% in 2017, but its research and development expenditures grew 8%, resulting in an R&D/sales ratio of 7.5% compared to 12.5% in 2016.  Similarly, SK Hynix’s sales climbed 79% in 2017, while its research and development spending increased 14% in the year, which resulted in an R&D/sakes ratio of 6.5% versus 10.2% in 2016.

Fifth-ranked Toshiba and sixth-ranked Taiwan Semiconductor Manufacturing Co. (TSMC) each allocated about the same amount for R&D spending in 2017.  Toshiba’s R&D spending was down 7% while TSMC had one of the largest increases in R&D spending among the top 10 companies shown in the figure. TSMC’s R&D expenditures grew by 20% as the foundry raced rivals Samsung and GlobalFoundries in launching new process technologies, while its sales rose 9% to $32.2 billion in the year.

Rounding out the top-10 list were MediaTek, Micron, Nvidia, which moved from 11th place in 2016 to 9th position to displace NXP in the 2017 ranking, and SK Hynix.  Collectively, the top-10 R&D spenders increased their outlays by 6% in 2017, two points more than the 4% R&D increase for the entire semiconductor industry.  Combined R&D spending by the top 10 exceeded total spending by the rest of the semiconductor companies ($35.9 billion versus $23.0 billion) in 2017.

A total of 18 semiconductor suppliers allocated more than more than $1.0 billion for R&D spending 2017.  The other eight manufacturers were NXP, TI ST, AMD, Renesas, Sony, Analog Devices, and GlobalFoundries.

The latest market research report by Technavio on the global semiconductor IP market predicts a CAGR of close to 10% during the period 2018-2022.

The report segments the global semiconductor IP market by application (healthcare, networking, industrial automation, automotive, consumer electronics, and mobile computing devices), by end-user (fabless semiconductor companies, IDMs, and foundries), and by geography (North America, APAC, and Europe). It provides a detailed illustration of the major factors influencing the market, including drivers, opportunities, trends, and industry-specific challenges.

Here are some key findings of the global semiconductor IP market, according to Technavio hardware and semiconductor researchers:

  • Complex chip designs and use of multi-core technologies: a major market driver
  • Proliferation of wireless technologies: emerging market trend
  • North America dominated the global semiconductor IP market with 47% share in 2016

Complex chip designs and use of multi-core technologies: a major market driver

Nowadays, the electronic device manufacturers develop products that have better functionalities while offering power-packed performances as compared to their earlier products. This is driving the semiconductor chip manufacturers to ensure that their IC designs are capable of and reliable for offer maximum use in terms of performance, which is propelling the product development process in the semiconductor industry.

Players in the market are competing against each other based on timely delivery of offerings while ensuring high performing and multi-functional devices. Semiconductor manufacturers are incorporating new and complex architecture and designs of semiconductor ICs to deliver high-end multi-functional products. For example, 3D ICs are compact, consume less power, and are more efficient in performance. They have a complex electronic circuit design and manufacturing process. Such complexity tends to hamper the overall productivity of the industry.

 

Proliferation of wireless technologies: emerging market trend

In the last 25 years, IoT has evolved a great deal. Internet Protocol version 6 (IPv6) that was in the development phase since 1990 is replacing Internet Protocol version 4 (IPv4). This allows many hosts to connect to the Internet and increases the data traffic that can be transmitted.

The popularity of mobile computing devices has helped the network traffic to grow at an exponential rate. This led to the continued deployment of next-generation wireless standards such as 4G and 5G, and wireless technologies such as Bluetooth low energy (BLE), Wi-Fi, ZigBee, and Z-Wave across the globe. Such wireless standards and wireless technologies offer a wireless connection that is equivalent to broadband connections that have resulted in an increase in the number of users accessing the Internet from anywhere and at any time.

According to a senior analyst at Technavio for research on semiconductor equipment, “At present, ZigBee is one of the three leading wireless technology used for connected devices such as connected bulbs, remote controls, smart meters, smart thermostats, and set-top boxes. High-bandwidth and content-rich applications such as audio, video, gaming, and Internet use the Wi-Fi technology. BLE is used for low power applications and is primarily used to connect wearables to smartphones. ZigBee is a low power version of Wi-Fi which is appropriate for smart home applications such as lighting, remote controls, security, and thermostats.”

Global market opportunities

In terms of regional dominance, North America led the global semiconductor IP market, followed by APAC and Europe in 2017. However, APAC is expected to grow at a faster rate due to increased prevalence of orthopedic surgical procedures. The emerging economies like China and Taiwan contributed to the growth of this market in APAC.

The market share of North America is expected to decrease during the forecast period due to factors such as strong governmental policies against exports from the governments of South Korea, Japan, China, and India, who want to become completely self-sufficient in the semiconductor industry.

 

By Cherry Sun, SEMI China

Yawning differences between cultures, economic systems and rules of law stand as barriers for many China- and US-based technology companies to do business on each other’s soil, making it imperative for both countries to work together to bridge the gaps that make it harder for tech businesses in each country to find partners and open markets in the other, SEMI China president Lung Chu said at a recent conference.

One answer is for SEMI, serving as a natural unifying communications platform, to help foster greater cooperation between US and China tech companies, Lung Chu said, speaking at the 2nd Silicon Valley Beijing International IoT Summit & Investment and Financing Competition in Santa Clara last month. The event gathered industry experts and experts to mine opportunities across technologies including smart and mobile medical care, virtual and augmented reality, wearables, smart homes, artificial intelligence (AI), robotics, 3D printing, Internet of Things (IoT) and manufacturing design.

In the IoT roundtable chaired by Chu, he asked mayors and other city officials from Sunnyvale, Palo Alto and Cupertino to consider the potential of IoT technology for improving city management. Inspired by the idea of greater efficiency, the mayors pointed to IoT applications including traffic management to better regulate traffic flow; faster, more effective medical treatment from first responders and emergency medical technicians; more efficient energy usage by cities and the public; better water resources management; and bicycle sharing programs for commuters.

Deploying more advanced networking architectures, the mayors agreed, is the first step for cities seeking to fulfill the promise of IoT. A recognized global leader in smart city technologies, China is much more than a key trade partner with the U.S., having developed IoT use cases for cities in Silicon Valley and beyond to consider.

Chu also asked the mayors about the importance to their cities of attracting talent and encouraging entrepreneurship. The roundtable agreed that in Silicon Valley, taking risks in hopes of reaping huge profits is prized and that failure is embraced as necessary to innovation. In China, pressure on business startups to flourish can inhibit the free-wheeling thinking and calculated risk-taking often needed to build new enterprises.

On talent, one mayor underscored the importance of diversity in building a skilled workforce. According to a recent report based on 2016 census data, nearly three-quarters – about 71 percent of tech employees in Silicon Valley – “are foreign born, compared to around 50 percent in the San Francisco-Oakland-Hayward region,” The Mercury News reported. Carl Guardino, CEO of the Silicon Valley Leadership Group, has noted that this “diversity is the strength of Silicon Valley.”

Much as China can turn to Silicon Valley as a model of entrepreneurship and diversity, the U.S. can learn from China’s deployment of IoT technologies to power smart cities as the country’s prominence in the semiconductor manufacturing industry continues to grow. An ally in that rising influence, SEMI China follows the 5C principles – Connect, Collaboration, Community, Communication, China – to help narrow the differences between China and other countries and foster stronger partnerships.

Originally published on the SEMI blog.