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IC Insights has revised its outlook for semiconductor industry capital spending and will present its new findings in the November Update to The McClean Report 2017, which will be released at the end of this month.  IC Insights’ latest forecast now shows semiconductor industry capital spending climbing 35% this year to $90.8 billion.

After spending $11.3 billion in semiconductor capex last year, Samsung announced that its 2017 outlays for the semiconductor group are expected to more than double to $26 billion.  Bill McClean, president of IC Insights stated, “In my 37 years of tracking the semiconductor industry, I have never seen such an aggressive ramp of semiconductor capital expenditures.  The sheer magnitude of Samsung’s spending this year is unprecedented in the history of the semiconductor industry!”

Figure 1 shows Samsung’s capital spending outlays for its semiconductor group since 2010, the first year the company spent more than $10 billion in capex for the semiconductor segment.  After spending $11.3 billion in 2016, the jump in capex expected for this year is simply amazing.

To illustrate how forceful its spending plans are, IC Insights anticipates that Samsung’s semiconductor capex of $8.6 billion in 4Q17 will represent 33% of the $26.2 billion in total semiconductor industry capital spending for this quarter.  Meanwhile, the company is expected to account for about 16% of worldwide semiconductor sales in 4Q17.

IC Insights estimates that Samsung’s $26 billion in semiconductor outlays this year will be segmented as follows:

3D NAND flash: $14 billion (including an enormous ramp in capacity at its Pyeongtaek fab)

DRAM: $7 billion (for process migration and additional capacity to make up for capacity loss due to migration)

Foundry/Other: $5 billion (for ramping up 10nm process capacity)

annual samsung capex

IC Insights believes that Samsung’s massive spending outlays this year will have repercussions far into the future. One of the effects likely to occur is a period of overcapacity in the 3D NAND flash market. This overcapacity situation will not only be due to Samsung’s huge spending for 3D NAND flash, but also to its competitors in this market segment (e.g., SK Hynix, Micron, Toshiba, Intel, etc.) responding to the company’s spending surge.  At some point, Samsung’s competitors will need to ramp up their capacity or loose market share.

Samsung’s current spending spree is also expected to just about kill any hopes that Chinese companies may have of becoming significant players in the 3D NAND flash or DRAM markets.  As our clients have been aware of for some time, IC Insights has been extremely skeptical about the ability of new Chinese startups to compete with Samsung, SK Hynix, and Micron with regards to 3D NAND and DRAM technology.  This year’s level of spending by Samsung just about guarantees that without some type of joint venture with a large existing memory suppler, new Chinese memory startups stand little chance of competing on the same level as today’s leading suppliers.

Gigaphoton Inc., a manufacturer of light sources used in semiconductor lithography, announced its intention to draw up a new roadmap with the aim of improving the availability of the equipment, and also to respond to the needs of the semiconductor chip manufacturers who are being confronted with increasingly high demands.

Gigaphoton recently drew up a roadmap titled “RAM Enhancement” to enhance the Reliability, Availability, and Maintainability of the Excimer laser, a DUV light source. The company has already started off on overcoming the “99.8%-availability” barrier by 2020, which is the threshold limit value in the industry.

The availability of lithography tools is a key parameter which has a major impact on manufacturing IC chips. In line with this, maximizing the availability requires “long-term stable operation” and “minimized maintenance time.” To achieve both of the above, Gigaphoton is now striving to extend module lifetime and improve on-site unit serviceability that the company’s field engineers provide to customers, aiming at maintenance with the minimum number of machine stops.

To achieve “long-term stable operation,” the company is now increasing each lifetime of major modules such as the chamber (AMP CH), the line narrow module (LNM), and the monitor module (MM) up to 120 Bpls. As for “minimized maintenance time,” new software which automatically calculates expected unit lifetime and the right time for maintenance is ready to be introduced.

With these efforts, the company are now in the course of reducing the required number of maintenance down to only once per year as well as the mean time between module replacement down to half the conventional hours, and also overcoming the barrier of 99.8%-availability on every customer site by 2020. (This is on the assumption that memory chip makers use 60Bpls/year.)

Katsumi Uranaka, President & CEO of Gigaphoton commented, “Along with the increasing demand for semiconductor chips in recent years, the availability of semiconductor manufacturing equipment is becoming increasingly important. The ‘RAM Enhancement’ roadmap which we are promoting was formulated in order to meet these customer needs. From now on as well, Gigaphoton will continue to provide the optimum solutions, while taking into consideration the demands of our customers and also the market trends. ”

A transfer technique based on thin sacrificial layers of boron nitride could allow high-performance gallium nitride gas sensors to be grown on sapphire substrates and then transferred to metallic or flexible polymer support materials. The technique could facilitate the production of low-cost wearable, mobile and disposable sensing devices for a wide range of environmental applications.

Transferring the gallium nitride sensors to metallic foils and flexible polymers doubles their sensitivity to nitrogen dioxide gas, and boosts response time by a factor of six. The simple production steps, based on metal organic vapor phase epitaxy (MOVPE), could also lower the cost of producing the sensors and other optoelectronic devices.

Sensors produced with the new process can detect ammonia at parts-per-billion levels and differentiate between nitrogen-containing gases. The gas sensor fabrication technique was reported November 9 in the journal Scientific Reports.

Abdallah Ougazzaden, director of Georgia Tech Lorraine in Metz, France and Chris Bishop, a researcher at Institut Lafayette, example a sample being processed in a lab at Georgia Tech Lorraine. (Credit: Rob Felt, Georgia Tech).

Abdallah Ougazzaden, director of Georgia Tech Lorraine in Metz, France and Chris Bishop, a researcher at Institut Lafayette, example a sample being processed in a lab at Georgia Tech Lorraine. (Credit: Rob Felt, Georgia Tech).

“Mechanically, we just peel the devices off the substrate, like peeling the layers of an onion,” explained Abdallah Ougazzaden, director of Georgia Tech Lorraine in Metz, France and a professor in Georgia Tech’s School of Electrical and Computer Engineering (ECE). “We can put the layer on another support that could be flexible, metallic or plastic. This technique really opens up a lot of opportunity for new functionality, new devices – and commercializing them.”

The researchers begin the process by growing monolayers of boron nitride on two-inch sapphire wafers using an MOVPE process at approximately 1,300 degrees Celsius. The boron nitride surface coating is only a few nanometers thick, and produces crystalline structures that have strong planar surface connections, but weak vertical connections.

Image shows wafer-scale processed AlGaN/GaN sensors being tested. (Credit: Georgia Tech Lorraine).

Image shows wafer-scale processed AlGaN/GaN sensors being tested. (Credit: Georgia Tech Lorraine).

Aluminum gallium nitride (AlGaN/GaN) devices are then grown atop the monolayers at a temperature of about 1,100 degrees Celsius, also using an MOVPE process. Because of the boron nitride crystalline properties, the devices are attached to the substrate only by weak Van der Waals forces, which can be overcome mechanically. The devices can be transferred to other substrates without inducing cracks or other defects. The sapphire wafers can be reused for additional device growth.

“This approach for engineering GaN-based sensors is a key step in the pathway towards economically viable, flexible sensors with improved performances that could be integrated into wearable applications,” the authors wrote in their paper.

So far, the researchers have transferred the sensors to copper foil, aluminum foil and polymeric materials. In operation, the devices can differentiate between nitrogen oxide, nitrogen dioxide, and ammonia. Because the devices are approximately 100 by 100 microns, sensors for multiple gases can be produced on a single integrated device.

“Not only can we differentiate between these gases, but because the sensor is very small, we can detect them all at the same time with an array of sensors,” said Ougazzaden, who expects that the devices could be modified to also detect ozone, carbon dioxide and other gases.

The gallium nitride sensors could have a wide range of applications from industry to vehicle engines – and for wearable sensing devices. The devices are attractive because of their advantageous materials properties, which include high thermal and chemical stability.

“The devices are small and flexible, which will allow us to put them onto many different types of support,” said Ougazzaden, who also directs the International Joint Research Lab at Georgia Tech CNRS.

To assess the effects of transferring the devices to a different substrate, the researchers measured device performance on the original sapphire wafer and compared that to performance on the new metallic and polymer substrates. They were surprised to see a doubling of the sensor sensitivity and a six-fold increase in response time, changes beyond what could be expected by a simple thermal change in the devices.

“Not only can we have flexibility in the substrate, but we can also improve the performance of the devices just by moving them to a different support with appropriate properties,” he said. “Properties of the substrate alone makes the different in the performance.”

In future work, the researchers hope to boost the quality of the devices and demonstrate other sensing applications. “One of the challenges ahead is to improve the quality of the materials so we can extend this to other applications that are very sensitive to the substrates, such as high-performance electronics.”

The Georgia Tech researchers have previously used a similar technique to produce light-emitting diodes and ultraviolet detectors that were transferred to different substrates, and they believe the process could also be used to produce high-power electronics. For those applications, transferring the devices from sapphire to substrates with better thermal conductivity could provide a significant advantage in device operation.

Ougazzaden and his research team have been working on boron-based semiconductors since 2005. Their work has attracted visits from several industrial companies interested in exploring the technology, he said.

“I am very excited and lucky to work on such hot topic and top-notch technology at GT-Lorraine,” said Taha Ayari, a Ph.D. student in the Georgia Tech School of ECE and the paper’s first author.

In addition to Ougazzaden, the research team includes Georgia Tech Ph.D. students Taha Ayari, Matthew Jordan, Xin Li and Saiful Alam; Chris Bishop and Youssef ElGmili, researchers at Institut Lafayette; Suresh Sundaram, a researcher at Georgia Tech Lorraine; Gilles Patriarche, a researcher at the Centre de Nanosciences et de Nanotechnologies (C2N) at CNRS; Paul Voss, an associate professor in the Georgia Tech School of ECE; and Jean Paul Salvestrini, a professor at Georgia Tech Lorraine and adjunct professor in the Georgia Tech School of ECE.

The research was supported by ANR (Agence Nationale de Recherche), the National Agency of Research in France through the “GANEX” Project.

CITATION: Taha Ayari, et al., “Gas sensors boosted by two-dimensional h-BN enabled transfer on thin substrate foils: towards wearable and portable applications,” (Scientific Reports, 2017). http://dx.doi.org/10.1038/s41598-017-15065-6

By Ajit Manocha, president and CEO, SEMI

Artificial intelligence (AI) may be a hot topic today, but SEMI has helped to incubate Big Data and AI since its founding. Early in SEMI’s history, SEMI’s always intelligent members worked together to introduce International Standards that enabled different pieces of equipment to collect and later pass data.  At first, it was for basic interoperability and equipment state analysis.  Later, SEMI data protocol Standards allowed process and metrology data to be used locally and across the fab to approach the goals of Smart Manufacturing and AI – for the equipment itself to make adjustments based on incoming wafer data.

Ajit--photo 1--sample.e.XL3A5483 (from pdg)As a part of this evolution, SEMI members developed the latest sensors and computational hardware that could ever better sense, analyze and act on the environment. Often first to use its own newly developed hardware, progress in this area was critical toward improving the likelihood of success for one of the world’s most complicated production processes – and coping with the breakneck speed of Moore’s Law – by accelerating capabilities that would later be regarded as the basis for machine learning and “thinking” systems.

Since then, process steps have increased from about 175 to as many as 1,000 for the leading technology nodes. By the time 300mm wafers were introduced, manufacturing intelligence and automation sharply increased productivity while reducing fab labor by more than 25 percent. Employing adaptive models, modern leading-edge factories are fully automated and operate at nearly 60 percent autonomous control.

Today, AI is akin to where IoT was yesterday in the hype cycle – popping up everywhere as a major consideration for the future. Neither IoT nor AI is hype, though – they’re the future.  There is ever more at stake for SEMI members with AI.  AI appears to be the next wave helping to maintain double-digit growth for the foreseeable future.

As part of its appeal for the global supply chain, AI can be a key silicon driver for three inflections that should benefit society. First, there is a massive increase in the amount of compute needed. Half of all the compute architectures shipping in 2021 will be supporting and processing AI.

Second, the Cloud will flourish and the Edge will bloom. By 2021, 50 percent of enterprise infrastructure will employ cognitive and artificial intelligence.

Third, new species of chips will emerge, such as the devices fueling IC content and electronics for the rapid growth of disruptive capabilities in vehicles and autonomous cars (as well as medical and agricultural applications, for example). There are also many more advantages created with and for AI as SEMI members enable new materials and advanced packaging.

What results can be measured from these changes for the global electronics manufacturing supply chain? More apps, more electronics, more silicon and more manufacturing.

On the other hand, the technologies alone create relatively little business value if the problems in our factories and markets are not well understood. There’s a great need to anticipate and guide AI. This requires a new kind of collaboration.

To address this need, SEMI’s vertical application platforms have been created for Smart Data (which is all about AI), and also for Smart MedTech, Smart Transportation, Smart Manufacturing and IoT. This higher degree of facilitated collaboration serves to cultivate multiple “smart communities” that accelerate progress for AI, better directing how connected networks and data mining can step up the pace for advancement of global prosperity. This process also provides members with access to untapped business opportunities and new players.​​

Ajit--photo 2 (panel)_D512959

We at SEMI are learning right along with our members. If you attended SEMICON West in July, several lessons about AI were presented by the Executive Panel (“Meeting the Challenges of the 4th Industrial Revolutions along the Microelectronics Supply Chain”) with Mary Puma (Axcelis), Shaheen Dayal (Intel), Lori Ciano (Brooks Automation) and Regenia Sanders (Ernst & Young). This very timely and excellent panel discussed how and where predictive analytics can have the biggest impact and the implications of sharing (and not sharing) data for problem solving and process optimization.

Ensuring that the SEMI staff gleans everything possible from the experts, we hosted an “encore” of the Executive Panel in October in our headquarters for an even more in-depth discussion about how to enhance collaboration across the supply chain in support of AI.

Going forward, these SEMI vertical platform communities will help to simplify and accelerate supply chain engagement for member value. Collaboration will play an ever greater role for using AI to master the making of advanced node semiconductor devices and enabling limitless cognitive computing. As a result, AI as we know it today, has a big head start over the previous pace of evolution for one of our great trendsetters, Moore’s Law.

Join the conversation.  Find out how you can work with SEMI to advance the AI – and especially AI in semiconductor manufacturing.  Frank Shemansky Jr., Ph.D., is heading up SEMI’s formation of SEMI’s Smart Data vertical application platform.  Let Frank know ([email protected]) you’re interested and he’ll give you more information on what’s to come.  As always, please let me know your thoughts.

 

The RC delay issues started a few nodes ago, and the problems are becoming worse.

BY ZSOLT TOKEI, imec, Leuven, Belgium

With the 7nm technology node in the development phase and the 5nm node moving into development, transistor scaling gets ever more complex. On top of that, the performance benefits gained at the front-end-of-line (i.e., the transistors) can easily be undone if the back-end-of-line can’t come along. BEOL processing involves the creation of stacked layers of Cu wires that electrically interconnect the transistors in the chip. Today, high-end logic chips easily have 12 to 15 levels of Cu wires. With each technology node, this Cu wiring scheme becomes more complex, mainly because there are more transistors to connect with an ever tighter pitch. Shrinking dimensions also means the wires have a reduced cross-sectional area, which drives up the resistance-capacitance product (RC) of the interconnect system. And this results in strongly increasing signal delay. The RC delay issues started a few nodes ago, and the problems are becoming worse. For example, a delay of more than 30% is expected when moving from the 10nm to the 7nm node.

The current BEOL flow

Cu-based dual damascene has been the workhorse process flow for interconnects since its introduction in the mid 1990s. A simple dual damascene flow starts with the deposition of a low-k dielectric material on a structure. These low-k films are designed to reduce the capacitance and the delay in the ICs. In a next step, this dielectric layer is covered with an oxide and a resist, and vias and trenches are formed using lithography and etch steps. These vias connect one metal layer with the layer above or below. Then, a metallic barrier layer is added to prevent Cu atoms from migrating into the low-k materials (FIGURE 1). The barrier layers are deposited with physical vapor deposition, using materials such as tantalum and tantalum nitride, and subsequently coated by a Cu seed barrier. In a final step, this structure is electroplated by Cu in a chemical mechanical polishing (CMP) step.

Screen Shot 2017-11-07 at 11.49.49 AM

A 5nm technology full dual damascene module

The semiconductor industry is hugely in favor of extending the current dual damascene technology as long as possible before moving to a new process. And this starts with incremental changes to the current technology, which should suffice for further scaling to at least the 5nm technology node. Researchers at imec have demonstrated a full dual damascene module for the 5nm technology node. At this node, the BEOL process becomes extremely complex, and interconnects are designed at very tight pitches. For example, a 50% area scaling in logic and 60% scaling of an SRAM cell from 7nm to 5nm results in a gate pitch at around 42nm and an intermediate first routing metal at 32nm pitch (or 16nm half pitch, which is half the distance between identical features). In these BEOL layers, trenches are created which are then filled with metal in a final metallization step. In order to create electrically functional lines, perpendicular block layers to the trenches are added, where metal traces are not formed. One of the many challenges to scaling the interconnects relates to the patterning options. Patterning these tight pitch layers is no longer possible by using single immersion lithography and direct etch steps. Only multi-patterning – which is known to be very costly and complex – is possible either by immersion or by EUV or by a combination of immersion and EUV exposures to form a single metal layer. At IITC, imec showed a full integration flow using multi-patterning, which enables the patterning of tight-pitch metal-cut (the blocks), and effectively scaling the trench critical dimension to 12nm at 16nm half pitch. The researchers also looked at the reliability, for example at electromigration issues caused by the movement of atoms in the interconnect wires. They demonstrated the ability of imec’s Cu metallization scheme at 16nm critical dimension with extendibility to 12nm width, and investigated full ruthenium (Ru) metallization as copper replacement.

Scaling the BEOL beyond the 5nm node

For the technology nodes below the 5nm, the team of imec is investigating a plethora of options and comparing their merits. Options include new materials for conductors and dielectrics, barrier layers, vias, and new ways to deposit them; innovative BEOL architectures for making 2.5D/3D structures; new patterning schemes; co-optimization of system and technology, etc.

For example, to achieve manufacturable processes and at the same time control the RC delay, scaling boosters, such as fully self-aligned vias, are increasingly being used. Via alignment is a critical step in the BEOL process, as it defines the contact area between subsequent interconnect levels. Any misalignment impacts both resistance and reliability. Imec’s team has shown the necessity of using a fully self-aligned via to achieve overlay specifications, and proposed a process flow for 12nm half pitch structures.

Also, self-assembled monolayers (SAMs) open routes to new dielectric and conductor schemes. SAMs composed of sub-1nm organic chains and terminated with desired functional groups can help engineering thin-film dielectric and metal interfaces, and can strongly inhibit interfacial diffusion. The use of SAMs has been a topic of research for the past ten years. Imec has now moved this promising concept from lab to fab, and combined SAMs with a barrier/liner/metallization scheme on a full wafer. The researchers investigated the implica- tions on the performance and scaling ability of this process flow, and demonstrated a ~18% reduction in the RC of 22nm half-pitch dual damascene intercon- nects, due to a better interface and thinner barrier.

For conventional BEOL metallization, a barrier layer is coated by a Cu seed barrier, and this structure is electroplated with low-resistive Cu, which acts as the conductor. But when moving to sub-10nm interconnects, the resistivity of Cu continues to increase. At the same time, the diffusion barrier – which is highly resistive and difficult to scale – is taking up more space, thereby increasing the overall resistance of the barrier/Cu structure. Therefore, alternative metals are being investigated that could possibly serve as a replacement for Cu and do not require a diffusion barrier. Among the potential candidates, such as Co, Ni, Mo, etc., platinum-group metals, especially ruthenium (Ru), have shown great promise due to their low bulk resistivity and resistance to oxidation. They also have a high melting point which can result in better electromigration behavior (FIGURE 2). Imec has realized Ru nanowires with 58nm2 cross section area. The nanowires exhibit low resistivity and robust wafer-level reliability. For example, a very high current carrying capacity with fusing currents as high as 720MA/cm2 was demonstrated.

Screen Shot 2017-11-07 at 11.50.00 AM

At the 2017 IITC conference, this author was invited to take part in a panel discussion, organized by Applied Materials, to discuss the latest developments in metallization at single-digit nodes, the challenges and bottlenecks arising at these very small dimensions, and new application-driven requirements. Distinguished speakers from the technical field reviewed viable solutions for extending the current technology and alternative options were discussed. From the discussion it is clear that the biggest immediate benefit can be found in the area of conductors – both from the material side as well as design. Indeed, it is driving the replacement of copper at specific metallization levels. Other avenues – such as dielectric innovations, functionality in the BEOL or 2D materials – remain interesting options for the R&D pipeline.

As an option that is further out, spin wave propagation in conductors is an alternative signaling to traditional electron based propagation.

Adding additional functionality in the BEOL

In the future, more and more technology options may get dictated by the requirements of systems or even applications. This could result in a separate technology for e.g. high-performance computing, low-power mobile communication, chips for use in medical applications, or dedicated chips for IoT sensors. Along the same lines, imec is investigating the benefits of introducing additional functionality in the BEOL.

More specifically, imec is evaluating the possibility of integrating thin-film organic transistors – with typically low-leakage level – into the BEOL interconnect circuitry of Si FinFETs. The potential advantages of fabricating them together are mainly a reduced power consumption and improved area saving. A variety of circuits can fully utilize the benefits of this hybrid processing, including portable applications, eDRAM, displays and FPGA applications. As a concrete example, imec researchers are currently merging imec’s expertise in BEOL technologies and in thin-film-based flat panel displays, thereby opening opportunities for new applications…

Broadcom Limited (NASDAQ: AVGO) (“Broadcom”), a semiconductor device supplier to the wired, wireless, enterprise storage, and industrial end markets, today announced a proposal to acquire all of the outstanding shares of Qualcomm Incorporated (NASDAQ: QCOM) (“Qualcomm”) for per share consideration of $70.00 in cash and stock.

Under Broadcom’s proposal, the $70.00 per share to be received by Qualcomm stockholders would consist of $60.00 in cash and $10.00 per share in Broadcom shares. Broadcom’s proposal represents a 28% premium over the closing price of Qualcomm common stock on November 2, 2017, the last unaffected trading day prior to media speculation regarding a potential transaction, and a premium of 33% to Qualcomm’s unaffected 30-day volume-weighted average price. The Broadcom proposal stands whether Qualcomm’s pending acquisition of NXP Semiconductors N.V. (“NXP”) is consummated on the currently disclosed terms of $110 per NXP share or the transaction is terminated. The proposed transaction is valued at approximately $130 billion on a pro forma basis, including $25 billion of net debt, giving effect to Qualcomm’s pending acquisition of NXP on its currently disclosed terms.

“Broadcom’s proposal is compelling for stockholders and stakeholders in both companies. Our proposal provides Qualcomm stockholders with a substantial and immediate premium in cash for their shares, as well as the opportunity to participate in the upside potential of the combined company,” said Hock Tan, President and Chief Executive Officer of Broadcom. “This complementary transaction will position the combined company as a global communications leader with an impressive portfolio of technologies and products. We would not make this offer if we were not confident that our common global customers would embrace the proposed combination. With greater scale and broader product diversification, the combined company will be positioned to deliver more advanced semiconductor solutions for our global customers and drive enhanced stockholder value.”

Tan continued, “We have great respect for the company founded 32 years ago by Irwin Jacobs, Andrew Viterbi and their colleagues, and the revolutionary technologies they developed. Following the combination, Qualcomm will be best positioned to build on its legacy of innovation and invention. Given the common strengths of our businesses and our shared heritage of, and continued focus on, technology innovation, we are confident we can quickly realize the benefits of this compelling transaction for all stakeholders. Importantly, we believe that Qualcommand Broadcom employees will benefit from substantial opportunities for growth and development as part of a larger company.”

Thomas Krause, Broadcom Chief Financial Officer, added, “The Broadcom business continues to perform very well. Broadcom has completed five major acquisitions since 2013, and has a proven track record of rapidly deleveraging and successfully integrating companies to create value for our stockholders, employees and customers. Given the complementary nature of our products, we are confident that any regulatory requirements necessary to complete a combination with Qualcomm will be met in a timely manner. We look forward to engaging immediately in discussions with Qualcomm so that we can sign a definitive agreement and complete this transaction expeditiously.”

 

“The combined Qualcomm/Broadcom operation would represent the third largest global semiconductor supplier. The Qualcomm shareholders are likely to be split with many viewing this opportunity as a solution to the worsening relations with Apple, whom Broadcom has a good relationship with. The potential merger raises significant questions surrounding the difficult takeover of NXP by Qualcomm and much is still to be discerned regarding the value of the Qualcomm patent holdings and its associated lucrative high-margin revenue stream,” said Stuart Carlaw, Chief Research Officer at ABI Research.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $107.9 billion for the third quarter of 2017, marking the industry’s highest-ever quarterly sales and an increase of 10.2 percent compared to the previous quarter. Sales for the month of September 2017 were $36.0 billion, an increase of 22.2 percent over the September 2016 total of $29.4 billion and 2.8 percent more than the previous month’s total of $35.0 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

highest ever sales

“Global semiconductor sales increased sharply year-to-year in September, and year-to-date sales through September are more than 20 percent higher than at the same point last year,” said John Neuffer, SIA president and CEO. “The industry posted its highest-ever quarterly sales in Q3, and the global market is poised to reach its highest-ever annual revenue in 2017.”

Regionally, year-to-year and month-to-month sales increased in September across all markets: the Americas (40.7 percent year-to-year/5.9 percent month-to-month), China (19.9 percent/2.5 percent), Europe (19.0 percent/1.8 percent), Asia Pacific/All Other (16.8 percent/1.9 percent), and Japan (11.9 percent/0.5 percent).

“The Americas market continued to stand out, notching its largest year-to-year sales increase in more than seven years,” Neuffer said. “Standouts among semiconductor product categories included memory products like DRAM and NAND flash, both of which posted major year-to-year growth in September, as well as Logic products, which enjoyed double-digit growth year-to-year.”

Scientists at the U.S. Department of Energy’s National Renewable Energy Laboratory (NREL) reported significant advances in the thermoelectric performance of organic semiconductors based on carbon nanotube thin films that could be integrated into fabrics to convert waste heat into electricity or serve as a small power source.

The research demonstrates significant potential for semiconducting single-walled carbon nanotubes (SWCNTs) as the primary material for efficient thermoelectric generators, rather than being used as a component in a “composite” thermoelectric material containing, for example, carbon nanotubes and a polymer. The discovery is outlined in the new Energy & Environmental Science paper, Large n- and p-type thermoelectric power factors from doped semiconducting single-walled carbon nanotube thin films.

“There are some inherent advantages to doing things this way,” said Jeffrey Blackburn, a senior scientist in NREL’s Chemical and Materials Science and Technology center and co-lead author of the paper with Andrew Ferguson. These advantages include the promise of solution-processed semiconductors that are lightweight and flexible and inexpensive to manufacture. Other NREL authors are Bradley MacLeod, Rachelle Ihly, Zbyslaw Owczarczyk, and Katherine Hurst. The NREL authors also teamed with collaborators from the University of Denver and partners at International Thermodyne, Inc., based in Charlotte, N.C.

Ferguson, also a senior scientist in the Chemical and Materials Science and Technology center, said the introduction of SWCNT into fabrics could serve an important function for “wearable” personal electronics. By capturing body heat and converting it into electricity, the semiconductor could power portable electronics or sensors embedded in clothing.

Blackburn and Ferguson published two papers last year on SWCNTs, and the new research builds on their earlier work. The first paper, in Nature Energy, showed the potential that SWCNTs have for thermoelectric applications, but the films prepared in this study retained a large amount of insulating polymer. The second paper, in ACS Energy Letters, demonstrated that removing this “sorting” polymer from an exemplary SWNCT thin film improved thermoelectric properties.

The newest paper revealed that removing polymers from all SWCNT starting materials served to boost the thermoelectric performance and lead to improvements in how charge carriers move through the semiconductor. The paper also demonstrated that the same SWCNT thin film achieved identical performance when doped with either positive or negative charge carriers. These two types of material–called the p-type and the n-type legs, respectively–are needed to generate sufficient power in a thermoelectric device. Semiconducting polymers, another heavily studied organic thermoelectric material, typically produce n-type materials that perform much worse than their p-type counterparts. The fact that SWCNT thin films can make p-type and n-type legs out of the same material with identical performance means that the electrical current in each leg is inherently balanced, which should simplify the fabrication of a device. The highest performing materials had performance metrics that exceed current state-of-the-art solution-processed semiconducting polymer organic thermoelectrics materials.

“We could actually fabricate the device from a single material,” Ferguson said. “In traditional thermoelectric materials you have to take one piece that’s p-type and one piece that’s n-type and then assemble those into a device.”

Silicon has provided enormous benefits to the power electronics industry. But performance of silicon-based power electronics is nearing maximum capacity.

Enter wide bandgap (WBG) semiconductors. Seen as significantly more energy-efficient, they have emerged as leading contenders in developing field-effect transistors (FETs) for next-generation power electronics. Such FET technology would benefit everything from power-grid distribution of renewable-energy sources to car and train engines.

Diamond is largely recognized as the most ideal material in WBG development, owing to its superior physical properties, which allow devices to operate at much higher temperatures, voltages and frequencies, with reduced semiconductor losses.

A main challenge, however, in realizing the full potential of diamond in an important type of FET — namely, metal-oxide-semiconductor field-effect transistors (MOSFETs) — is the ability to increase the hole channel carrier mobility. This mobility, related to the ease with which current flows, is essential for the on-state current of MOSFETs.

Researchers from France, the United Kingdom and Japan incorporate a new approach to solve this problem by using the deep-depletion regime of bulk-boron-doped diamond MOSFETs. The new proof of concept enables the production of simple diamond MOSFET structures from single boron-doped epilayer stacks. This new method, specific to WBG semiconductors, increases the mobility by an order of magnitude. The results are published this week in Applied Physics Letters, from AIP Publishing.

Left: Optical microscope image of the MOSCAPs and diamond deep depletion MOSFETs (D2MOSFETs) of this work. Top right: Scanning electron microscope image of a diamond D2MOSFET under electrical investigation. S: Source, G: Gate, D: Drain. Bottom right: D2MOSFET concept. The on-state of the transistor is ensured thanks to the accumulation or flat band regime. The high mobility channel is the boron-doped diamond epilayer. The off-state is achieved thanks to the deep depletion regime, which is stable only for wide bandgap semiconductors. For a gate voltage larger than a given threshold, the channel is closed because of the deeply and fully depleted layer under the gate. Credit: Institut NÉEL

Left: Optical microscope image of the MOSCAPs and diamond deep depletion MOSFETs (D2MOSFETs) of this work. Top right: Scanning electron microscope image of a diamond D2MOSFET under electrical investigation. S: Source, G: Gate, D: Drain. Bottom right: D2MOSFET concept. The on-state of the transistor is ensured thanks to the accumulation or flat band regime. The high mobility channel is the boron-doped diamond epilayer. The off-state is achieved thanks to the deep depletion regime, which is stable only for wide bandgap semiconductors. For a gate voltage larger than a given threshold, the channel is closed because of the deeply and fully depleted layer under the gate. Credit: Institut NÉEL

In a typical MOSFET structure, an oxide layer and then a metal gate are formed on top of a semiconductor, which in this case is diamond. By applying a voltage to the metal gate, the carrier density, and hence the conductivity, of the diamond region just under the gate, the channel, can be changed dramatically. The ability to use this electric “field-effect” to control the channel conductivity and switch MOSFETS from conducting (on-state) to highly insulating (off-state) drives their use in power control applications. Many of the diamond MOSFETs demonstrated to date rely on a hydrogen-terminated diamond surface to transfer positively charged carriers, known as holes, into the channel. More recently, operation of oxygen terminated diamond MOS structures in an inversion regime, similar to the common mode of operation of silicon MOSFETS, has been demonstrated. The on-state current of a MOSFET is strongly dependent on the channel mobility and in many of these MOSFET designs, the mobility is sensitive to roughness and defect states at the oxide diamond interface where unwanted carrier scattering occurs.

To address this issue, the researchers explored a different mode of operation, the deep-depletion concept. To build their MOSFET, the researchers deposited a layer of aluminum oxide (Al2O3) at 380 degrees Celsius over an oxygen-terminated thick diamond epitaxial layer. They created holes in the diamond layer by incorporating boron atoms into the layer. Boron has one less valence electron than carbon, so including it leaves a missing electron which acts like the addition of a positive charge, or hole. The bulk epilayer functioned as a thick conducting hole channel. The transistor was switched from the on-state to the off-state by application of a voltage which repelled and depleted the holes — the deep depletion region. In silicon-based transistors, this voltage would have also resulted in formation of an inversion layer and the transistor would not have turned off. The authors were able to demonstrate that the unique properties of diamond, and in particular the large band gap, suppressed formation of the inversion layer allowing operation in the deep depletion regime.

“We fabricated a transistor in which the on-state is ensured by the bulk channel conduction through the boron-doped diamond epilayer,” said Julien Pernot, a researcher at the NEEL Institute in France and an author of the paper. “The off-state is ensured by the thick insulating layer induced by the deep-depletion regime. Our proof of concept paves the way in fully exploiting the potential of diamond for MOSFET applications.” The researchers plan to produce these structures through their new startup called DiamFab.

Pernot observed that similar principles of this work could apply to other WBG semiconductors. “Boron is the doping solution for diamond,” Pernot said, “but other dopant impurities would likely be suitable to enable other wide bandgap semiconductors to reach a stable deep-depletion regime.”

The 2017 GLOBALFOUNDRIES Technology Conference (GTC) was held today in Shanghai, with GF executives, customers, partners and leaders in the Chinese semiconductor industry gathering to discuss the technologies that will enable a new era of connected intelligence. At the event, GF senior executives shed light on the company’s technologies, design solutions, and manufacturing services. The company also highlighted growing momentum around its differentiated 22FDX® technology, including customer adoption by several leading Chinese chip designers.

Mike Cadigan, GF’s senior vice president for global sales and business development, delivered a keynote speech, emphasizing GF’s expectations to become a strong leader in the Chinese semiconductor market. “Along with the rapid growth of customers, markets and applications in this region of the world, we are also continuously developing new technologies for enabling connected intelligence,” Cadigan said. “China is definitely one of our most important markets, and we will keep bringing advanced and differentiated technologies here to help our customers grow and succeed.”

At the event, GF revealed three Chinese customers that will be adopting its new 22FDX technology for next-generation wireless, battery-powered applications. Shanghai Fudan Microelectronics Group will adopt the 22FDX platform to design and develop highly reliable servers, AI and smart IoT intelligent products in 2018. Rockchip will apply 22FDX technology in the design of ultra-low power WiFi smart hardware SoC and high-performance AI processers. Hunan Goke Microelectronics is planning to adopt 22FDX in its next generation of IoT chips.

China is a key region for GF’s future growth plans. The company is building an advanced 300mm semiconductor fab in Chengdu, where a “truss-hoisting” ceremony was recently held to commemorate a major milestone in the construction of the facility, which will be called Fab 11. The construction of the fab is progressing at a fast pace and is on track to be completed in early 2018.

The company is also working closely with the Chengdu municipality to expand the FD-SOI ecosystem, with an investment of more than $100 million to make Chengdu a center of excellence for FDX IC design and IP development. Several leading semiconductor companies have already committed to supporting the ecosystem initiative, including Invecas, GF’s advanced IP development partner. Invecas has established a strong presence in China, including a recently expanded engineering team in Shanghai and Shenzhen and a commitment to set up an R&D center in Chengdu to develop and support advanced IP and designs for FD-SOI systems.