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IC Insights has raised its IC market growth rate forecast for 2017 to 22%, up six percentage points from the 16% increase shown in its Mid-Year Update.  The IC unit volume shipment growth rate forecast has also been increased from 11% depicted in the Mid-Year Update to 14% currently.  As shown below, a large portion of the market forecast revision is due to the surging DRAM and NAND flash markets.

In addition to increasing the IC market forecast for this year, IC Insights has also increased its forecast for the O-S-D (optoelectronics, sensor/actuator, and discretes) market.  In total, the semiconductor industry is now expected to register a 20% increase this year, up five percentage points from the 15% growth rate forecast in the Mid-Year Update.

For 2017, IC Insights expects a whopping 77% increase in the DRAM ASP, which is forecast to propel the DRAM market to 74% growth this year, the largest growth rate since the 78% DRAM market increase in 1994.  After including a 44% expected surge in the NAND flash market in 2017, including a 38% increase in NAND flash ASP this year, the total memory market is forecast to jump by 58% in 2017 with another 11% increase forecast for 2018.

At $72.0 billion, the DRAM market is forecast to be by far the largest single product category in the semiconductor industry in 2017, exceeding the expected NAND flash market ($49.8 billion) by $22.2 billion this year. As shown in Figure 1, the DRAM and NAND flash segments are forecast to have a strong positive impact of 13 percentage points on total IC market growth this year. Excluding these memory segments, the IC industry is forecast to grow by 9%, less than half of the current total IC market growth rate forecast of 22% when including these memory markets.

Figure 1

Figure 1

IC Insights is set to release its October Update to The McClean Report.  The 30-page Update includes a detailed analysis of IC Insights’ revised forecasts for the IC, O-S-D, and total semiconductor markets through 2021.

China IC industry outlook


October 17, 2017

SEMI, the global industry association and provider of independent electronics market research, today announced its new China IC Industry Outlook Report, a comprehensive report for the electronics manufacturing supply chain. With an increasing presence in the global semiconductor manufacturing supply chain, the market opportunities in China are expanding dramatically.

China is the largest consumer of semiconductors in the world, but it currently relies mainly on semiconductor imports to drive its growth. Policies and investment funds are now in place to further advance the progress of indigenous suppliers in China throughout the entire semiconductor supply chain. This shift in policy and related initiatives have created widespread interest in the challenges and opportunities in China.

With at least 15 new fab projects underway or announced in China since 2017, spending on semiconductor fab equipment is forecast to surge to more than $12 billion, annually, by 2018. As a result, China is projected to be the top spending region in fab equipment by 2019, and is likely to approach record all-time levels for annual spending for a single region.

Figure 1

Figure 1

This report covers the full spectrum of the China IC industry within the context of the global semiconductor industry. With more than 60 charts, data tables, and industry maps from SEMI sources, the report reveals the history and the latest industry developments in China across vast geographical areas ranging from coastline cities to the less developed though emerging mid-western regions.

The China IC industry ecosystem outlook covers central and local government policies, public and private funding, the industry value chain from design to manufacturing and equipment to materials suppliers. Key players in each industry sector are highlighted and discussed, along with insights into China domestic companies with respect to their international peers, and potential supply implications from local equipment and material suppliers. The report specifically details semiconductor fab investment in China, as well as the supply chain for domestic equipment and material suppliers.

Figure 2

Figure 2

With the prospects of large 450mm wafers going nowhere, IC manufacturers are increasing efforts to maximize fabrication plants using 300mm and 200mm diameter silicon substrates. The number of 300mm wafer production-class fabs in operation worldwide is expected to increase each year between now and 2021 to reach 123 compared to 98 in 2016, according to the forecast in IC Insights’ Global Wafer Capacity 2017-2021 report.

As shown in Figure 1, 300mm wafers represented 63.6% of worldwide IC fab capacity at the end of 2016 and are projected to reach 71.2% by the end of 2021, which translates into a compound annual growth rate (CAGR) of 8.1% in terms of silicon area for processing by plant equipment in the five-year period.

capacity install

Figure 1

The report’s count of 98 production-class 300mm fabs in use worldwide at the end of 2016 excludes numerous R&D front-end lines and a few high-volume 300mm plants that make non-IC semiconductors (such as power transistors).  Currently, there are eight 300mm wafer fabs that have opened or are scheduled to open in 2017, which is the highest number in one year since 2014 when seven were added, says the Global Wafer Capacity report.  Another nine are scheduled to open in 2018.   Virtually all these new fabs will be for DRAM, flash memory, or foundry capacity, according to the report.

Even though 300mm wafers are now the majority wafer size in use, both in terms of total surface area and in actual quantity of wafers, there is still much life remaining in 200mm fabs, the capacity report concludes.  IC production capacity on 200mm wafers is expected to increase every year through 2021, growing at a CAGR of 1.1% in terms of total available silicon area. However, the share of the IC industry’s monthly wafer capacity represented by 200mm wafers is forecast to drop from 28.4% in 2016 to 22.8% in 2021.

IC Insights believes there is still much life left in 200mm fabs because not all semiconductor devices are able to take advantage of the cost savings 300mm wafers can provide.  Fabs running 200mm wafers will continue to be profitable for many more years for the fabrication of numerous types of ICs, such as specialty memories, display drivers, microcontrollers, and RF and analog products.  In addition, 200mm fabs are also used for manufacturing MEMS-based “non-IC” products such as accelerometers, pressure sensors, and actuators, including acoustic-wave RF filtering devices and micro-mirror chips for digital projectors and displays, as well as power discrete semiconductors and some high-brightness LEDs.

Today, Intel announced the delivery of a 17-qubit superconducting test chip for quantum computing to QuTech, Intel’s quantum research partner in the Netherlands. The new chip was fabricated by Intel and features a unique design to achieve improved yield and performance.

The delivery of this chip demonstrates the fast progress Intel and QuTech are making in researching and developing a working quantum computing system. It also underscores the importance of material science and semiconductor manufacturing in realizing the promise of quantum computing.

Intel’s director of quantum hardware, Jim Clarke, holds the new 17-qubit superconducting test chip. (Credit: Intel Corporation)

Intel’s director of quantum hardware, Jim Clarke, holds the new 17-qubit superconducting test chip. (Credit: Intel Corporation)

Quantum computing, in essence, is the ultimate in parallel computing, with the potential to tackle problems conventional computers can’t handle. For example, quantum computers may simulate nature to advance research in chemistry, materials science and molecular modeling – like helping to create a new catalyst to sequester carbon dioxide, or create a room temperature superconductor or discover new drugs.

However, despite much experimental progress and speculation, there are inherent challenges to building viable, large-scale quantum systems that produce accurate outputs. Making qubits (the building blocks of quantum computing) uniform and stable is one such obstacle.

Qubits are tremendously fragile: Any noise or unintended observation of them can cause data loss. This fragility requires them to operate at about 20 millikelvin – 250 times colder than deep space. This extreme operating environment makes the packaging of qubits key to their performance and function. Intel’s Components Research Group (CR) in Oregon and Assembly Test and Technology Development (ATTD) teams in Arizona are pushing the limits of chip design and packaging technology to address quantum computing’s unique challenges.

About the size of a quarter (in a package about the size of a half-dollar coin), the new 17-qubit test chip’s improved design features include:

  • New architecture allowing improved reliability, thermal performance and reduced radio frequency (RF) interference between qubits.
  • A scalable interconnect scheme that allows for 10 to 100 times more signals into and out of the chip as compared to wirebonded chips.
  • Advanced processes, materials and designs that enable Intel’s packaging to scale for quantum integrated circuits, which are much larger than conventional silicon chips.

“Our quantum research has progressed to the point where our partner QuTech is simulating quantum algorithm workloads, and Intel is fabricating new qubit test chips on a regular basis in our leading-edge manufacturing facilities,” said Dr. Michael Mayberry, corporate vice president and managing director of Intel Labs. “Intel’s expertise in fabrication, control electronics and architecture sets us apart and will serve us well as we venture into new computing paradigms, from neuromorphic to quantum computing.”

Intel’s collaborative relationship with QuTech to accelerate advancements in quantum computing began in 2015. Since that time, the collaboration has achieved many milestones – from demonstrating key circuit blocks for an integrated cryogenic-CMOS control system to developing a spin qubit fabrication flow on Intel’s 300mm process technology and developing this unique packaging solution for superconducting qubits. Through this partnership, the time from design and fabrication to test has been greatly accelerated.

“With this test chip, we’ll focus on connecting, controlling and measuring multiple, entangled qubits towards an error correction scheme and a logical qubit,” said professor Leo DiCarlo of QuTech. “This work will allow us to uncover new insights in quantum computing that will shape the next stage of development.”

Advancing the quantum computing system

Intel and QuTech’s work in quantum computing goes beyond the development and testing of superconducting qubit devices. The collaboration spans the entire quantum system – or “stack” – from qubit devices to the hardware and software architecture required to control these devices as well as quantum applications. All of these elements are essential to advancing quantum computing from research to reality.

Also, unlike others, Intel is investigating multiple qubit types. These include the superconducting qubits incorporated into this newest test chip, and an alternative type called spin qubits in silicon. These spin qubits resemble a single electron transistor similar in many ways to conventional transistors and potentially able to be manufactured with comparable processes.

While quantum computers promise greater efficiency and performance to handle certain problems, they won’t replace the need for conventional computing or other emerging technologies like neuromorphic computing. We’ll need the technical advances that Moore’s law delivers in order to invent and scale these emerging technologies.

Intel is investing not only to invent new ways of computing, but also to advance the foundation of Moore’s Law, which makes this future possible.

A wide variety of laser technologies is today available to semiconductor manufacturers and enable the development of innovative semiconductor manufacturing processes. According to Yole Développement (Yole), the laser equipment market will grow at a 15% CAGR between 2016 and 2022 and should reach more than US$4 billion by 2022 (excluding marking). Those figures are showing the massive adoption of laser technologies for semiconductor manufacturing processes.
In its latest report titled Laser Technologies for Semiconductor Manufacturing, the market research and strategy consulting company details the status of this industry, mainly driven by dicing, via drilling and patterning in PCB flex and PCB HDI, IC substrates and semiconductor device processing.

The Laser Technologies for Semiconductor Manufacturing report from Yole provides a thorough analysis of the different existing laser equipment and laser source solutions developed for semiconductor process steps. It is a comprehensive analysis highlighting the maturity level of each laser type, based on a technical roadmap until 2022. With this new report, Yole’s analysts offer a clear understanding of the laser technologies’ benefits and added value for each manufacturing process.

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The Laser Technologies for Semiconductor Manufacturing report is the first of a wide collection of reports that will be released by Yole during the next months. Further its 1st Executive Forum on Laser Technologies taking place in Shenzhen, China, welcoming more than 100 attendees, the “More than Moore” market research and strategy consulting company Yole confirms the expansion of its activities towards the laser-based solutions. Technologies, roadmaps, market metrics, supply chain, competitive landscape, market shares and more. All these topics will be described and deeply analyzed in Yole’s laser technology & market reports.

Today, laser applications in the semiconductor industry are broad and diversified. Various laser technologies have started integrating into major semiconductor processes, including laser cutting, drilling, welding/bonding, debonding, marking, patterning, marking, measurement, deposition, driven by motherboards. They are used to process semiconductor devices, flexible and HDI PCBs , and in IC packaging applications.

Drivers of laser methods differ from one process step to another. However, there are similar and common drivers for applicability of lasers to semiconductor and PCB processing applications. The key trends driving laser applicability and contributing to its growth are:

   •  The desire for die size reduction and thus further miniaturization of devices driven by computers, hand-held electronic devices such as mobile phones, tablets and electronic book readers, wearable devices and consumer electronics.
•  Demand for increased yield and throughput.
•  Better die quality.
•  The need to inspect voids and particles through a transparent material such as glass, which requires the use of laser methods.
•  Laser annealing for very high flexibility.
However, the choice of the most suitable laser processing type depends strongly on the material to be processed, processing parameters, and the manufacturing process step.

Laser type is defined by parameters such as wavelength, emitting UV, green, or IR light, for example, as well as the duration of pulse, for example nanosecond, picosecond or femtosecond. Users must consider which pulse length and wavelength is right for their semiconductor process step and application.

Nanosecond lasers are the most commonly used type of laser applied in semiconductor manufacturing and PCB processing, with more than 60% market share. They are followed by picosecond, CO2 and femtosecond lasers. In the case of dicing step, the choice of laser type also depends on the material and substrate to be diced. For low dielectric constant (low-k) materials, nanosecond and picosecond UV lasers are used to optimize optical absorption. Picosecond and femtosecond IR lasers are typically used for cutting glass and sapphire substrates but not singulating SiC substrates.

In drilling, the type of laser employed depends on the substrate. Nanosecond UV lasers are usually employed in flexible PCBs, while CO2 lasers are largely applied for PCB HDI and IC substrates. However, for IC substrates, the choice between CO2 and nanosecond or picosecond UV lasers depends on via diameters. Below 20μm diameters, the industry tends to go to picosecond UV lasers which are much more expensive than nanosecond UV lasers but offer superior quality.

Generally speaking, CO2 is the cheapest and fastest laser solution and used in preference to nanosecond, picosecond or femtosecond solid state lasers for dicing, drilling, patterning, marking for applications that require high power and do not care about heat damage or dicing width. However, CO2 is limited when small features are needed. Nanosecond lasers are currently the dominant technology, but picosecond and femtosecond lasers could move ahead in the laser dicing equipment market. However, femtosecond laser implementation is more complex and expensive.

Yole’s laser report will provide a comprehensive overview of the laser equipment and laser sources used for each semiconductor process step application, along with a detailed analysis of laser technology trends and a market forecast. It will also offer a detailed analysis of the laser equipment market by volume and value, its growth for the 2016-2022 timeframe, and breakdown by laser type and process step application.

Global power semiconductor revenues grew year-over-year by 3.9 percent in 2016, reversing a 4.8 percent decline in 2015, according to a recent report from business information provider IHS Markit (Nasdaq: INFO).

All categories of power semiconductors (power discretes, power modules, and power integrated circuits) were up for the year, with the discretes market seeing the biggest jump. Sales in all regions increased, with China revenues topping the list. IHS Markit expects the market to grow by 7.5 percent in 2017, to $38.3 bill and achieve yearly increases through 2021.

Automotive and industrial lead the way

The automotive and industrial segments were particularly strong in 2016, with power semis in automotive growing by 7.0 percent and industrial by 5.0 percent. Advanced driver assistance systems (ADAS) – such as blind-spot detection, collision avoidance, and adaptive cruise control – are moving from luxury to mid-level vehicles, driving double digit increases for power semiconductors in that category.

Power semiconductors, especially power modules and discretes also saw sharp gains as the number of cars equipped with inverter systems for advanced start/stop and hybrid powertrains increased. In particular, power modules for cars and light trucks jumped 29.3 percent in 2016.

In the broad industrial sector the drive for energy efficiency improvement led to growth in renewable energy (solar and wind inverters), building and home control, and factory automation applications. Revenues from home appliances in the consumer segment also grew nicely as advanced motor control systems found their way into white goods, fans, kitchen, and cleaning products.

Despite good gains, other categories were flat to down. Power module sales for industrial motor drives, a large sub-segment, slid 1.1 percent and modules for traction applications were down 17.5 percent for the year.  Power ICs for consumer application declined 4.9 percent while power discretes for lighting applications were off 2.7 percent.

Growth to continue

“The industry megatrends of vehicle electrification, advanced vehicle safety, energy efficiency and connected everything will continue to drive growth over the next five years,” said Kevin Anderson, senior analyst, power management for IHS Markit. “IHS Markit predicts that the compound-average annual growth rate (CAGR) from 2016 – 2021 will be 4.8 percent.  Regionally, the highest growth is projected in China, at 6.0 percent CAGR, followed closely by the rest of Asia including Taiwan, Europe, Middle East and Africa, and the Americas – all with projected growth over 5 percent.”

IC Insights recently released its September Update to The McClean Report.  This 32-page Update included a detailed look at the pure-play foundry market.  Shown below is an excerpt from the Update.

With the rise of fabless IC companies in China, demand for foundry services in that country has also increased.  Figure 1 shows IC Insights’ listing of the top pure-play foundries and their sales to China in 2016 and a forecast for 2017.  In total, pure-play foundry sales in China are expected to jump by 16% this year to about $7.0 billion, more than double the rate of increase for the total pure-play foundry market.  As shown, only about 10% of TSMC’s sales are forecast to go into China in 2017, yet the company is expected to hold the largest share of the China foundry market this year with a 46% share, up two percentage points from 2016.

Figure 1

Figure 1

The Chinese foundry market represented 11% of the total pure-play foundry market in 2015, 12% in 2016, and is forecast to hold a 13% share this year.  As a result of this growth, most pure-play foundries have made plans to locate or expand IC production in mainland China over the next few years. TSMC, GlobalFoundries, UMC, Powerchip, and, most recently, TowerJazz have announced plans to boost their China-based wafer fabrication production.  Most of these new China-based foundry wafer fabs are scheduled to come online in late 2017 or in 2018.  UMC began 40nm production at its 300mm joint venture China fab in November of 2016 and the company is planning to introduce 28nm technology into the fab in the second half of this year with additional expansion plans to come through the end of the decade.

It is well known that China is striving to develop an indigenous semiconductor industry but gaining access to the manufacturing technology has become increasingly difficult.  As a result, many China IC companies and government entities have structured joint ventures or partnerships with foundry companies in order to access leading manufacturing technology.  The partnerships give Chinese companies much needed access to production capacity using first-rate manufacturing technology and provide the foundries with an ongoing market presence and revenue stream within China.

Examples of pure-play foundries that are working to set up new manufacturing plants in China include,

•    UMC is working with Fujian Jin Hua IC Company to construct a 300mm wafer fab in Fujian, China to manufacture DRAM using 32nm process technology developed by UMC.

•    GlobalFoundries joined with the Chengdu Government in 1Q17 to begin building a 300mm wafer fab that will manufacture ICs using mainstream 130nm and 180nm processes.  Completion is set for early 2018.

•    TSMC started construction on a wholly owned $3 billion fab in Nanjing, China that will serve as a foundry that manufactures ICs using 16nm technology.  Production is scheduled to begin in 2H18.

•    TowerJazz signed an agreement with Tacoma Semiconductor to construct a 200mm wafer fab, also in Nanjing, China.  TowerJazz will have access to 50% of the capacity.  Tacoma is responsible for the entire investment of the project.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $35.0 billion for the month of August 2017, an increase of 23.9 percent compared to the August 2016 total of $28.2 billion and 4.0 percent more than the July 2017 total of $33.6 billion. All major regional markets posted both year-to-year and month-to-month increases in August, and the Americas market led the way with growth of 39.0 percent year-to-year and 8.8 percent month-to-month. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales were up significantly in August, increasing year-to-year for the thirteenth consecutive month and reaching $35 billion for the first time,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales in August increased across the board, with every major regional market and semiconductor product category posting gains on a month-to-month and year-to-year basis. Memory products continue be a major driver of overall market growth, but sales were up even without memory in August.”

Year-to-year sales increased in the Americas (39.0 percent), China (23.3 percent), Asia Pacific/All Other (19.5 percent), Europe (18.8 percent), and Japan (14.3 percent). Month-to-month sales increased in the Americas (8.8 percent), China (3.7 percent), Japan (2.8 percent), Asia Pacific/All Other (2.2 percent), and Europe (0.6 percent).

“With about half of global market share, the U.S. semiconductor industry is the worldwide leader, but U.S. companies face intense global competition,” said Neuffer. “To allow our industry to continue to grow and innovate here at home, policymakers in Washington should enact corporate tax reform that makes the U.S. tax system more competitive with other countries. The corporate tax reform framework released last week by leaders in Congress and the Trump Administration is an important step forward. We look forward to working with policymakers to enact corporate tax reform that strengthens our industry and the U.S. economy.”

Aug 2017

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

6.94

7.55

8.8%

Europe

3.20

3.22

0.6%

Japan

3.04

3.13

2.8%

China

10.68

11.08

3.7%

Asia Pacific/All Other

9.77

9.98

2.2%

Total

33.63

34.96

4.0%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

5.43

7.55

39.0%

Europe

2.71

3.22

18.8%

Japan

2.73

3.13

14.3%

China

8.99

11.08

23.3%

Asia Pacific/All Other

8.35

9.98

19.5%

Total

28.22

34.96

23.9%

Three-Month-Moving Average Sales

Market

Mar/Apr/May

Jun/Jul/Aug

% Change

Americas

6.27

7.55

20.5%

Europe

3.11

3.22

3.8%

Japan

2.95

3.13

6.0%

China

10.25

11.08

8.1%

Asia Pacific/All Other

9.43

9.98

5.9%

Total

31.99

34.96

9.3%

By Dr. Jeongdong Choe, Senior Technical Fellow, TechInsights

There has been a great deal of speculation around the composition of Intel’s Optane™ XPoint memory technology: PCM or ReRAM, selector, layouts, patterning technology, technology node, multi-stacked cell structure, die floor plan, interconnection to each electrode (wordlines and bitlines), functional blocks, scalability and process integration.

TechInsights set about to find answers. We have analyzed Optane’s memory cell structure, materials, cell array and memory peripheral array design, layouts, process flow and circuitry. Our Advanced CMOS Essential (ACE) analyses on Intel’s XPoint memory presents our complete findings and market trend predictions. The following paragraphs present some of the highlights.

Intel XPoint memory is based on PCM and selector memory (storage) cell elements. GST-based PCM, Ge-Se-As-Si based Ovonic Threshold Switch (OTS) and two memory cell stacked array architecture are common across Intel’s and Micron’s XPoint technologies.

We examined effective memory cell area efficiency vs. memory array efficiency, and compared it to current DRAM and NAND products. In our previous analysis on XPoint memory die, we found that memory density per die is 0.62 Gb/mm2 and memory efficiency is over 91%. The memory array efficiency, however, may not represent the reality because the memory peripheral and CMOS circuitry cover most of the die area.

We can define the effective cell area efficiency as a ratio of the real area of the cell memory elements (storage) to the total die area. For example, the effective memory cell area efficiency on Toshiba 15 nm 2D planar NAND is 43.9% due to excluding BC, CSL, SSL, GSL dummy wordlines and peripheral area on a die, while memory array efficiency is 72%. Figure 1 shows comparison of the effective memory cell area efficiency for 2D/3D NAND products from Toshiba/SanDisk (Western Digital), Micron/Intel, SK Hynix and Samsung, and 3D XPoint (OptaneTM from Intel).

Figure 1. A comparison of effective memory cell area efficiency on 2D/3D NAND and XPoint memory

Figure 1. A comparison of effective memory cell area efficiency on 2D/3D NAND and XPoint memory

When it comes to the effective unit cell size per 1 bit, NAND flash devices have been scaled down from 2D NAND (320 nm2) to 48L 3D NAND (145.8 nm2) or even to 64L 3D NAND (88.5 nm2) for Toshiba NAND products, while Intel OptaneTM two cell stacked XPoint memory has 800 nm2 (effectively 2F2) (Figure 2).

Figure 2. A comparison of effective unit cell area per bit on 2D/3D NAND and XPoint memory

Figure 2. A comparison of effective unit cell area per bit on 2D/3D NAND and XPoint memory

A comparison of memory density with DRAM products shown in Figure 3 illustrates that XPoint has higher memory density (0.62 Gb/mm2) than Samsung 1x nm (0.19 Gb/mm2), SK Hynix 2y nm (0.15 Gb/mm2) and Micron 20 nm (0.094 Gb/mm2) DRAM dice. Micron announced that the memory density of XPoint would be ten times higher than commercial DRAM products. This is true if we compare it with 30 nm class DRAM products, because most of the 30 nm class DRAM products from major DRAM manufacturers have 0.06 Gb/mm2 memory density. The first commercial XPoint memory die has three times (vs. Samsung 1x DRAM) or six times (vs. Micron 20 nm DRAM) higher memory density than those of current DRAM products.

Figure 3. A comparison of die size and memory density on DRAM (25nm/20nm/18nm) and XPoint memory

Figure 3. A comparison of die size and memory density on DRAM (25nm/20nm/18nm) and XPoint memory

We found that Intel introduced some innovative and compelling technologies on their first XPoint products such as PCM/OTS stack used for memory elements, GST based PCM, Ge-Se-As-Si based OTS and carbon based conductor and 2-bit cell stacked memory array with three electrodes. Intel successfully used a 20nm SADP double patterning technology to build a very uniform GST-based PCM/OTS memory square/island. Complete details on the of TechInsights’ XPoint memory analysis can be found here.

Click here to hear more from Dr. Choe and his TechInsights colleagues on 3D NAND.

A new system combines acoustic, optical and reflectometric techniques to enable measurement of metals, dielectrics, resists and critical dimensions on a single platform.

BY CHEOLKYU KIM, Director of Metrology Product Management, Rudolph Technologies, Inc.

Rapid growth in the mobile device market is generating demand for advanced packaging solutions with higher levels of system integration and increased I/Os and functionality. This demand is driving 2.5D/3D integration of IC devices, which in turn requires sophisticated packaging technologies. Among various approaches, fan-out is gaining traction as outsourced semiconductor assembly and test (OSAT) houses and wafer foundries roll out their own technologies. As illustrated in FIGURE 1, the adoption of fan-out technology accelerated significantly in 2016, and is projected to reach $2.5 billion by 2021, a more than 10X increase from 2015.

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First generation “core” fan-out was geared toward mobile applications and had RDL lines that were typically 10/10μm (line/space) and larger. Second generation HDFO processes, which were developed to integrate multiple chips in a single package, use more RDL lines at smaller width and tighter pitch, down to 2/2μm and smaller. Growth in HDFO accelerated with the entry of Apple and TSMC in 2016 and accounts for the bulk of the fan-out growth projected through 2021 [2-4].

As design rules for HDFO approach those of front-end processes, so too will requirements for process control and, in consequence, the need for more accurate and repeatable metrology. Until now, manufacturers have characterized metal films, such as RDL and under bump metallization (UBM), using semi-automated measurement tools, such as contact profilometers, which are easy to use and relatively inexpensive. However, these tools are not the best solution for measuring a variety of products with varying topographies in high volume production.

High Density Fan-Out process control

HDFO processes include one or more RDL, the number depending on the application. Like front-end processes, HDFO processes use additive and subtractive technol- ogies to create patterns of conductive metal lines isolated by dielectric materials. As RDL lines become smaller, controlling line resistance with appropriate dimensional control has become essential. For an RDL process, the most important parameters to monitor are dielectric thickness, Cu seed layer thickness, Cu thickness and line width (CD). In general, the process must operate inside a window that varies within 10% of the target value. This, in turn, requires measurement tools with a gauge capability (3σ repeatability + reproducibility) of 10% of the variability, or 1% of the target value. In addition to delivering accuracy and repeatability, the metrology system must be able to operate on product wafers and, therefore, 1) be able to measure test structures smaller than 50μm, 2) be non contact/non-destructive/ non-contaminating, 3) be fast enough to support high volume production and 4) be able to handle the significant surface topography and substrate/wafer warpage that are induced by the HDFO process.

As shown schematically in FIGURE 2, the metrology system described here (MetaPULSE® AP, Rudolph Technologies), combines picosecond ultrasonic laser sonar (PULSETM), automated optical microscopy and reflectometry to meet all the requirements for RDL process control in a single system. The acoustic technique, well proven and widely accepted for metal film metrology in front-end applications, is a first principle technology that provides accurate measurements of metal film thickness for UBM and RDL.

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Measurements of RDL thickness with this technique on dense line arrays, pads and bumps have shown excellent correlation to cross sectional scanning electron microscope (X-SEM) results. The precision and gage capability of the technology have been validated down to 2μm and meet OSAT and foundry RDL roadmap requirements.

The integration of a high-resolution reflectometer provides accurate measurements of dielectric and resist thickness, ranging from a few 1000Å to 60μm, on product wafers. The incorporation of an automated optical microscope/high-resolution camera provides gage-capable CD measurements. CD measurements can be made simultaneously with thickness measurements. The addition of optical CD measurements and reflectometer-based transparent film thickness measurements to the acoustic platform provides an efficient and comprehensive in-line RDL metrology solution that eliminates the need to route wafers to multiple measurement tools.

PULSE acoustic thickness measurements on opaque films

FIGURE 3 illustrates the principles of the PULSE acoustic measurement technology. An extremely short laser pulse is focused onto a small spot on the sample surface where the energy of the laser pulse is absorbed by the film surface. This causes a sudden increase of surface temperature, and rapid thermal expansion launches a sound wave on the surface that travels into the film. When the sound wave reaches an interface with an underlying film, it is partially reflected back to the surface as an echo. Upon arrival at the surface, the echo causes a change in optical reflectivity, which is detected to measure the round-trip travel time of the sound wave. Film thickness can be calculated from the travel time of the sound wave and the speed of sound in the material. Some of the energy from the original sound wave is transmitted through the interface. In a multi-layered stack, the progressing sound wave returns a distinct echo from each interface. An analysis of the round-trip travel time for each successive echo permits the calculation of the thickness of each layer. Typical data acquisition times vary from 1s to 4s per site. Repeatability is < 0.1% of target thickness, meeting the 10% GR&R requirement. FIGURE 4 shows the correlation between X-SEM and PULSE measurements for RDL in the 1.25μm-1.5μm thickness range. The excellent correlation clearly demonstrates the accuracy of PULSE thickness measurements.

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Reflectometer thickness measurements on transparent films

FIGURE 5 (left) demonstrates the strong correspondence between a measured reflectometer signal and a model fitted curve for 5μm polyimide on Si. The figure also shows the correlation between reflectometer measurements and a fab reference metrology tool. The excellent correlation with the reference tool confirms the accuracy of reflectometer measurements. Data collection time for reflectometer measurements is typically less than 1s. The reflectometer has excellent sensitivity with Å level resolution and gage-capable R&R.

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Automated optical CD measurements

Using the optical microscope/ high resolution camera system, users can define multiple regions of interest (ROI) for CD measurements, including single line and multi-line arrays. The built-in measurement algorithms can report individual or average values. Extension of the CD technique to also measure overlay has shown promising results and additional work is in progress to fully characterize the capability. FIGURE 6 shows images and signals from CD measurements on lines and arrays. The strong correlation between optical CD and X-SEM measurements (FIGURE 7) validates the accuracy of the technique. CD measurement with the optical microscope is limited by the micro- scope’s resolution, typically 1μm or larger. Since SEM resolution is typically on the scale of nanometers, the correlation requires proper calibration. The results shown in Fig. 7 are after calibration.

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Multi-layered stacks

Most of RDL plating requires prior deposition of a Cu seed layer, the thickness of which must also be tightly controlled. FIGURE 8 (left) shows examples of the acoustic signals acquired from three Cu/ Ti stacks of varying thickness. The first positive peak of each signal gives the round-trip travel time of the sound wave in the Cu film, while the spacing between first and second positive peaks gives the round-trip travel time through the Ti layer. The echo positions are used to calculate the thickness of Cu and Ti layers simultaneously. Figure 8 (right) shows the signal of an Au/Ni/Cu/Al stack measured on UBM. The echo from each layer is distinct. Knowing the arrival times of the echoes and the speed of sound in the materials, the system calculates the thickness of all four layers simultaneously, with 3σ repeatability less than 1% for each of the layers.

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Warped wafer handling

The thin wafers/substrates used in HDFO processes can be warped significantly at several different steps in the process, most significantly by the mismatch between thermal expansion coefficients of the molding compound and the die. Warpage of 2mm or more poses a major challenge to handling and measurement systems. A specially designed vacuum chuck has three concentric vacuum zones. Applying vacuum to the zones sequentially, starting with the innermost zone and working out, the chuck pulls and holds warped wafers flat against itself to allow accurate measurements.

Conclusions

High density fan-out packaging is essential for advancing growth in mobile and networking applica- tions. The integration of multi-chip modules in fan-out processes requires complex processing using tools and materials that are significantly more expensive than traditional packaging lines. We have described an automated metrology solution that combines acoustic measurements with high resolution reflectometry and optical microscopy to provide comprehensive, gage- capable measurements for characterizing critical process steps in high volume production applications. Simultaneous measurement of multiple parameters on a single platform eliminates the need to route product through several different tools, improving the speed and efficiency, and reducing the overall cost-of-ownership, of the metrology process.

References

1. “Fan-out technnologies and MarketTrends 2016 Report”,Yole Devel- oppement, July 2016
2. “What is driving advanced packaging platforms development?”, T. Buisson and S. Kumar, Chip Scale Review, pp. 32-36,May-June 2016 3. “Recent advances and trends in advanced packaging”, J. Lau, Chip
Scale Review, pp. 46-54, May-June 2017.
4. “Status of Advanced Packaging Report,” Yole Developpement, June 2017.