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DSA and EUV should be envisioned as complementary, not competing, techniques that will eventually become mainstream for fine-pitch lithography.

BY DOUGLAS J. GUERRERO, Ph.D., Brewer Science, Rolla, MO

Advances in lithography have always been critical in the drive toward each subsequent semiconductor node. Anticipating limitations in the scaling ability of immersion lithography, the industry has been pursuing next-generation lithography techniques. Several techniques have been proposed, including extreme ultraviolet (EUV) lithography, multibeam electron-beam lithography, nanoimprint lithography and directed self-assembly (DSA) of block copolymers.

DSA attracted a great deal of interest from major semiconductor manufacturers for several years, following its initial development in the early 2000s. However, it has since fallen out of favor to some extent, in part because of advances in EUV lithography as a result of focused investment in that technology. Recent developments in DSA materials and processing promise to overcome concerns that have delayed its implementation.

Choosing an appropriate lithography technique does not need to be an either-or proposition. The greatest opportunity may lie in leveraging both EUV lithography and DSA. Although these two technologies are sometimes seen as competing, it makes more sense to envision them as complementary. This article explains how lithography may benefit by taking advantage of both EUV and DSA, and why previously existing roadblocks may no longer pose obstacles.

The material defines the pattern

Unlike most lithography techniques, where the mask defines the pattern, in DSA the pattern exists in the material itself. The original block copolymers (BCPs) for DSA combine polystyrene (PS) and poly(methyl methacrylate) (PMMA), two polymers that naturally segregate themselves into separate phases. Adjusting the relative proportions of PS and PMMA in the PS-b-PMMA material changes the morphology from spherical to cylindrical to lamellar (FIGURE 1). The product of the Flory interaction parameter, χ, and the segment length determine the spacing of the ordered structure. The higher the value of χ, the finer the pitch of the resulting structure.

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Standard PS-b-PMMA materials have relatively low χ, which limits the pitch to 20nm or larger. Some materials manufacturers are considering chemistries other than PS-b-PMMA to produce high-χ BCPs, replacing the PMMA component with polydimethylsiloxane or polyhydroxystyrene. Modifying PS-b-PMMA is another approach to increase χ. In this manner, it is possible to tune χ, the molecular weight and the glass transition temperature to achieve lamellar spacing between 14nm and 40nm under various annealing conditions.

The process flow for BCP deposition is straightforward. A neutral layer spin-coated onto the substrate allows for the BCP to separate into its individual domains during the thermal annealing process. The neutral layer allows for domain separation because it does not have affinity for either of the polymer chains in the BCP. Polymer domain separation is responsible for pattern formation.

Processing considerations

The DSA deposition process uses one of two basic approaches (FIGURES 2 and 3). Graphoepitaxy leverages topography to align the BCPs, depositing them into relatively deep trenches. Guide patterns define the trenches, confining the BCPs into configurations in which they align in a preferred direction. Chemical epitaxy, or chemoepitaxy, is based on a chemical pattern on a flat substrate, on top of which the BCPs self-align.

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Click to enlarge.

The semiconductor industry is pursuing both graphoepitaxy and chemoepitaxy approaches, favoring the former for producing fine-pitch vias and the latter for creating arrays of parallel lines.

Annealing temperatures are in the range of 250°C to 275°C, making them compatible with standard semiconductor processing. The annealing step can be lengthy—up to two hours to create structures with sufficiently low defect rates—adding cost to the process.

PS-b-PMMA BCPs are being manufactured in high- volume quantities. Worldwide, 1.1 million tons of the material are currently in use for a variety of applica- tions. This quantity is greater than the needs of the entire semiconductor industry. Therefore, although no commercially produced DSA materials are currently targeted for semiconductor applications, the infra- structure is in place to scale up production of suitable materials when the industry is ready.

Why DSA is attractive now

DSA was added to the ITRS roadmap in 2007. Major semiconductor industry players originally believed DSA would enter commercial production anywhere between the 14nm and 7nm logic nodes, and even sooner for DRAM; but so far that has not come to pass. A survey at the 2016 DSA Symposium suggested that the technology is still not ready for the mainstream and won’t be for several years. But some IDMs would like to accelerate the process, and there are reasons to believe this is not only possible, but desirable.

Decreasing the wavelength to 193nm immersion lithography has enabled line width and spacing down to 80nm. Techniques such as self-aligned quadruple patterning (SAQP) can create even smaller features through multiple lithography/etch iterations, but at the expense of adding lithography steps, each requiring a custom mask.

Immersion lithography is reaching its limits, providing an opportunity for next-generation lithographic techniques. Designs with critical dimensions (CD) in the range of 10nm to 30nm create a sweet spot for these state-of-the-art techniques.

Advances in EUV lithography are one factor that has led the industry to favor it over DSA. Today’s EUV materials have greater sensitivity compared with older- generation products, therefore requiring lower UV doses; and line roughness has improved as well. EUV lithography can create vias with 30nm or 40nm spacing that are not feasible with immersion lithography.

DSA enables even finer resolution than the semicon- ductor industry currently demands. Feature sizes are just now approaching a level where DSA can be especially effective. If these trends continue, the technique is poised to be widely adopted before the end of this decade.

DSA and EUV: Better together?

The most effective solution may lie in leveraging EUV and DSA technologies to take advantage of the strengths of each. Both methods can achieve resolution levels that are compatible with the N7 and N5 logic nodes. EUV lithography is well-suited to patterning designs with multiple different pitches, down to line width and spacing around 30nm. For such fine pitches, however, the number of mask steps required may make the technique prohibitively expensive. Local CD uniformity (LCDU) can also be a concern, especially at high throughput rates.

The initial hard-mask lithography process is the same for both EUV and DSA, but they diverge during pattern processing. Once the BCPs are deposited, DSA can achieve 30nm feature size without requiring additional masks. Annealing naturally separates the two phases into the correct morphology. The DSA process, however, is best suited to designs with a single pitch.

EUV can be used to pattern lower-resolution features on a chip, plus create spacers for subsequent DSA deposition. This combination provides the greatest design flexibility while streamlining the fabrication process, eliminating processing steps and reducing mask costs. LCDU is also better than with EUV alone.

DSA is best suited for devices with multiple repeating, regular fine-pitch features. Therefore, it likely will first be implemented in DRAM storage, later migrating to use in via layers on logic devices. Graphoepitaxy, especially using EUV to deposit the spacers, can enable more complex designs using DSA, where different regions of the chip require different pitches. This will presumably be the approach of choice for logic chips.

Despite the promise that leveraging both DSA and EUV offers, the semiconductor industry will only migrate to this approach once suppliers can convince IDMs that the materials have overcome their technical limita- tions. DSA has suffered from several challenges that have delayed its adoption: Primary issues are defectivity, pattern placement accuracy, ease of integration into manufacturing flows, and cost. But there is reason to be optimistic, as advances in chemistry and processing methods are improving all these metrics.

Overcoming technical challenges

The 2016 DSA Symposium survey identified defec- tivity as the greatest technical challenge. Defectivity and cost are related, in that the lowest defect levels are seen with the longest annealing times. While annealing for as little as five minutes causes the two phases to separate, the resulting material contains far too many defects to be suitable for commercial use.

Wafers are typically annealed one at a time, which can make the cost of annealing prohibitive. However, recent research using batch annealing in a vertical furnace showed great promise for reducing cost. By annealing 150 wafers in parallel for 30 minutes, researchers were able to demonstrate sufficiently low defect levels at a cost lower than that of SAQP.

Using both DSA and EUV has the potential to alleviate the problem of pattern placement errors. For example, EUV lithography can create prepatterned holes for doublet vias. The two vias may merge during the EUV process but will then automatically separate during DSA. Without DSA, an additional lithography step may be required to avoid merged vias.

This approach of leveraging EUV and DSA for fine- pitch vias is most reliable when the via shape is optimized. Studies have shown that a peanut shape, rather than an elliptical one, is ideal for creating doublet vias with minimal risk for pattern placement errors, even at the challenging N5 node.

Collaborating to advance DSA adoption

The semiconductor industry has extensive experience with lithography, but DSA requires a shift in mindset. BCP materials are not something that the industry is used to, and revolutionary rather than evolutionary changes in materials and processes can face resistance. DSA needs to be demonstrated on real devices before it can achieve traction in the semiconductor market.

Collaborative efforts between semiconductor industry materials suppliers and chemical companies with deep experience in BCPs are one route to bridge this gap. One such collaboration is currently underway. Brewer Science has teamed up with Arkema, a company with two decades of experience producing BCPs, but little leverage with the semiconductor industry. The partnership, begun in 2015, has led to pilot production of DSA materials, paving the way for the technique to move out of the laboratory and into commercial semiconductor products.

DSA and EUV should be envisioned as complementary, not competing, techniques that will eventually become mainstream for fine-pitch lithography at the N7 node and beyond. Partnerships between materials and chemical companies are poised to enable this transition, unlike previous efforts by single organizations.

The basics of laser marking are reviewed, as well as current and emerging laser technologies.

BY DIETRICH TÖNNIES, Ph.D. and DIRK MÜLLER, Ph.D., Coherent Inc., Santa Clara, CA

Laser marking is established at multiple points in semiconductor production and applications continue to diversify. There are several laser technologies servicing the application space. This article reviews the basics of laser marking and the current and emerging laser technologies they utilize. It is intended to give a clear sense of what applications parameters drive the choice of laser (speed, cost, resolution, etc.), and provide those developing a new application some guidance on how to select the optimum technology.

Laser marking basics

Laser marking usually entails inducing a visible color or texture change on a surface. Alternatively, although less commonly, marking sometimes involves producing a macroscopic change in surface relief (e.g.engraving). To understand what laser type is best for a specific marking application, it is useful to examine the different laser/ material interactions that are generated by commonly used laser types.

Most frequently, lasers produce high contrast marks through a thermal interaction with the work piece. That is, material is heated until it undergoes a chemical reaction (e.g. oxidation) or change of crystalline structure that produces the desired color or texture change. However, the particulars of this process vary significantly between different materials and laser types.

CO2 lasers have been employed extensively for PCB marking because they provide a fast method of producing high contrast features. However, they are rarely selected when marking at the die or package level. This is because the focused spot size scales with wavelength due to diffraction. CO2 lasers emit the longest infrared (IR) output of any marking laser. Additionally, IR penetrates far into many materials, which can cause a substantial thermal impact on surrounding structures. Consequently, CO2 laser marking is limited to producing relatively large features where a significant heat affected zone (HAZ) can be tolerated.

Fiber lasers, which offer high power output in the near IR, have emerged over the past few years as one of the most cost effective tools for high-speed marking. Furthermore, the internal construction of fiber lasers renders a compact footprint, facilitating their integration into marking and test handlers. Cost and space savings are further enhanced when the output of a single, high power fiber laser is split, feeding two scanner systems.

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But fiber lasers have disadvantages, too. One reason for the low cost of many fiber lasers is that they are produced in high volumes with designs meant for general-purpose applications. For example, they usually produce a high quality beam with a Gaussian intensity profile. This is advantageous for many material processing applications, but not always for laser marking. In fact, a more uniform beam intensity distribution, called a flat-top profile, is sometimes more useful since it produces marks with a sharper, more abrupt edge (rather than a smooth transition from the marked to the unmarked region). Coherent recently introduced a new type of fiber (NuBEAM Flat-Top fiber technology) which enables efficient conversion of single-mode laser beams into flat-top beam profiles, specifically to address this issue.

Other quality criteria, such as high-purity linear polarization, and stability of pulse energy and pulse width, are difficult to achieve with low-cost fiber lasers. This limits their use in more stringent or sensitive marking applications. From a practical standpoint, most fiber lasers cannot be repaired in the field, but are replaced as a whole. This leads to longer equipment downtime and increased maintenance efforts as compared to traditional marking lasers based on diode-pumped, solid-state (DPSS) technology (specifically, DPSS is used here to refer to lasers with crystal resonators).

DPSS lasers also emit in the near infrared. Generally, these lasers are more expensive than a fiber laser of the same output power level. So, infrared DPSS lasers are most commonly used in applications having technical requirements that cannot be met by fiber lasers,such as high volume production of more advanced and expensive semiconductor devices.

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One advantage of DPSS laser technology is that it can be configured to directly produce a multi-mode beam profile which is essentially flat-top. The Coherent ❘ Rofin PowerLine E Air 30-1064 IC is an example which has found extensive use in semiconductor marking, since it provides an efficient way to rapidly produce very high contrast marks.

Another useful feature of DPSS lasers, which produce pulsewidths in the nanosecond regime, is that their output is much more stable than that of fiber lasers. This makes it much easier to reliably frequency double or triple their infrared light within the laser head, giving a choice of output in the green or ultraviolet (UV). Output at these wavelengths provides two significant benefits. First, they offer additional options in matching the absorption of the material to the laser wavelength. Stronger absorption generally yields higher marking efficiency and reduced HAZ, since the laser light doesn’t penetrate as far into the material. The second benefit of shorter wavelengths is the ability to focus to smaller spot sizes (because of their lower diffraction) and produce smaller, finer marks.

However, frequency multiplied DPSS lasers are generally more costly and voluminous than either fiber lasers or infrared DPSS lasers with comparable output power. Lower power translates into reduced marking speed.

Therefore, green and UV DPSS lasers are typically employed when they offer a significant advantage due to the particular absorption characteristics of the material(s) being marked.

Another emerging and important class of marking lasers has pulsewidths in the sub-nanosecond range. Due to the nature of the laser/material interaction at short pulsewidths, these lasers tend to produce the smallest possible HAZ with excellent depth control.

There are just a few products currently on the market that exploit this property. One example is the PowerLine Pico 10 from Coherent ❘ Rofin which generates 0.5 ns laser pulses in either the near IR (8 W total power) or green (3 W total power), at pulse repetition rates between 300 kHz and 800 kHz. This combination of output characteristics makes it capable of high speed marking of a wide range of materials where mark penetration depth must neces- sarily be shallow because of low material thickness, or to minimize HAZ.

Laser marking today

Typically, the first consideration in choosing a laser for a specific application is matching the absorption characteristics of the material with the laser wavelength. Similarly, desired feature size is also driven by laser wavelength, as well as by the precision of the beam scanning system. Next, HAZ constraints usually determine the maximum pulsewidth which can be used (although this choice is again highly material dependent). To see how these parameters interact in practice, it’s useful to review some real world applications.

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Epoxy-based molding compounds

The most commonly used molding compounds absorb very well in the near IR. Specifically, the near IR laser transforms the usually black molding compound into a gray/white powder, yielding high contrast marks. Plus, many IC packages have mold compound caps thick enough to easily tolerate a marking depth of 30 μm to 50 μm. As a result, many marking systems based on near IR lasers, both fiber and DPSS, are currently in use.

However, some semiconductor devices with small form factor have only thin mold compound caps to protect wire bonded silicon dies, and a marking depth of only 10 μm or less is required. Increasingly, green lasers are used for this type of shallow marking because of a stronger absorption at this wavelength by the epoxy matrix.

Ceramics

The process window when marking ceramics, such as used in packaging power semiconductors, high-brightness LEDs, RF devices, saw filters or MEMS sensors, is relatively narrow. Accurate focus and high pulse energy are critical to ensure reliable marking results, and ideally, the laser marker should have the capability to adjust the focus of the laser beam onto the ceramic surface in real time, in order to compensate for package height variations. Because of their more reliable interaction with ceramic materials, DPSS lasers based on Nd:YAG, which offer high pulse energies and relatively long pulses, are often still used for marking ceramic lids and substrates. Coherent ❘ Rofin has also developed a special fiber laser (the PowerLine F 20 Varia IC), which offers adjustable pulse widths up to 200 ns, specifically to improve process windows for marking applications of this type.

The ceramic substrates used with high-power LEDs often require tiny marks to identify individual devices. IR lasers are the preferred lasers for marking these ceramic substrates, providing their spot size is not too big for the layout to be marked. For very small marking features a green laser or UV laser is often required.

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Organic substrates

IC substrates or interposers are marked during production with traceable data matrix codes. The thin green solder resist layer on top of the substrate has to carry the mark, and care has to be taken that the copper underneath the solder resist is not exposed. Moreover, data matrix codes can be quite small, with cell sizes of only 125 μm or even less. Since the spot size of the focused laser beam must thus be much smaller than the cell size, the final spot diameter must be significantly less than 100 μm.

Defective IC substrates often are identified by marking large features (e.g., a cross) into the solder resist layer. Although the part is defective, the properties of the mark are still important. This is because it has to be reliably recognized by subsequent processing tools, and also, because any delamination of the solder resist layer might cause problems during succeeding processes.

IC strips have gold pads along their periphery which are used to identify parts found to be defective after die attach and wire bonding. For defective parts, the gold pad is marked by converting its color from gold to black or to dark grey.

Ideally, it is desirable to have one laser marker that can accomplish all three of these marking applications tasks. The green DPSS laser has become the standard laser marker for these applications, with UV lasers occasionally employed for high-end substrates.

Semiconductors

The growing demand for flip-chip devices, wafer-level packaging and defective die identification drives the need for direct marking of silicon, GaAs, GaN/sapphire or other semiconductors. Silicon is partially trans- parent in the near IR, and lasers at this wavelength are used whenever deep marks into silicon are required, such as placing wafer IDs near the wafer edge. Near IR laser markers are also selected for marking molded fan-out wafer level packaging wafers.

However, for marking either flip-chips or the backside of wafers, green lasers are preferred because of the strong absorption of this wavelength in silicon. Wafer backside marking requires only very shallow marks and the shallow laser penetration avoids potential damage to the circuitry on the reverse side of the flip-chip or wafer. The need for shallow marking also minimizes the laser power requirement. For example, Coherent ❘ Rofin provides a 6 W green laser (the PowerLine E 12 SHG IC) that is well suited for wafer backside marking, and can also mark the wafer through the tape whenever the wafer is mounted on a film frame.

Metals

Near IR lasers are widely used for marking the metal lids used with microprocessors and other high power consumption ICs.

Leadframes, which are plated with tin, silver or gold, are marked either before or after plating. Since leadframes are used for cost sensitive devices, capital investment is critical, and economical fiber lasers are often chosen for this reason.

Laser marking tomorrow

As packages get thinner and smaller, they will require shallower, higher resolution marks. Sub-nanosecond lasers are the most promising method for producing these types of marks, and are compatible with a wide range of materials. The diverse capabilities of this technology are shown in Figure 5, which depicts marking results on four different materials using a sub-nanosecond laser (Coherent ❘ Rofin PowerLine Pico 10-532 IC).

The first image is a flexible IC substrate; very thin solder resist layers and metal coatings make it important that the laser does not cause delamination. Here, the circular gold pad has been converted to black without delamination. In the next image, an IC substrate has been given a white mark, again without delaminating the solder resist.

The third image shows very small characters (< 150 μm) marked on the backside of a silicon wafer containing hundred thousands of tiny discrete semiconductor devices. Producing marks of this resolution through the film would be difficult to accomplish with a nanosecond pulsewidth laser.

The final image is a copper leadframe coated with thin silver film. Here, the goal is to produce a shallow mark with high contrast without engraving the under- lying material, which has been accomplished with the sub-nanosecond laser.

Conclusion

Semiconductor fabrication and packaging represent challenging marking applications, often requiring small, fine marks produced without a significant effect on surrounding material. An overall trend towards smaller and thinner device geometries will drive increased use of higher precision laser tools, such as those utilizing green and UV nanosecond lasers, and even sub-nanosecond lasers, while cost-sensitive applications will continue to utilize inexpensive fiber lasers.

IC Insights has just released its September Update to The McClean Report.  This 32-page Update includes a detailed look at the pure-play foundry market and an analysis of the historical DRAM price-per-bit trends.  Shown below is an excerpt from the Update that examines the IC technology trends in the pure-play foundry market.

In 2017, the 7% increase in the total pure-play foundry market is forecast to be almost entirely due to an 18% jump in <40nm feature size device sales (Figure 1).

Figure 1

Figure 1

Although expected to represent 60% of total pure-play foundry sales in 2017, the ≥40nm pure-play IC foundry market is forecast to be up only $0.2 billion this year.  In contrast, the 2017 leading-edge <40nm pure-play foundry market is expected to surge by a hefty $3.3 billion.  Moreover, not only is almost all of the pure-play foundry growth forecast to come from leading-edge production in 2017, most of the profits that are expected to be realized in the foundry market also forecast to come from the finer feature sizes as well.

TSMC is by far the technology leader among the major pure-play foundries.  In 2017, 58% of TSMC’s revenue is expected to come from <40nm processing, more than double percentage at GlobalFoundries and more than triple the share at UMC.  In total, TSMC is forecast to hold an 86% share of the total <40nm pure-play foundry market this year.

Illustrating how dominant TSMC is in the leading-edge pure-play foundry market, the company is expected to have almost 7x the dollar volume sales at <40nm as compared to GlobalFoundries, UMC, and SMIC combined this year ($18.5 billion for TSMC and $2.7 billion for combined total of GlobalFoundries, UMC, and SMIC).  In fact, 10% of TSMC’s total sales this year are forecast to be for its 10nm process technology.

In contrast to TSMC, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production.  In fact, only 7% of SMIC’s 2017 sales are expected to be from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so much less compared to TSMC.

Despite a slightly down first quarter, the semiconductor industry achieved near record growth in the second quarter of 2017, posting a 6.1 percent growth from the previous quarter, according to IHS Markit (Nasdaq: INFO). Global revenue came in at $101.4 billion, up from $95.6 billion in the first quarter of 2017. This is the highest growth the industry has seen in the second quarter since 2014.

The memory chip market set records in the second quarter, growing 10.7 percent to a new high of $30.2 billion with DRAM and NOR flash memory leading the charge, growing 14 percent and 12.3 percent quarter-on-quarter, respectively.

“The DRAM market had another quarter of record revenues on the strength of higher prices and growth in shipments,” said Mike Howard, director for DRAM memory and storage at IHS Markit. “Anxiety about product availability in the previous third and fourth quarters weighed on the industry. This led many DRAM buyers to build inventory — putting additional pressure on the already tight market. This year is shaping up to smash all DRAM revenue records and will easily pass the $60 billion mark.”

“For NOR, the supply-demand balance has tightened raising average selling prices and revenue,” said Clifford Leimbach, senior analyst for memory and storage at IHS Markit. “This mature memory technology has been in a steady decline for many years, but some market suppliers are reducing supply or leaving the market, which has tightened supply recently, resulting in the increase of revenue.”

In terms of application, consumer electronics and data processing saw the most growth, increasing in revenue by 7.9 percent and 6.8 percent, respectively, quarter-on-quarter. A lot of this growth can be attributed to the continual growth in memory pricing, as supply still remains tight.

Industrial semiconductors showed the third highest growth rate at 6.4 percent during the same period. This growth can be attributable to multiple segments, such as commercial and military avionics, digital signage, network video surveillance, HVAC, smart meters, traction, PV inverters, LED lighting and medical electronics including cardiac equipment, hearing aids and imaging systems.

Another trend in the industrial market is increasing factory automation, which alone is driving growth for discrete power transistors, thyristors, rectifiers and power diodes. The market for these devices is expected to reach $8 billion in 2021, up from $5.7 billion in 2015.

Intel remains the number one semiconductor supplier in the world, followed by Samsung Electronics by a slight margin. IHS Markit does not include foundry operations and other non-semiconductor revenue in the semiconductor market rankings.

Among the top 20 semiconductor suppliers, Advanced Micro Devices (AMD) and nVidia achieved the highest revenue growth quarter over quarter by 24.7 percent and 14.6 percent, respectively. There was no market share movement in the top 10 semiconductor suppliers. However, seven of the 10 companies in the 11 to 20 market share slots did change market share.

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Soitec, a designer and manufacturer of semiconductor materials for the electronics industry, is launching a pilot line to produce fully depleted silicon-on-insulator (FD-SOI) wafers in its Singapore wafer fab. This is the first stage in beginning FD-SOI production in Singapore and providing multi-site FD-SOI substrate sourcing to the global semiconductor market.

“Our decision to launch this FD-SOI line in Singapore as well as the decision we already made to ramp up our FD-SOI production in France are based on direct customer demand,” said Paul Boudre, CEO of Soitec. “These are very important milestones for Soitec and the expanding FD-SOI ecosystem. In Singapore, we plan to get full qualification at the customer level in the first half of 2019 and then increase capacity in line with market commitment.”

The FD-SOI ecosystem continues to strengthen and the use of FD-SOI technology is progressing. Multiple foundries, IDMs and fabless customers are engaged with a growing number of FD-SOI tape-outs and wafer starts. FD-SOI offers a unique value proposition for low-power applications, which makes it well suited for rapidly growing electronic market segments such as mobile processing, IoT, automotive and industrial.

Soitec reports that its investment in Singapore to launch its FD-SOI pilot line is approximately US$40 million, to be spent over a 24-month period.

Historically, the DRAM market has been the most volatile of the major IC product segments. Figure 1 reinforces that statement by showing that the average selling price (ASP) for DRAM has more than doubled in just one year. In fact, the September Update to The McClean Report will discuss IC Insights’ forecast that the 2017 price per bit of DRAM will register a greater than 40% jump, its largest annual increase ever!

Just one year ago, DRAM buyers took full advantage of the oversupply (excess capacity) portion of the cycle and negotiated the lowest price possible with the DRAM manufacturers, regardless of whether the DRAM suppliers lost money on the deal. Now, with tight capacity in the market, DRAM suppliers are getting their “payback” and charging whatever the market will bear, regardless of whether the price increases hurt the users’ electronic system sales or causes it to lose money.

Figure 1

Figure 1

The three remaining major DRAM suppliers—Samsung, SK Hynix, and Micron—are each currently enjoying record profits from their memory sales.  For example, Micron reported net income of $1.65 billion on $5.57 billion in sales—a 30% profit margin—in its fiscal 3Q17 (ending in May 2017).  In contrast, the company lost $170 million in its fiscal 4Q16 (ending August 2016).  A similar turnaround has occurred at SK Hynix.  In 2Q17, SK Hynix had a net profit of $2.19 billion on sales of $5.94 billion—a 37% profit margin.  In contrast, SK Hynix had a net profit of only $246 million on $3.39 billion in sales one year ago in 2Q16.

Previously, when DRAM capacity was tight and suppliers were enjoying record profits, one or more suppliers eventually would break rank and begin adding additional DRAM capacity to capture additional sales and marketshare. At that time, there were six, eight, or a dozen DRAM suppliers.  If the supplier was equipping an existing fab shell, new capacity could be brought on-line relatively quickly (i.e., six months).  A greenfield wafer fab—one constructed on a new site—took about two years to reach high-volume production.  Will the same situation play out with only three DRAM suppliers left to serve the market?

Recently, Micron stated that it does not intend to add DRAM wafer capacity in the foreseeable future. Instead, it will attempt to increase its DRAM output by reducing feature size that, in turn, reduces die size.   Eventually, as the company moves down the learning curve, it will be able to ship an increasing number of good die per wafer.  However, SK Hynix, in its 2Q17 financial analyst conference call, stated that it plans to begin adding DRAM wafer capacity since it is not able to meet increasing demand by technology advancements alone.  Samsung has been less forthcoming in its plans for future DRAM production capacity.

Although Samsung and Micron may tolerate SK Hynix’s DRAM expansion efforts for a short while, IC Insights believes that both companies will eventually step up and add DRAM wafer start capacity to protect their marketshare—and DRAM ASPs will begin to fall.  As the old saying goes, it only takes two companies to engage in a price war—and there are still three major DRAM suppliers left.

The latest update to the World Fab Forecast report, published on September 5, 2017 by SEMI, again reveals record spending for fab equipment. Out of the 296 Front End facilities and lines tracked by SEMI, the report shows 30 facilities and lines with over $500 million in fab equipment spending.  2017 fab equipment spending (new and refurbished) is expected to increase by 37 percent, reaching a new annual spending record of about US$55 billion. The SEMI World Fab Forecast also forecasts that in 2018, fab equipment spending will increase even more, another 5 percent, for another record high of about $58 billion. The last record spending was in 2011 with about $40 billion. The spending in 2017 is now expected to top that by about $15 billion.

fab equipment spending

Figure 1: Fab equipment spending (new and refurbished) for Front End facilities

Examining 2017 spending by region, SEMI reports that the largest equipment spending region is Korea, which increases to about $19.5 billion in spending for 2017 from the $8.5 billion reported in 2016. This represents 130 percent growth year-over-year. In 2018, the World Fab Forecast report predicts that Korea will remain the largest spending region, while China will move up to second place with $12.5 billion (66 percent growth YoY) in equipment spending. Double-digit growth is also projected for Americas, Japan, and Europe/Mideast, while other regions growth is projected to remain below 10 percent.

The World Fab Forecast report estimates that Samsung is expected to more than double its fab equipment spending in 2017, to $16-$17 billion for Front End equipment, with another $15 billion in spending for 2018. Other memory companies are also forecast to make major spending increases, accounting for a total of $30 billion in memory-related spending for the year. Other market segments, such as Foundry ($17.8 billion), MPU ($3 billion), Logic ($1.8 billion), and Discrete with Power and LED ($1.8 billion), will also invest huge amounts on equipment. These same product segments also dominate spending into 2018.

In both 2017 and 2018, Samsung will drive the largest level in fab spending the industry has ever seen. While a single company can dominate spending trends, SEMI’s World Fab Forecast report also shows that a single region, China, can surge ahead and significantly impact spending. Worldwide, the World Fab Forecast tracks 62 active construction projects in 2017 and 42 projects for 2018, with many of these in China.

For insight into semiconductor manufacturing in 2017 and 2018 with more details about capex for construction projects, fab equipping, technology levels, and products, visit the SEMI Fab Database webpage (www.semi.org/en/MarketInfo/FabDatabase) and order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,200 facilities including over 80 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $33.6 billion for the month of July 2017, an increase of 24.0 percent compared to the July 2016 total of $27.1 billion and 3.1 percent more than the June 2017 total of $32.6 billion. All major regional markets posted both year-to-year and month-to-month increases in July, and the Americas market led the way with growth of 36.1 percent year-to-year and 5.4 percent month-to-month. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Worldwide semiconductor sales increased on a year-to-year basis for the twelfth consecutive month in July, reflecting impressive and sustained growth for the global semiconductor market,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales in July increased throughout every major regional market and semiconductor product category, demonstrating the breadth of the global market’s recent upswing, and the industry is on track for another record sales total in 2017.”

Year-to-year sales increased in the Americas (36.1 percent), China (24.1 percent), Asia Pacific/All Other (20.5 percent), Europe (18.9 percent), and Japan (16.7 percent). Month-to-month sales increased in the Americas (5.4 percent), Asia Pacific/All Other (2.8 percent), China (2.7 percent), Japan (2.1 percent), and Europe (1.2 percent).

To find out how to purchase the WSTS Subscription Package, which includes comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, please visit http://www.semiconductors.org/industry_statistics/wsts_subscription_package/. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2017 SIA Databook: https://www.semiconductors.org/forms/sia_databook/.

Jul 2017

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

6.59

6.94

5.4%

Europe

3.16

3.20

1.2%

Japan

2.98

3.04

2.1%

China

10.41

10.69

2.7%

Asia Pacific/All Other

9.50

9.77

2.8%

Total

32.64

33.65

3.1%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

5.10

6.94

36.1%

Europe

2.69

3.20

18.9%

Japan

2.60

3.04

16.7%

China

8.61

10.69

24.1%

Asia Pacific/All Other

8.11

9.77

20.5%

Total

27.13

33.65

24.0%

Three-Month-Moving Average Sales

Market

Feb/Mar/Apr

May/Jun/Jul

% Change

Americas

6.08

6.94

14.2%

Europe

2.99

3.20

7.3%

Japan

2.88

3.04

5.7%

China

10.13

10.69

5.6%

Asia Pacific/All Other

9.21

9.77

6.0%

Total

31.29

33.65

7.5%

Lam Research Corporation (Nasdaq:LRCX), a global supplier of innovative wafer fabrication equipment and services to the semiconductor industry, announced that it has completed the acquisition of Coventor, Inc., a provider of simulation and modeling solutions for semiconductor process technology, micro-electromechanical systems (MEMS), and the Internet of Things (IoT). The combination of Lam and Coventor supports Lam’s advanced process control vision and is expected to accelerate process integration simulation to increase the value of virtual processing, further enabling chipmakers to address some of their most significant technical challenges.

“We see a strong synergy between our modeling capability and Lam’s desire to enable virtual experimentation of process development for customers and within its business units,” said Mike Jamiolkowski, president and CEO of Coventor. “We believe that our combination will increase the value we can deliver to our customers by providing more capability and improving their time to market.”

Customers rely on Coventor software and expertise to help predict the structures and behavior of designs before committing to time-consuming and costly wafer fabrication. This fast and accurate “virtual fabrication” allows technology developers and manufacturers to understand process variation effects early in the development timeframe and reduce the number of silicon learning cycles required to bring a successful product to market.

“We are looking forward to Coventor being a part of Lam and increasing the value and contribution we jointly provide to our customers,” said Rick Gottscho, executive vice president and corporate chief technical officer of Lam Research. “To keep pace with future design requirements, new technologies such as virtual fabrication and processing will be crucial to improve time to market. Together, our collective goal is to deliver more simulation, more virtual fabrication, and an overall increase in computational techniques to support the development of next-generation transistors, memories, MEMS and IoT devices.”

By Ajit Manocha, president and CEO, SEMI

In my first six months at SEMI, I’ve visited with many member companies and industry leaders.  One theme I hear repeatedly is a concern about our most fundamental source of innovation and productivity – people.

Our industry has a significant need for additional workers and several trends are working against us.

For one, only 11 percent of elementary students in the U.S. indicate an interest in science, technology, engineering, and mathematics (STEM) education according to the National Science Foundation.  In other regions, recruiting and retaining high-skilled workers remains a constant challenge.

Ironically, the incredible electronics manufacturing technology that we create has enabled many of the new-tech industries in software, social media, internet services and applications that now directly compete for the best and brightest technical talent.  Young engineers have other choices and many are lured to newer growth industries with familiar internet brands.

Today, due to continued industry advancement and robust growth, capital equipment companies, device makers and materials companies collectively have thousands to tens-of-thousands of open unfilled positions. Furthermore, the representation of women in the high-tech workplace remains disproportionately low.

We have long been aware of the need to support a diverse pipeline for high-skilled workers.  In 2001, the SEMI Foundation was established to encourage STEM education and stimulate interest in high-tech careers. SEMI and its Foundation launched the High-Tech U (HTU) program to engage and excite high school students. HTU enlists industry volunteers to work with local high school students in a three-day interactive hands-on curriculum. Young people get a fun and inspirational exposure to binary logic, circuit making, a fab or electronics manufacturing setting and other aspects of professional development.

To date, we’ve delivered 216 HTU programs and reached nearly 7,000 students in 12 states and nine countries.  The results are compelling.  Our 2016 survey of HTU alumni shows that they enter college at five times the national rates and 70 percent that graduated college are employed in a STEM field.   By any measure, the initiative is successful and worthwhile.

However, the talent problem statement has grown. Industry needs are greater and the time has come to redouble our effort to attract and retain talent for our high-skilled manufacturing sector.  Therefore, SEMI is elevating workforce development as a top strategic priority.

The SEMI HTU team is already engaged with key member companies to develop our enhanced roadmap for workforce development including a comprehensive study with Deloitte Consulting to underpin the key problems and solutions in areas of focus for decisive and systematic SEMI action.

Belle Wei, SEMI Foundation Board member and the Carolyn Guidry Chair in Engineering Education and Innovative Learning at San Jose State University said, “It is critical that we work to prepare the future workforce.  This requires a high level of collaboration between industry and higher education.  We appreciate SEMI’s leadership role in this collaboration to further develop the workforce pipeline.”

We have launched a HTU Certified Partner Program (CPP) with the goal of reaching more students through industry partners who commit to long-term participation and independent delivery of High Tech U.  In addition, we are expanding outreach to universities and community colleges and preparing to launch an industry image campaign to better tell the remarkable story of opportunity in our industry.

The capacity to innovate and the skills to manage complex design, engineering and manufacturing processes are essential factors that sustains our high-tech industry – and they are dependent on people.

Finally, as mentioned above, we have already started some new initiatives to enhance our HTU. A SEMI workforce development roadmap and execution plan will be detailed in a future SEMI Global Update article following the upcoming SEMI International Board Meeting.  SEMI welcomes any inputs in addition to your continued support.

This endeavor is increasingly urgent and recruiting the industry’s future innovators is well-aligned with SEMI’s mantra to connect, collaborate, innovate, grow and prosper.