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As 3D NAND becomes the mainstream technology, its challenging roadmap poses opportunities for continued innovation.

BY HARMEET SINGH, Lam Research Corp., Fremont, CA

Since its introduction several years ago, 3D NAND has become a mainstream technology because of its ability to increase bit density in memory devices. Its adoption has been accelerated by advances in the underlying manufacturing processes that are enabling 3D architectures and lowering the cost per bit. With all its advantages, however, the overall complexity and capital intensity of 3D NAND manufacturing add significantly to the challenges fabs are facing in terms of process control, yield, and economics.

Market and technology drivers for 3D NAND

The main impetus for 3D NAND was the recognition that planar technology was approaching the end of its physical limits to deliver higher densities and a lower cost-per-bit. Past advances in conventional planar NAND technology have primarily been driven by physical scaling, where lithography capabilities determined just how many memory cells could fit within a given die size. Using multiple levels of charge within each cell by going from single- to multi-level cell designs has also enabled increased bit densities. However, these improvements typically have come at the expense of speed because of the need to differentiate between the multiple levels of charge. In addition, since the individual memory cells for these designs lie in a horizontal plane, scaling is still ultimately limited by lithography. Other challenges in scaling 2D NAND beyond the 15 nm node include cell-to-cell interference, unscalable dielectrics, and electron leakage [1].

To address these challenges, 3D NAND fundamentally changes the scaling paradigm. Instead of traditional X-Y scaling in a horizontal plane, 3D NAND scales in the Z-direction by stacking multiple layers of NAND gates vertically. This allows more cells to be packed into the same X-Y space (planar area) on the die without shrinking dimensions horizontally. By easing cell size requirements, triple- and even quadruple-level cell designs are possible. As such, 3D NAND offers a signif- icant increase in bit density over planar NAND.

Unlike planar NAND, where scaling is primarily driven by lithography, 3D NAND scaling is enabled by advances in deposition and etch processes. An incredible level of precision and repetition is required in defining complex 3D structures with extremely high aspect ratio (HAR) features. Achieving success with 3D NAND requires innovative deposition and etch solutions that minimize variability.

Overview of critical 3D NAND processes

The 3D NAND architecture requires advanced capabilities enabling HAR and complex structures (FIGURE 1). Critical processes involved include multilayer stack deposition, HAR channel etch, wordline metallization, staircase etch, HAR slit etch, and stair contacts formation. The following sections look at some of these areas in more depth and describe the most critical process parameters that must be controlled.

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Film deposition

Creating stacked memory cells starts with depositing alternating layers of thin films. Unlike planar NAND, where cell pitch is defined by lithography, pitch in 3D NAND is determined by the film thickness. As such, precise control of layer-to-layer deposition uniformity is extremely important. Currently, commercial 3D NAND products in high-volume manufacturing have layers ranging from 32 to 48 pairs, while next-generation products with more than 60 pairs are now beginning high-volume ramps.

Critical requirements for depositing stacked films are the stress and uniformity of the individual layers within the overall stack. These requirements become more stringent and increasingly more challenging to meet as the number of layers grows. Wafer bow and local film stress (FIGURE 2) directly impact the ability to achieve precise lithog- raphy overlay. Film thickness and repeatability affects the active area of cell and consistency of the litho/etch performance. As a result, both film stress control and excellent uniformity are critical to wafer yields. To address these concerns, careful management of stress by tuning deposition conditions and optimizing integration is needed not only for the film stack deposition, but also throughout 3D NAND manufacturing.

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High aspect ratio channel etching

HAR channel etch is the most critical and challenging step in 3D NAND because it is key to achieving uniform hole size through multiple layers to define the channel of memory cells. More than a trillion holes must be etched simultaneously and uniformly on every wafer, each with an aspect ratio of more than 40:1. For comparison, the highest aspect ratio structure that is etched in planar NAND is less than 15:1.

Deep etch on these multilayer stacks can push the limits of physics to achieve uniformity from top to bottom. As shown in FIGURE 3, the high aspect ratio of this etch leads to transport limitation challenges that can generate a range of problems. These include incomplete etch wherein some holes don’t reach the bottom, bowing, twisting, and CD variation between the top and bottom of the stack. Such defects can lead to shorts, interference between neighboring memory strings, and other perfor- mance issues. Solving these HAR-related transport issues requires precise control of high-energy ions during the etch process. Technologies that help deliver this capability include a symmetric chamber design for intrinsic uniformity, a proprietary high ion energy source with advanced plasma confinement and modulation, and orthogonal (independent) uniformity tuning knobs, such as multi-zone gas delivery and temperature control to achieve required uniformity across the wafer.

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As the 3D NAND roadmap adds more layers to achieve higher bit density, channel hole etching becomes increasingly challenging due to higher aspect ratios. Managing the fundamental trade-offs among profile, selectivity, and CD requires continuous equipment innovation, not only to deliver HAR etching capabilities for more than 100 pairs, but also to do this at the productivity needed for volume manufacturing.

Wordline tungsten metal fill

For replacement-gate 3D NAND schemes, wordline tungsten fill provides the critical conductive links between individual memory cells within layers. This process is particularly challenging because of the need to achieve void-free fill of complex, narrow, lateral structures with minimal stress on the memory stack.

Due to the structural complexity, atomic-scale engineering is required for wordline fill. Traditional CVD tungsten films have inherent characteristics that limit capability for 3D NAND wordline fill. High tensile stress in CVD tungsten can lead to wafer bow, and fluorine in the process has been known to diffuse into adjacent layers where it can create yield-limiting defects. In addition, resistivity limits scaling: making each layer thinner would allow for more layers (more storage bits), but would also make wordline resistance too high. One approach to address these concerns is the use of a low-fluorine tungsten (LFW) ALD process. This has the ability to provide a smoother morphology that conforms better with the surface in each fill layer, thereby minimizing stress induced by the deposition process. Stress reduction by more than an order of magnitude has been demonstrated with LFW ALD technology. This approach has also been shown to lower fluorine content by up to 100x (FIGURE 4) and reduce resistivity by over 30% compared to conventional CVD tungsten.

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Staircase etch

The staircase etch step creates the individual contact pads for each memory cell within the layers. A highly controlled etch process is used to define the size of each contact pad. To reduce the cost associated with lithography and improve productivity, repeated vertical etch and lateral trim etch processes are adopted to form the staircase instead of using numerous lithography steps. For each lithography pass, multiple staircase levels can be created by etching and trimming, as shown in FIGURE 5. The number of stairs that can be formed by this process is determined by the lateral-to-vertical (L/V) etch rate. Improving L/V etch selec- tivity can reduce the number of lithography steps needed.

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Extreme accuracy is required to maintain the stair CD, thus avoiding misaligned contacts. If the CD for a pad is off by a few percent, that error will propagate through subsequent pads defined within the same lithography pass. Current technology can deliver uniform and repeatable stair CD precision of 1% (3-sigma) after more than five L/V trim processes. This is a critical factor for achieving high productivity and being able to scale to higher stacks with more layers economically.

Summary

Traditional planar scaling to increase NAND density is approaching its limits due to lithography and performance challenges. As 3D NAND becomes the mainstream technology, its challenging roadmap poses opportunitiesforcontinuedinnovation. Stress management throughout wafer processing is crucial, and significant innovations in both deposition and etch processes are essential in forming the HAR features that dominate 3D NAND architectures. Finally, reducing variability in every critical step is a must to meet performance, yield, reliability, and cost requirements.

3D NAND completely changes the scaling paradigm by going vertical. No longer limited by lithography capabilities, 3D NAND can achieve greater levels of integrity, perfor- mance, and reliability – while building vertically for higher bit density and a lower cost-per- bit – through relying on advances in deposition and etch processes.

References

1. Y.W. Park, Flash Memory, IEDM short course, 2015

BY ELISABETH BRANDL, THOMAS UHRMANN and MARTIN EIBELHUBER, EV Group, St. Florian, Austria

Fan-out packaging is an established technology for many mobile applications. Whereas early semiconductor packages have been single-chip packages, the continuing trend of expanding the wiring surface to support increased functionality has led to more complex packages, stacked packages, systems inpackageaswellashigh-performancepackages. With this development, fan-out technology is bridging a gap between cost-competitive packaging and high performance. For all aforementioned packages, temporary bonding will be needed, either to enable the thinning of wafers to address the need for smaller form factors, to achieve cost savings on mold materials or to serve as a processing platform for redistribution-layer (RDL) first processes.

Temporary bonding requires both a bonding and debonding process. Determining the right debonding technology can be difficult and confusing as every application from fan-out wafer-level packaging (FoWLP) to power devices has its own requirements in terms of process temperature, mechanical stress and thermal budget, to name just a few considerations. In this article, we will focus on laser debonding, where high- temperature compatible materials are available. We will point out for which applications the laser debond characteristics fit well.

To limit the thermal input associated with debonding, UV lasers are utilized for debonding where several materials from different temporary bonding material suppliers are available. To confine the maintenance effort to a minimum, a diode-pumped solid-state (DPSS) laser is the right choice in combination with beam-shaping optics for high process control and minimum heat input.

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Challenges of temporary bonding for FoWLP

FoWLP has gained significant industry interest in part due to carrier, the requirements of the temporary bonding material in terms of chemical and thermal compat- ibility are high. Certain kinds of polyimides comply with this harsh environment and are also suitable for laser debonding.

By just comparing these two processes, the require- ments differ significantly even though both are FoWLP processes. By looking at the wide variety of semiconductor processes for various applications, it becomes clear that no single debonding process solution is compatible with all semiconductor processes, but rather several solutions are necessary. This is the reason why a variety of debonding processes (temporary bonding is characterized by the debonding technology) have been developed and are still in use today.

Comparison of the mainstream debonding technologies

The most common debonding methods are thermal slide-off debonding, mechanical debonding and UV laser debonding. These three methods are all in high- volume manufacturing and differ strongly in their process compatibility.

Thermal slide-off is a method that employs a thermo-plastic material as an adhesive interlayer between the device and carrier wafer. The debonding method uses the reversible thermal behavior of the thermoplastic material, meaning that at elevated temperatures the material experiences a drop in viscosity, which enables debonding to be accomplished by simply sliding the wafers off of each other. The character- istics of thermal slide-off debonding is bonding and debonding at elevated temperatures, which depending on the thermoplastic material being used can range between 130 and 350°C. Temperature stability depends in large part on mechanical stress, which can be observed due to the thermoplastic’s low viscosity at high temperatures [1].

Mechanical debonding is a method that is highly dependent on the surface properties of the wafers involved as well as the adhesion and cohesion of the temporary bonding material. For most material systems, a mechanical release layer is applied to achieve a controlled debonding mechanism. Key characteristics of mechanical debonding include processing at room temperature and a strong dependence on mechanical stress. Since mechanical debonding needs a low adhesion between the temporary bonding material and the wafer for a successful debond process, it can be tricky to use it for FoWLP applications. This is because the high wafer stress associated with FoWLP processing can lead to spontaneous debonding, even during the thinning process, which in turn can result in a drastic drop in yield [2].

Laser debonding is a technology that has been implemented with several different variations. The debond mechanism depends on the type of laser as well as the temporary bonding adhesive or the specific release layer used for the process. Infrared lasers work on the principle of the photo thermal process, where light is absorbed and transferred into heat, which leads to high temperatures within the bond interface. UV laser debonding typically uses the photo chemical process, where light is absorbed and the energy is used for breaking chemical bonds. Breaking the chemical bonds of a polymer results in the production of fragments of the original polymer. These fragments comprise gases, which increase the pressure within the interface to support the debonding process. For FoWLP applications, this method is a good fit due to the high adhesion of the temporary bonding adhesive to the wafers before the debonding process.

Optimized solution for FoWLP applications

UV lasers are advantageous for FoWLP processing due to their limited thermal input through the debonding process. The carrier wafer must be transparent to the UV laser’s wavelength to ensure efficient use of the laser energy and also ensure a higher lifetime of the carrier wafer. Two main types of UV lasers are available (solid-state laser and excimer laser), with each having several different wavelength options. Choosing a laser with a wavelength larger than 300nm is optimal for several reasons. First, commercially available laser debond materials effectively absorb and therefore debond at wavelengths higher than 300nm. Second, it allows a standard glass wafer to be used as the carrier since glass enables high transmission in this wavelength regime.

Solid-state lasers have the advantage of lower maintenance costs because they do not need halogen gas, which must be replaced on a regular basis. For solid-state lasers, the consumables are very low, and depending on the amount of power used by the laser there are examples of lasers used for laser debonding on a 24/7 basis that have required no laser consumables in the first five years of operation. Additionally, a smaller footprint can also be achieved due to a compact optical setup. Solid-state lasers typically have Gaussian beam profiles, pictured in FIGURE 3.

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UV laser debonding is a threshold process, meaning that debonding occurs above a certain value of radiant exposure. In Figure 3, the area with the blue criss-cross lines indicates the radiant exposure, which is used for the debonding process. The energy that is below or above that value (areas in red in the picture) cannot be used for debonding and is typically trans- ferred into heat, which can lead to carbonization and particle creation. Because of the lack of sufficient energy at the edge of the Gaussian laser beam profile, a certain overlap of the pulses is necessary, which is an additional variable that must be optimized in order to achieve successful debonding without carbonization. Additionally, the excess energy in the beam center can cause carbonization. A Gaussian beam profile is not suitable to limit thermal effects during debonding.

Gaussian beam profiles can be transferred into quasi top hat beam profiles by using a proprietary optical setup for beam shaping. By employing this optical setup, a highly reproducible beam for debonding (whereby the beam shape does not change over time) is achieved with constrained thermal input similar to what is seen in the “top hat” beam profile in FIGURE 4. This gives tighter process control, which in combination with the high pulse repetition rate of this laser type and the ability to scan across the surface of a fixed wafer leads to a well-controlled, high-throughput debonding process. The scanning process is pictured in FIGURE 5 where — in contrast to an excimer laser — the wafer is fixed on a static stage and the laser spot is controlled by a galvo scanner over the wafer. leads to a well-controlled, high-throughput debonding process.

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Screen Shot 2017-07-27 at 9.10.34 AM Screen Shot 2017-07-27 at 9.10.42 AMAs shown in FIGURE 6, a test wafer is used to determine the optimum radiant exposure for debonding. Even with a top hat beam profile, it is important to use a radiant exposure value close to the debonding threshold to minimize heat effects [3]. Small overlaps are necessary nonetheless because the adhesion between the temporary bonding material and the wafers is very high.

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Temporary bonding for future FoWLP

Ultrathin and stacked fan-out packages, also called Package on package (PoP), are already on several industry roadmaps due to their ability to enable higher device densities. However, the need for reconstituted wafers to become even thinner for PoP versus current FoWLP will give rise to more challenges for temporary bonding. For example, the bow of the temporary bonded wafer stack consisting of a molded wafer and a carrier wafer must be minimized to ensure uniform thinning. The maximum total thickness variation (TTV) will also become tighter depending on the final thickness. As for every 3D application, questions regarding interconnects, such as choosing via first or via last, also arises for PoP, where several processes are also available and where no standard process exists that is employed by all fan-out packaging houses.

Summary

UV laser debonding is a suitable method for both chip- first and chip-last/RDL-first FoWLP processes because it offers debonding at room temperature, and because chemically stable materials are available. The UV laser debonding solutions presented in this article combine the advantages of the solid-state laser with low mainte- nance, low consumables costs and high pulse frequencies combined with high spatial control due to the special beam-shaping optics.

Further Readings

1. Critical process parameters and failure analysis for temporary bonded wafer stacks. Karine Abadie, Elisabeth Brandl, Frank Fournel, Pierre Montméa, Wimplinger, Jürgen Burggraf, Thomas Uhrmann, Julian Bravin. Fountain Hills, Arizona: iMaps, 2016. iMaps Device Packaging Conference.

2. Temporary Wafer Carrier Solutions for thin FOWLP and eWLB-based PoP. Jose Campos, André Cardoso, Mariana Pires, Eoin O’Toole, Raquel Pinto, Steffen Kröhnert, Emilie Jolivet, Thomas Uhrmann, Elizabeth Brandl, Jürgen Burggraf, Harald Wiesbauer, Julian Bravin, Markus Wimplinger and Paul Lindner. San Jose, California : SMTA International, 2015. iWLPC (International Wafer Level Packaging Conference).

3. Key Criteria for Successful Integration of Laser Debonding. Elisabeth Brandl, Thomas Uhrmann, Jürgen Burggraf, Martin Eibelhuber, Harald Wiesbauer, Mariana Pires, Philipp Kolmhofer, Matthias Pichler, Julian Bravin, Markus Wimplinger and Paul Lindner. San Jose, California : SMTA Inter- national, 2016. iWLPC.

In its upcoming Mid-Year Update to The McClean Report 2017 (to be released later this week), IC Insights addresses the changing landscape for semiconductor industry mergers and acquisitions.

The historic flood of merger and acquisition agreements that swept through the semiconductor industry in the past two years slowed to a trickle in the first half of 2017, with the combined value of about a dozen transactions announced in 1H17 reaching just $1.4 billion.

In the first halves of 2016 and the record-high M&A year of 2015, the combined value of acquisition agreements in 1H16 and 1H15 totaled $4.6 billion and $72.6 billion, respectively (Figure 1).  Last year, M&A got off to a slow start—compared to the record-breaking pace in 1H15—but several large transactions announced in 3Q16 pushed the 2016 total value in semiconductor acquisitions to nearly $100 billion and within striking distance of the all-time high of $107.3 billion set in 2015.  A few major semiconductor acquisitions were pending or rumored to be in the works during July 2017, but it is unlikely that a 2H17 surge in purchase agreements will bring this year’s M&A total value anywhere close to those of 2016 and 2015.

The big difference between semiconductor M&A activity in 2017 and the prior two years has been the lack of megadeals.  Thus far, only one transaction in 2017 has topped a half billion dollars (MaxLinear’s $687 million cash acquisition of analog and mixed-signal IC supplier Exar announced in March 2017 and completed in May).  There were seven announced acquisitions with values of more than $1 billion in 2016 (three of which were over $10 billion) and 10 in 2015 (four of which were over $10 billion).  IC Insights’ M&A list only covers semiconductor suppliers and excludes acquisitions of software and systems businesses by IC companies (e.g., Intel’s planned $15.3 billion purchase of Mobileye, an Israeli-based provider of digital imaging technology for autonomous vehicles, announced in March 2017).

The 250+ page Mid-Year Update to the 2017 edition of The McClean Report further describes IC Insights’ updated forecasts for the 2017-2021 timeperiod.

Figure 1

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SUNY Polytechnic Institute (SUNY Poly) announced today that Interim Dean of Graduate Studies Dr. Fatemeh (Shadi) Shahedipour-Sandvik and her team of collaborators have been selected to receive $720,000 in federal funding from the U.S. Department of Energy’s Advanced Research Projects Agency-Energy (ARPA-E). The grant will be used to develop more efficient and powerful high-performance power switches at SUNY Poly for power electronics applications, such as for enabling a more efficient energy grid, for example. The research is in partnership with Dr. Woongje Sung of SUNY Poly, the Army Research Lab, Drexel University, and Gyrotron Technology, Inc.

“On behalf of SUNY Poly, I am excited to congratulate Professor Shahedipour-Sandvik as her wide-bandgap-focused research is recognized by the Department of Energy for its potential to improve power devices that are all around us to make our technological world more energy efficient and robust,” said SUNY Poly Interim President Dr. Bahgat Sammakia. “This award highlights SUNY Poly’s unique and advanced research capabilities, as well as its superb faculty who are developing the innovations of tomorrow right now in New York State.”

“This award is a strong indicator of how SUNY Poly’s resources and facilities are enabling the types of research that have the potential to improve power electronics devices which have become ubiquitous, from those utilized to make the power grid more efficient, to those that can improve electric car capabilities,” said SUNY Poly Vice President of Research Dr. Michael Liehr.

“I am proud that the U.S. Department of Energy’s ARPA-E has recognized our leading-edge power electronics-focused research, which holds the incredible potential to drive innovation for practical applications that could lead to worldwide energy savings. Advanced power electronic devices offer significant advances in power density, efficiency, and reduced total lifecycle cost,” said Prof. Shahedipour-Sandvik. “This grant allowing our SUNY Poly team and partners at the Army Research Lab, Drexel University and Gyrotron Technology, Inc. to explore advanced doping and annealing techniques for gallium nitride-based power devices is a testament to how SUNY Poly’s resources and leadership in areas like power electronics can help power the future in exciting and meaningful ways.” 

The SUNY Poly grant is part of a total of $6.9 million in funding that the U.S. Department of Energy ARPA-E is providing through its Power Nitride Doping Innovation Offers Devices Enabling SWITCHES (PNDIODES) program to seven institutions and organizations. With PNDIODES, ARPA-E is tackling a specific challenge in wide-bandgap semiconductor production. Wide-bandgap semiconductors are an important area of research because the materials, such as gallium nitride (GaN), allow for electronic devices to operate at higher temperatures and/or frequencies, for example, than current silicon-based computer chips, which is why technical advances in power electronics promise energy efficiency gains throughout the United States economy. Achieving high power conversion efficiency in these systems, however, requires low-loss power semiconductor switches. Power converters based on GaN could potentially meet the challenge by enabling higher voltage devices with improved efficiency—while also dramatically reducing size and weight of the device, for example.

The PNDIODES-funded research focuses on a process called selective area doping, in which a specific impurity is added to a semiconductor to change its electrical properties and achieve performance characteristics that are useful for electronics. Implemented well, this process can allow for the fabrication of devices at a competitive cost compared to their traditional, silicon-based counterparts. Developing a reliable and usable doping process that can be applied to specific regions of GaN and its alloys is an important obstacle in the fabrication of GaN-based power electronics devices that PNDIODES seeks to overcome. Ultimately, the PNDIODES project teams, including the Shahedipour-Sandvik team and Dr. Sung at SUNY Poly as well as the institution’s partners, will develop new ways to build semiconductors for high performance, high-powered applications like aerospace, electric vehicles, and the grid.

Prof. Shahedipour-Sandkvik team’s research, “Demonstration of PN-junctions by ion implantation techniques for GaN (DOPING-GaN),” will focus on ion implantation as the centerpiece of its approach and use new annealing techniques to develop processes to activate implanted silicon or magnesium in GaN to build p-n junctions, which are used to control the flow of electrons within an integrated circuit. Utilizing a unique technique with a gyrotron beam, a high-power vacuum tube that generates millimeter-wave electromagnetic waves, the team’s research aims to understand the impact of implantation on the microstructural properties of the GaN material and its effects on p-n diode performance.

In addition to this GaN-focused research being conducted by Prof. Shahedipour and her team at SUNY Poly, which also provides hands-on research opportunities for a number of the institution’s students, SUNY Poly and General Electric also lead the New York Power Electronics Manufacturing Consortium (NY-PEMC) with the goal of developing and producing low cost, high performance 6″ silicon carbide (SiC) wafers for power electronics applications. The consortium announced its first successful production of SiC-based patterned wafers in February at the Albany NanoTech Complex’s 150mm SiC line, with production coordinated with SUNY Poly’s Computer Chip Commercialization Center (Quad-C), located at its Utica campus where the SiC-based power chips will be packaged, a process that combines them with a housing that allows for interconnection with an application.

TECHCET CA—the advisory service firm providing electronic materials information—today announced that specialty chemical precursor market for the deposition of dielectrics and metals in integrated circuit (IC) fabrication is forecasted to increase at ~10% CAGR through the year 2021. TECHCET’s proprietary Wafer Forecast Model (WFM) shows that 3D-NAND devices are expected to grow at a rapid pace from 2016 and become one of the top three market segments by 2020. Logic ICs will continue to evolve, from 3D finFET devices to Gate-All-Around Nano-Wires (GAA-NW), enabled by new critical materials and manufacturing processes as detailed in new reports from TECHCET, “Advanced Insulating Dielectric Precursors,” and “ALD/CVD High-k & Metal Precursors.”

Precursors tracked by TECHCET for ALD/CVD of metal and high-k dielectric films on IC wafers include sources of aluminum, cobalt, hafnium, tantalum, titanium, tungsten, and zirconium. The total market for 2017 is now estimated to be US$435M, growing to US$638M in 2021. The top-2 suppliers are estimated to hold more than half of the total available market, with many players competing to supply the next enabling molecule. In particular, cobalt precursor demand is forecasted to reach >$80M in 2021 as foundries transition to below 14nm-node processing. As a potential conflict mineral, TECHCET tracks the sub-suppliers of cobalt.

“Metal precursors have had double-digit growth over an extended period of time, and we expect that to continue as the IC industry transitions to 10nm- and 7nm-node logic and 3D-NAND fabrication, with an average long term CAGR of 11% over 2013 to 2021,” says Dr. Jonas Sundqvist, lead author of the report, senior technology analyst with TECHCET and researcher with Fraunhofer IKTS. “Dielectric precursors growth today is clearly driven by dielectric PEALD deposition in multiple patterning, and by dielectric CVD in 3D-NAND.”

Precursors tracked by TECHCET for ALD/CVD/SOD of advanced dielectric films on IC wafers include multiple sources of silicon. The total market for 2017 is now estimated to be just over US$400M, growing to US$560M in 2021. Current growth over 10% is expected to slow slightly to be in the 8-10% range over 2019-2021. Anticipated near-term developments include transitions from CVD to ALD for several IC fab modules.

Leti today announced that the European FP7 project PLAT4M has now been completed with results that exceeded expectations.

Si photonics has long been expected to bring substantial breakthroughs in very high speed data communications, telecommunications and supercomputing. In addition, it is one of the most promising industrial-production candidates because of its potential for large-scale and low-cost production capability in existing CMOS foundries.

The European Commission launched the 15-member PLAT4M project in 2012 to build a Si photonics supply chain in Europe that would speed industrialization of the technology by enabling its seamless transition to commercial production.

The main objective of PLAT4M was to advance existing silicon photonics research foundries and seamlessly transition to pilot line operation and industrial manufacturing of products based on silicon photonics. The supply chain is based on three different but complementary technology platforms of Leti, STMicroelectronics and imec.

Leti Platform

Leti’s 8,500m2 cleanroom facility includes a 200mm pilot line that enables fabrication of passives, detectors, modulators and integrated lasers with a focus on high-bandwidth devices. The project team developed a new Si-photonic platform based on a 310nm silicon film on top of an 800nm buried oxide (BOX) on a high-resistivity silicon substrate. Since the targeted applications for the project were O-band transceivers and receivers, most of the developed devices are suitable for 1310nm operations.

CEA-LETI has developed 3 PDKs which are dedicated to Multi Project Wafers (MPW) runs on this silicon photonics technology which is now offered via the brokers CMP and Europractice. Moreover, III-V Lab has designed and co-fabricated a state-of-the-art integrated hybrid III-V/Si transmitter using a wafer bonding technique on this platform.

STMicroelectronics Platform 

STMicroelectronics, the first 300mm wafer silicon photonics device manufacturer, is a key solution provider for 100 Gbps transceiver products since 2016. In parallel to its industrial activity, during the PLAT4M project ST developed another silicon photonics technology aimed at generating and nurturing further application specific industrial nodes. This technology platform creates an advanced photonic nanoscale environment, and combines state-of-the-art CMOS foundry tools with the flexibility necessary to support R&D efforts. Strong collaboration with research partners such as CEA LETI and University Paris Sud have been devoted to advanced studies in power consumption management, optical excess loss reduction and higher data-rate transmissions using complex modulation formats, signal multiplexing and higher Baud-rate devices. With R&D exploration that goes as far as core-to-core optical interposers, ST has also evaluated notions of device and circuit footprints toward Large System Integration (LSI).

In the context of PLAT4M, the participants chose a 4×25G transceiver as a Wavelength Division Multiplexing (WDM) data-communication demonstrator to validate both LETI and ST R&D platforms. The device functionalities were evaluated for compatibility with the 100GBase-LR4 standard, implying a signal transmission over 4 channels, spaced by 800 GHz around 1310 nm window, one fiber out and one fiber in.

imec Platform

In the course of the PLAT4M project imec has consolidated and further developed its silicon photonics technology platform ISIPP25G using its 200mm pilot line facilities located in Leuven to support industrial prototyping for various applications and markets. The imec platform component portfolio has been expanded to specific devices for sensing and high power free space applications. Furthermore, imec’s technology is supporting state-of-the-art modulation and detection at 50Gb/s and beyond with a variety of modulator options (GeSi EAM, Si MZM, Si MRM) now offered under its ISIPP50G technology along with both edge and surface fiber coupling technology and a library of O-Band and C-Band high quality passive components.

The technology is accessible through imec’s PDK, which is supported by software tools from several vendors including project partner PhoeniX Software. In collaboration with Mentor, a Siemens business, imec has also explored LVS verifications to reduce design errors and performed litho-friendly design analysis to improve the patterning predictability. Using the imec technology with new processing steps, TNO has demonstrated a multi-channel ring resonator based sensor system. Polytec demonstrated the operation of Multichannel Laser Doppler Vibrometer. THALES has demonstrated an integrated FMCW LiDAR system with 8 switchable output channels, enabling to scanning directions as well as a coherent beam combiner with 16 beams with linear operation up to a maximum input power of 26dBm. The thermal phase-shifter elements achieved a power efficiency of 10mW for a p-phase shift.

Finally, imec has demonstrated new advances in its technology such as a very low loss silicon waveguide technology (~0.6dB/cm for a 220nmx450nm waveguide) applying leading edge CMOS patterning technology developed in its 300mm pilot line with immersion lithography. It has also demonstrated a further reduction of thermal phase-shifter elements down to 4mW for a p-phase shift.

In an Unified Design Environment

The PLAT4M project has led to a qualitative leap of the design flow for silicon photonics, allowing the photonics community to design more complex and more robust circuits. Mentor and PhoeniX Software have worked closely together on an integrated electronics/photonics co-design workflow. This has been accomplished by building on existing tool-sets wherever possible and developing new technologies when required.

The supply chain includes EDA solutions such as Mentor’s Pyxis™ and Calibre®, which were extended to “understand” photonics. Interfaces were developed between these tools and Photonic IC design solution OptoDesigner from PhoeniX Software to create integrated design flows using the best practices from both photonics and electronics design. In addition, process design kit elements were developed for Mentor’s Calibre DRC, Calibre LVS, and Pyxis tools, incorporating new components, added models and fabrication information.

Producing a Packaging toolkit 

Packaging played a key role in the development of the project demonstrators. The skills and processes developed by Aifotec and Tyndall, advanced the development of the Silicon Photonic packaging toolkit. This toolkit establishes standardised packaging processes for optical fibres, active devices, electronic components and thermo-mechanical systems to ensure that PICs can be more easily packaged in a timely and cost-effective way. A design rule document was made available through EuroPractice by Tyndall and also implemented into PDKs for OptoDesigner.

Perspectives 

“The consortium developed advanced technologies and tools by building a coherent design flow, demonstrating manufacturability of elementary devices and process integration, and developing a packaging toolkit,” said Jean-Marc Fedeli, coordinator of the PLAT4M project. “The high level of maturity of the technology offered by these platforms makes them readily accessible to a broad circle of users in a fabless model.”

In its upcoming Mid-Year Update to The McClean Report 2017 (to be released at the end of July), IC Insights forecasts that the 2017 global electronic systems market will grow by only 2% to $1,493 billion while the worldwide semiconductor market is expected to surge by 15% this year to $419.1 billion. Moreover, IC Insights forecasts that the total semiconductor market will exceed $500.0 billion four years from now in 2021.  If the 2017 forecasts come to fruition, the average semiconductor content in an electronic system will reach 28.1%, an all-time record (Figure 1).

Figure 1

Figure 1

Historically, the driving force behind the higher average annual growth rate of the semiconductor industry as compared to the electronic systems market is the increasing value or content of semiconductors used in electronic systems.  With global unit shipments of cellphones (0%), automobiles (2%), and PCs (-2%) forecast to be weak in 2017, the disparity between the slow growth in the electronic systems market and high growth of the semiconductor market is directly due to the increasing content of semiconductors in electronic systems.

While the trend of increasing semiconductor content has been evident for the past 30 years, the big jump in the average semiconductor content in electronic systems in 2017 is expected to be primarily due to the huge surge in DRAM and NAND flash ASPs and below average electronic system sales growth this year. After dipping slightly to 28.6% in 2020, the semiconductor content figure is expected to climb to 28.9% in 2021, an average yearly gain over the 2016-2021 timeperiod of about 0.8 percentage points.

Of course, the trend of increasingly higher semiconductor value in electronic systems has a limit. Extrapolating an annual increase in the percent semiconductor figure indefinitely would, at some point in the future, result in the semiconductor content of an electronic system reaching 100%.  Whatever the ultimate ceiling is, once it is reached, the average annual growth for the semiconductor industry will closely track that of the electronic systems market (i.e., about 4% per year).  In IC Insights’ opinion, the “ceiling” is at least 30% but will not be reached within the forecast period.

The 250+ page Mid-Year Update to the 2017 edition of The McClean Report further describes IC Insights’ IC market forecast data for 2017-2021.

By Pete Singer

Luc Van den Hove, president and CEO of imec

Luc Van den Hove, president and CEO of imec

Speaking at imec’s International Technology Forum USA yesterday afternoon at the Marriott Marquis, Luc Van den Hove, president and CEO of imec, provided a glimpse of society’s future and explained how semiconductor technology will play a key role. From everything the IoT to early diagnosis of cancer through cell sorters, liquid biopsies and high-performance sequencing, technology will enable “endless complexity increase,” he said.

Other developments, almost all of which are being worked on at imec, include self-learning neuromorphic chips, brain implants, artificial intelligence, 5G, IoT and sensors, augmented and virtual reality, high resolution (5000 ppi) OLED displays, EOG based eye tracking and haptic feedback devices. He also acknowledged the critical importance of security issues, but suggested a solution. He noted that each chip has its own fingerprint due to nanoscale variability. That’s been a problem for the industry but we could “turn this limitation into an advantage,” he said, with an approach called PUFs — Physical Unclonable Functions (Figure 1).

Figure 1. Nanoscale variability has been a problem for the industry but we could be turned into an advantage with PUFs -- Physical Unclonable Functions.

Figure 1. Nanoscale variability has been a problem for the industry but we could be turned into an advantage with PUFs — Physical Unclonable Functions.

At the forum, imec also announced that its researchers, in collaboration with scientists from KU Leuven in Belgium and Pisa University in Italy, have performed the first material-device-circuit level co-optimization of field-effect transistors (FETs) based on 2D materials for high-performance logic applications scaled beyond the 10nm technology node. Imec also presented novel designs that would allow using mono-layer 2D materials to enable Moore’s law even below 5nm gate length. Additionally, imec announced that it demonstrated an electrically functional 5nm solution for Back-End-of-Line interconnects.

FETs based on 2D materials

2D materials, a family of materials that form two-dimensional crystals, may be used to create the ultimate transistor with a channel thickness down to the level of single atoms and gate length of few nanometers. A key driver that allowed the industry to follow Moore’s Law and continue producing ever more powerful chips was the continued scaling of the gate length. To counter the resulting negative short-channel effects, chip manufacturers have already moved from planar transistors to FinFETs. They are now introducing other transistor architectures such as nanowire FETs. The work reported by imec looks further, replacing the transistor channel material, with 2D materials as some of the prime candidates.

Figure 2. 2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations.

Figure 2. 2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations.

In a paper published in Scientific Reports, the imec scientists and their colleagues presented guidelines on how to choose materials, design the devices and optimize performance to arrive at circuits that meet the requirements for sub-10nm high-performance logic chips. Their findings demonstrate the need to use 2D materials with anisotropicity and a smaller effective mass in the transport direction. Using one such material, monolayer black-phosphorus, the researchers presented novel device designs that pave the way to even further extend Moore’s law into the sub-5nm gate length. These designs reveal that for sub-5nm gate lengths, 2D electrostatics arising from gate stack design become more of a challenge than direct source-to-drain tunneling. These results are very encouraging, because in the case of 3D semiconductors, such as Si, scaling gate length so aggressively is practically impossible.

“2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations. With advancing R&D, we see opportunities emerging in domains such as photonics, optoelectronics, (bio)sensing, energy storage, photovoltaics, and also transistor scaling. Many of these concepts have already been demonstrated in the labs,” says Iuliana Radu, distinguished member of technical staff at imec. “Our latest results presented in Scientific Reports, show how 2D materials could be used to scale FETs for very advanced technology nodes.”

5nm Solution for BEOL

The announced electrically functional solution for 5nm back-end-of-line (BEOL) is a full dual-damascene module in combination with multi-patterning and multi-blocking. Scaling boosters and aggressive design rules pave the way to even smaller dimensions.

As R&D progresses towards the 5nm technology node, the tiny Cu wiring schemes in the chips’ BEOL are becoming more complex and compact. Shrinking the dimensions also reduces the wires cross-sectional area, driving up the resistance-capacitance product (RC) of the interconnect systems and thus increasing signal delay. To overcome the RC delay challenge and enable further improvements in interconnect performance, imec explores new materials, process modules and design solutions for future chip generations.

One viable option is to extend the Cu-based dual-damascene technology – the current workhorse process flow for interconnects – into the next technology nodes. Imec has demonstrated that the 5nm BEOL can be realized with a full dual-damascene module using multi-patterning solutions. With this flow, trenches are created with critical dimensions of 12nm at 16nm. Metal-cuts (or blocks) perpendicular to the trenches are added in order to create electrically functional lines and then the trenches are filled with metal. Area scaling is further pushed through the introduction of fully self-aligned vias. Moreover, aggressive design rules are explored to better control the variability of the metal tip-to-tips (T2Ts).

Figure 3. Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

Figure 3. Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

Beyond 5nm, imec is exploring alternative metals that can potentially replace Cu as a conductor. Among the candidates identified, low-resistive Ruthenium (Ru) demonstrated great promise. The imec team has realized Ru nanowires in scaled dimensions, with 58nm2 cross-sectional area, exhibiting a low resistivity, robust wafer-level reliability, and oxidation resistance – eliminating the need for a diffusion barrier.

“The emergence of RC delay issues started several technology nodes ago, and has become increasingly more challenging at each node. Through innovations in materials and process schemes, new BEOL architectures and system/technology co-optimization, we can overcome this challenge as far as the 5nm node”, said Zsolt Tokei, imec’s director of the nano-interconnect program. “Imec and its partners have shown attainable options for high density area scaled logic blocks for future nodes, which will drive the supplier community for future needs.”

For the longer term, imec is investigating different options including but not limited to alternative metals, insertion of self-assembled monolayers or alternative signaling techniques such as low-energy spin-wave propagation in magnetic waveguides, exploiting the electron’s spin to transport the signal. For example, the researchers have experimentally shown that spin waves can travel over several micrometers, the distance required by short and medium interconnects in equivalent spintronic circuits.

Worldwide industrial semiconductor revenues grew by 3.8 percent year-over-year in 2016, to $43.5 billion, according to the latest analysis from business information provider IHS Markit (Nasdaq: INFO).

Industrial electronics equipment demand was broad-based, with continued growth in commercial and military avionics, digital signage, network video surveillance, HVAC, smart meters, traction, PV inverters, LED lighting and various medical electronics such as cardiac equipment, hearing aids and imaging systems, IHS Markit said.

The U.S. economy continued to boost industrial spending while improved economic conditions in Europe and large emerging countries like China, India and Brazil toward the end of 2016 that propelled growth. These economic conditions are expected to continue thorough 2017, according to the IHS Markit analysis.

Top 20 company ranks: Global industrial semiconductor market share

Texas Instruments (TI) maintained its position as the largest industrial semiconductor supplier in 2016 followed by Intel, STMicroelectronics, Infineon Technologies and Analog Devices. Intel surged to second place, swapping spots with Infineon, which dropped to fourth. The Intel IoT group’s double-digit revenue growth is attributed to strength in factory automation, video surveillance and medical segments.

“Toshiba, ON Semiconductor and Microchip Technology climbed into the top 10 industrial semiconductor supplier ranks in 2016,” said Robbie Galoso, principal analyst, industrial semiconductors for IHS Markit. Toshiba’s industrial market share rank jumped to number six, according to survey feedback. Toshiba’s industrial electronics revenue grew from $1.1 billion in 2015 to $1.4 billion in 2016—a 30.5 percent bounce driven by discretes, microcomponent integrated circuits (ICs), memory and logic IC solutions in manufacturing and process automation, power and energy as well as security and video surveillance.

Mergers and acquisitions make an impact

The semiconductor industry had another cycle of merger and acquisition in 2016 that affected the competitive landscape. The combined ON Semiconductor – Fairchild organization generated $1.3 billion in 2016 industrial revenues, catapulting the consolidated company into seventh place. The acquisition of Fairchild allowed On Semiconductor to leapfrog to the top ranks of the power discrete market, forecast to be one of the higher growth markets over the next five years, IHS Markit said

On Semiconductor has been a relatively small player in the power discrete segment; with the Fairchild acquisition, it now has the scale and product portfolio to compete effectively with the combined Infineon International Rectifier. On Semiconductor’s 2016 revenue grew nearly 60 percent, largely driven by analog and discretes in the manufacturing and process automation and the power and energy sectors, both of which were sizeable segments for Fairchild.

The Microchip Technology – Atmel merger generated $1.2 billion in revenues in 2016, propelling the combined company into 10th place. The acquisition of leading microcontroller supplier, Atmel, positioned Microchip as the third-ranked supplier of microcomponent ICs in the industrial market, after Intel and TI. The combination of Microchip and Atmel created an MCU powerhouse, allowing it to compete effectively against the combined NXP Freescale. Microchip Technology’s 2016 revenue growth of 53 percent was driven by microcomponent ICs in manufacturing and process automation, Atmel’s bread and butter. Toshiba, Micron and ON Semiconductor displaced Nichia, Renesas and Xilinx in the top 10 rankings.

China’s massive investments in light-emitting diode (LED) manufacturing capacity propelled Chinese firm MLS into the 2016 top 20 industrial semiconductor supplier ranks, displacing Maxim. “MLS posted revenue growth of 27 percent, to $640 million, building its share against competition including top-20 firms Nichia, Osram and Cree,” added Galoso.

Strategic acquisitions will continue to play a major role in shaping the overall semiconductor market rankings in key industrial semiconductor segments. IHS Markit expects Analog Devices to increase its lead in 2017 market shares among the top semiconductor suppliers, due to an acquisition of Linear Technology. A joint Analog Devices – Linear Technology would battle for the number four spot and impressive gains in test and measurement, manufacturing and process automation as well as medical electronics.  Among the top 10 semiconductor suppliers, eight companies achieved growth in 2016, with two companies posting double-digit growth due to mergers.

industrial semi growth

Industrial semiconductor key growth drivers

Optical semiconductors delivered solid performance, driven by continued strength in the LED lighting market. IHS Markit expects the LED segment to grow from $9.4 billion in 2016 to $14.3 billion in 2021. With many countries phasing out incandescent bulbs, mass adoption of energy-efficient LED lighting solutions will continue to gain traction as prices for LED lamps fall to affordable levels for average-income households. Discrete power transistors, thyristors, rectifiers and power diodes are expected grow from $5.7 billion in 2015 to $8 billion in 2021 due to policy shifts toward energy efficiency in the factory automation market. IHS Markit projects that the microcontrollers (MCUs) segment  will grow robustly in the long term, expanding from $4.4 billion in 2016 to $7 billion in 2021, attributing this growth to both shipments and average selling price driven by system level cost savings provided by MCUs through advances in power efficiency and integration integrated features supporting connectivity, security, sensors and HMI.

Each year at SEMICON West, the “Best of West” awards are presented by Solid State Technology and SEMI. More than 26,000 professionals from the electronics manufacturing supply chain attend SEMICON West and the co-located Intersolar. The “Best of West” award was established to recognize new products moving the industry forward with technological developments in the electronics supply chain.

Selected from over 600 exhibitors, SEMI announced today that the following Best of West 2017 Finalists will be displaying their products on the show floor at Moscone Center from July 11-13:

  • Mentor, a Siemens Business: Tessent® Cell-Aware Diagnosis – With FinFETs in high volume, finding systematic yield issues at the transistor level is important. The Tessent Cell-Aware Diagnosis technology significantly improves diagnosis of defects beyond the inter-connect and inside the logic cells. (Process Control, Metrology and Test Category; North Hall Booth #6661)
  • Microtronic Inc.: EAGLEview 5 Macro Defect Management Platform – EagleView 5 is the new, yield-enhancing, breakthrough macro defect inspection platform that was developed – and deployed in production — through collaboration with several leading device manufacturers who wanted to standardize and unify wafer defect management throughout their fab. Innovations include: dramatically improved defect detection; level-specific sorting; and integration with manual microscopes. (Process Control, Metrology and Test Category; North Hall Booth #5467)
  • SPTS Technologies Ltd: SentinelTM End-Point Detection System for Plasma Dicing after Grind – The Sentinel™ End-Point Detection System improves the control of plasma dicing processes and protects taped wafers for improved yields.  In addition to signaling exposure of the tape, Sentinel™ also detects loss of active cooling during the process to enable intervention to prevent yield loss. (Process Control, Metrology and Test Category; West Hall Booth #7617)
  • TEL: Stratus P500 – The Stratus P500 system electroplates panel substrates with wafer level processing precision.  As redistribution layers (RDL) reduce to widths below 10 µm line/space, and package sizes increase, conventional plating systems are challenged to meet system-on-package requirements. The P500 makes panel scale fine line RDL and feature filling applications possible. (Assembly/Packaging Solutions Category; North Hall Booth #6168)

Congratulations to each of the Finalists. The Best of West Award winner will be announced during SEMICON West (www.semiconwest.org) on Wednesday, July 12, 2017.