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Industry experts answer questions about the new standard in a virtual roundtable.

In recent years, energy consumption has decreased due to several innovations that have helped to improve the energy efficiency of process tools and sub-fab equipment, but an increase in the number of processes and the growing complexity of processing at the current node has resulted in a spike in energy consumption in the fab. Approximately 43% of the energy consumed in the fab is due to the processing equipment and, of this, 20% is vacuum and abatement (8% overall).

A new standard from SEMI, E175, defines energy saving modes, which combined with the EtherCAT signaling standard, can help fabs save energy and other gas/utility costs when the tool is not processing and with no impact on subsequent wafer processing.

EtherCAT, based on industrial Ethernet, provides high- speed control and monitoring. It is the communication standard of choice for the latest semiconductor tool controllers to connect to sensors and actuators around the tool, including vacuum and abatement systems.

SEMI E175 defines how process tools communicate with sub-fab equipment, such as vacuum pumps and gas abatement systems, to reduce utility consumption at times when wafers are not being processed by the tool, and returning to full performance when the tool is again required to process wafers. It builds on SEMI E167, which defines communication between the fab host/ WIP controller and the process tools for the purpose of utility saving.

Collaboration between the E175 and EtherCAT groups has seen a harmonization of the communication standards to provide co-ordinated energy saving across devices in the fab.
We invited experts in this area to answer a few questions in a virtual roundtable. The participants are:

• GERALD SHELLEY, Senior Product Manager Communication and Control at Edwards, and the EtherCAT Chair Abatement / Roughing pump working groups, E175 task force.

• MIKE CZERNIAK, Environmental Solutions Business Development Manager at Edwardsm Co-Chair of SEMI International Standards E167 & E175, and campaigner for energy saving

• GINO CRISPIERI, Applied Materials – Past Co-chair of E175 (originally SEMATECH/ISMI, then independent consultant, prior to Applied Materials)

• MARTIN ROSTAN, Executive Director, EtherCAT Technology Group

Q: Please explain what drove the standards work on energy saving and the achievements to date.

SHELLEY: There is increased pressure on the industry to reduce energy and utility saving from both a cost and environmental standpoint. Subfab equipment is a major consumer of utilities, which is wasted when a tool is not in use. Different manufacturers have implemented energy saving solutions, with minimal direct connection to the tool. However, direct tool connection has emerged as the best way to maximize saving without any risk to wafer processing.

CZERNIAK: This work originated in the ISMI part of SEMATECH as a follow-on to generic work aimed at reducing the overall utilities footprint of modern fabs. In response to this and requests from customers, Edwards developed vacuum pumps and gas abatement systems that had energy-saving functionality. However, it soon became clear that the limitation to implementing such savings was the absence of standardised signalling between the process tool and sub-fab equipment.

CRISPIERI: A SEMATECH project around 2009 started to look into opportunities for saving energy in the semiconductor factories. At that time, suppliers of pumps and abatement systems already had started initiatives to provide their own solutions to the initiative. Since that time, the industry has adopted two new standards: SEMI E167 Specification for Equipment Energy Saving Mode Communication (between factory and semicon- ductor equipment) and SEMI E175 Specification for Subsystem Energy Saving Mode Communication (between semiconductor equipment and subsystems).

Q: Please describe how the energy saving task force was born and why you decided to get involved.

CRISPIERI: Back in 2009 while working for SEMATECH in Austin, Texas, prior to SEMATECH’s move the New York, Thomas Huang an assignee for GlobalFoundries to the EHS Program approached and asked me if I would be interested in helping him drive a standard for equipment suppliers to enable their equipment to save energy during idle times. Because of my previous experience working with equipment suppliers and developing standards for equipment and factory communication, I accepted to chair a task force to drive the equipment supplier’s new capability requirement into a standard. At first, we thought it would be an easy task and that everyone would jump to help create and approve the standard in a short amount of time because of its benefits. A two phase approach was defined to drive the standardization process and engage semiconductor and sub-fab equipment suppliers accordingly. It took almost three years to complete the Phase I (2013) and another three to complete the Phase II (2016) standards.

SHELLEY: The task force was an extension of E167 which previously defined the communication into the tool from the supervisory systems, however to achieve maximum benefit signalling to tool subsystems was key and the E175 task force was the result.

CZERNIAK: Following-on from the above, the ISMI working group became a SEMI Standards Task Force and began work at developing a standard, initially for Host to process tool (E167) and then from tool to sub-fab (E175), which I was co-chair for to ensure continuity and clear the signalling “roadblock”.

Q: How have suppliers collaborated on E175?

CRISPIERI: Compared with the suppliers who partic- ipated in SEMI E167 development, the suppliers involved in the development and approval of SEMI E175 were more committed to make it happen and helped drive the standardization process to conclusion much more efficiently. Edwards, AMAT, TEL, Hitachi- Kokusai and DAS-Europe regularly participated and provided inputs to standardize behavior and require- ments for their own equipment. We run into some difficulty getting aligned with other standard activities that were driven by SEMI’s EHS Committee because their changes affected our standardization process. I must note that the overall participation was excellent in particular from Edwards Vacuum and AMAT.

ROSTAN: Within the ETG Semiconductor Technical Working Group individual task groups already had multiple suppliers collaborating on the detail of the EtherCAT profiles for all devices, with technical support from the EtherCAT Technical Group. We were fortunate to have a delegate from Edwards in both the Semi E175 Task Force and key EtherCAT Task Groups to informally broker agreement between the teams.

SHELLEY: The suppliers were able to use their collective experience to work through a number of options to find the optimum way of controlling subfab equipment, tackling variability in wakeup time and control architec- tures between device types and equipment technology.

CZERNIAK: Suppliers, automation providers, tool OEMs and end-users have all collaborated to help develop a standard that works for everyone and aligns with earlier standards like S23.

Q: How was the EtherCAT collaboration beneficial to E175?

SHELLEY: By sharing information and understanding in real time we demonstrated the E175 concept is achievable using the favored protocol for new tool platforms and defined how it would be implemented. We co-operated to take both these standards to alignment in one simul- taneous step, saving considerable committee time on both sides that would have been necessary to resolve any divergence of the detail.

ROSTAN: By devising the implementation of E175 in parallel the EtherCAT Task Groups involved were able to feedback detailed technical proposals and show the E175 standard could be implemented relatively easily within the existing EtherCAT standards.

CRISPIERI: Participation and collaboration from the EtherCAT Working Group was critical to accelerate the implementation and adoption of the standard. Dry Contacts and EtherCAT communication protocol messages were added to two Related Information sections and included in the SEMI E175 standard at the time of its publication.

CZERNIAK: This enables a “richer” signalling environment than simple dry contacts (which are also supported) that enables even greater utility savings to be made.

Q: How has EtherCAT been able to support the require- ments of the tool and Semi E175?

CZERNIACK: By providing timing information; the longer the time the tool is inactive, the greater the savings possible.

ROSTAN: As the control network of choice for the latest semiconductor tools, EtherCAT has been ideally placed to support enhancements, such as the energy saving connectivity increasingly being requested by the fabs. In particular, it was good to see the Pump and Abatement Task Groups of the existing Semiconductor Technical Working Group formulate an E175 compliant solution within the timescales of the second release of the EtherCAT semiconductor device profiles. The EtherCAT Technology Group was also more than happy to support the publication of extracts of the EtherCAT standards being used as protocol examples in the Imple- mentation guidelines of the Semi E175 document.

SHELLEY: EtherCAT has the fast / deterministic connec- tivity and proven integration with tool controllers that allows E175 functionality to be easily added without any loss of performance. By including the requirements of Semi E175 in the EtherCAT standards, both equipment suppliers and tool vendors can establish energy saving communication quickly and easily.

CRISPIERI: The coordination between EtherCAT Working Group and the SEMI ESEC task force group was conducted by Mr. Gerald Shelley from Edwards Vacuum. With his help and leadership, we reached effortlessly agreement and acceptance for the required messages, parameters and values into the EtherCAT respective Pump and Abatement Profile documents. Havingworking usage scenarios and support from the EtherCAT Working Group has been invaluable.

Q: Why is energy saving important to the industry?

ROSTAN: In the industrial world, EtherCAT users are increasingly using our communication and control technologies to drive down energy consumption. The semiconductor industry operates in parts of the world where energy is a limited and expensive resource, whilst the latest wafer processing requires more power. The manufacturers are therefore in great need for energy saving opportunities, such as when the tool subsystems are not in use.

SHELLEY: The fabs are being squeezed by an increase in the complexity and number of processes involved in manufacturing a wafer, driving consumption up and increasing scarcity of energy supply. This is further compli- cated with associated cost and government pressure to “keep the lights on”.

CRISPIERI: It is not hard to see why is so important for device makers or the semiconductor manufacturing industry to adopt and require energy conservation capabilities in their factories. Energy consumed by many equipment components and support systems, such as pumps and abatement systems, never stop from running even when the equipment is idle and waiting for product to be delivered for processing. These components and support systems can save millions of dollars each year if their power consumption is reduced. This energy consumption reduction extends their life cycle thus reducing costs of maintenance and parts replacement. Any effort to reduce energy consumption helps lower costs and adds gains to not only the manufacturer but to those who have to generate the energy for consumption.

CZERNIACK: Cost reduction is always important, but electrical supply is limited in some areas.

TechInsights analysts share their view on where technology is going, how it’s changing, and what new developments are emerging.

BY STACEY WEGNER, JEONGDONG CHOE and RAY FONTAINE, TechInsights, Ottawa, ON

In 2016, wearables were extremely interesting mainly because there was so much uncertainty around whether or not the market will be viable. The year saw some truly low-cost smart and fitness devices, and some market surprises like Fitbit buying Pebble. The Apple Watch 2 was an improvement over the Watch 1. However, the Huawei watch is remarkably designed with a nice round face, and functional, making the decision on which smart- watch to buy difficult.

While wearables will remain intriguing, even more interesting to watch is the wearables market. Hearables can be as simple as ear buds and basic hearing aids or as complex as devices that correct and amplify sound, sync with wireless devices for virtually any application, and even measure biometric outputs. That’s just the beginning. New sensors being packed into small devices are bringing us devices with nearly 30 sensors per device.

Our recent AirPod teardown (FIGURES 1 and 2) sheds even more light on what’s happening in this area. The W1 chip found in the Beats Studio wireless headphone has the package mark 343S00131. Meanwhile, the W1 chip torn down from the Apple AirPods has the package mark 343S00130. They have a slight difference in the last digit in the package marks. TechInsights has confirmed that both 343S00131 and 343S00130 have the same die. This die measures 4.42 mm x 3.23 mm = 14.3 mm2 . TechInsights has been tracking Internet of Things (IoT) SoCs for over a year and our observations indicate that this new W1 SoC is very competitively placed when comparing its die size and connectivity specification of Bluetooth 4.2 or greater.

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Another extremely interesting technology to watch is the rise of intelligent personal or family assistants. This market started with the introduction of the popular Alexa and Echo. Sony may release their assistant this year with more sure to follow. As far as timing, we will have to wait and see. One issue that needs to be addressed is data collection and usage vs. persona privacy in a manner similar to Vizio’s issues with the FTC. In addition, more changes are coming for artificial intelligence or assistants on mobile devices with Samsung announcing Bixby ahead of its G8 launch.
Of course there are a slew of IoT technologies to watch like the acceptance of Zigbee, Z-Wave, LoRa, and Bluetooth 5.0, all of which seem to be vying aggressively for consumer IoT/connected home market. Rumors are gaining strength around how the Samsung S8 will have Bluetooth 5, which could mean a new WiFi modem, from whom we are not certain. Samsung and Wisol have been aligned for a while, but it would be a big statement to see a Samsung/Wisol WiFi/ Bluetooth modem design supporting a new technology like Bluetooth 5.0 in a flagship phone. Based on our knowledge of the Bluetooth Special Interest Group, we don’t believe that Bluetooth 5.0 has to be declared for a product. If fact, it would almost seem as if the SiG is asking OEMs to not make a declaration of the Bluetooth 5 in the device.

Image sensors

2016 was an exciting year for smartphone cameras, which should be considered as one of the biggest hardware differentiators between mobile handset platforms. Dual camera systems have reached the mainstream and are forecasted to drive growth for CMOS image sensor IDMs and foundries. Samsung introduced full chip Dual Pixels implemented in chips from its team and from Sony. Each Dual Pixel photosite is available as an autofocus (AF) point, and this complements traditional contrast AF methods and the emerging laser + time-of-flight (ToF) systems.

In 2017, ToF is expected to be a key differentiator in mobile platforms, both for AF and for new 3D/ranging functionality. Sony has introduced first generation direct bond interconnect (DBI) as a through silicon via (TSV) replacement and we expect tighter pitch DBI and eventually full chip active DBI going forward. On the image signal processor (ISP) side we are seeing a big push to lower nodes (28 nm ISPs are the state-of-the-art for high end stacked CIS chips). The flexibility offered by chip stacking should lead to new and disruptive partnerships between CMOS image sensor specialists and mixed signal advanced CMOS specialists. Finally, we expect new entrants to the digital imaging and sensing landscape. Machine vision, robotics, ranging, surveillance/security, and automotive vision and sensing applications are all positioned for growth due to enabling functionality and continued performance gains. It’s certainly an exciting time for all involved in designing and fabricating imaging and sensing pixel arrays and camera systems!

Memory devices

Last year virtually every vendor, device manufacturers, R&D engineer and market analyst we talked to was focused on DRAM and NAND technology roadmaps. We still talk to clients today who are focused on the future of these technologies. Today, 32L and 48L 3D NAND products are common and all the NAND players are eager to develop the next generation 3D NAND products such as 64L and 128L or even more (FIGURE 3). TechInsights has been analyzing and comparing these devices regularly. We found that 3D NAND is a kind of revolution for memory devices, and because of it, big data or data center, SSD/SD and related technologies like controller, interface and board/package, are moving forward. In addition, they may be able to keep pace for more than the next five years until any new emerging memory devices are commercialized.

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The memory products/technologies we are anticipating this year are 3D NAND technology with 64L, 72L and 128L and 1x and 1y nm DRAM technology. As always, 3D NAND technology is competitive with emerging memory including X-point memory regarding on the performance, reliability, retention, process integration and cost since X-point memory and crossbar devices such as ReRAM, CBRAM, MRAM and PCRAM are likely not cost effective (bit cost).

While Samsung has already revealed 1x nm DRAM, in 2017, we believe there will be another big area of competition in DRAM technology (FIGURE 4). DRAM cell has 1T1C architecture with a cylindrical capacitor, however, nowadays, the cell capacitance cannot meet the capacitance spec (20fF/ cell). Commercial DRAM products such as Samsung’s 18nm DRAM have just about 12fF/cell. With smaller cell nodes, it is absolutely harder to get the sufficient cell capacitance. Nevertheless, Samsung and SK-hynix are confident in developing n+1 (1y nm) and n+2 (1z nm). We anticipate that in 2017, every DRAM maker will be developing 1x and 1y nm commercial DRAM products. How these rollout and perform remains to be seen.

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Finally, we are anticipating a commercial product using X-point memory from Micron and Intel.

Conclusion

These represent some of the major technologies we have our eye on this year, although we fully anticipate seeing new technologies we can only imagine today emerge. After all, change is truly the only constant in our world. As our analysts continue to examine and reveal the innovations other can’t inside advanced technology, we will continue to share our findings on the technologies noted above, how they are used, and how they will be changed by the next discovery or invention.

A new type of scattered light measurement method will be presented, capable of measuring the full wafer surface of a 300 mm wafer in less than 30 seconds. Besides the roughness, the sensor simultaneously measures warpage, waviness and defects.

BY R. BRODMANN, B. BRODMANN, K. KONOVALENKO, and C. WIEHR, OptoSurf GmbH CHING-HSIEN HUANG, YA-LENG CHEN, Amkor Technology, Inc.

The trend towards very small and high-density electronics requires advanced processes to meet the specifications of thickness and thermal properties of the devices. This means that the processed silicon wafers have to be thinned from their original thickness of more than 700 μm down to 50 μm or less. The most common and relative low cost thinning method is back grinding by means of mechanical removal of the residual silicon. The wafer is fixed on a porous vacuum chuck with the IC (integrated circuit) side down. The rotation axis of the grinding wheel is positioned off-axis to the rotation axis of the wafer (distance is the radius of the wafer). The chuck has a slightly conical shape which deforms the wafer with a very little tilt to ensure that the grinding wheel only contacts half of the wafer during the grinding process. Due to the rotation of the chuck and simultaneously rotation of the grinding wheel a typical spiral pattern of scratches on the wafer surface is generated.

Depending on the grit size of the grinding wheel and the machining parameters as rotation speed and feed rate, this mechanical impact is responsible for the roughness, stress and induced subsurface damage. Therefore, a modern wafer grinding machine begins with a coarse grinding wheel to get a fast removal of the silicon and at the end follows a fine grinding process step with small grit size grinding wheel. This final process is absolute necessary when thinning down to 50 μm in order to minimize subsurface damage and stress. The roughness of the surface should be often in the range of Ra <10 nm or even 1 nm which is a challenge for mechanical grinding machines. Is the roughness too high or not uniformly distributed on the wafer surface, the later process steps as wire bonding, flip chip assembling, molding and testing can damage the thin chip through breakage. Besides a low surface roughness, the fracture strength of the die after dicing also depends on the orientation of the grinding marks. The correlation of die strength with roughness and surface texture is described in Ref. 1 and 2.

The interaction of the grinding wheel with its large number of single cutting edges, undergoing non-uniform wear, and the silicon surface, in particular when applying the fine grinding procedure is a rather complex process. Therefore, it is not possible to predict the quality of the entire wafer surface after grinding by means of a few small area roughness measurements with an AFM, a WLI or CFM, which is the standard today. Typically, the assessed area of one single measurement is 20 μm x 20 μm in case of an AFM and 160 μm x 160 μm with a CFM or WLI. Each measurement takes about 20 s-30 s and requires anti-vibration equipment to avoid influence from environmental mechanical noise.

In order to get information of the entire wafer surface, much faster and more robust measurement techniques are necessary. Scattered light measurement is the only method which can achieve these requirements. In the present paper, results of a new measurement machine (WaferMaster 300) are discussed which uses a scattered light sensor [4] to measure the roughness of a full 300 mm wafer surface in less than 30 s. Due to a special design of the sensor the WaferMaster can measure in addition the warpage, waviness and defects.

Measurement principle and surface characterization

Using scattered light to measure surface defects and roughness is already well known for CMP polished bare wafers, pattered wafer, hard disks, mirror surfaces and high quality fine machined automotive parts. The new type of scattered light sensor to measure back- grinding wafer is shown in FIGURE 1.

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The light source (1) illuminates nearly perpendicular the wafer surface with a 670 nm red LED spot of 0.9 mm spot size (2). This is the standard modus for fast measurement with medium lateral resolution. For high lateral resolution, another spot with 0.03 mm diameter from a laser source with the same wavelength can be switched on. The optics (3) collect the scattered light in an angle range of 32° and guides it to the linear detector (4). In contrast to other scattered light sensors this sensor measures the specular light (0°-part of the surface) together with the scattered light created by the microstructures of the surface. The advantage of this set-up is the capability to use the center of gravity of the scattered light distribution (5) as signal of the local geometrical deformation of the surface. Knowing the local slope angle of the surface and measuring continuously the surface in equal distance (created by an encoder signal) the local height can be calculated and, by integration of all angles, the entire profile of the surface.

The chuck with the wafer (6) rotates continuously during the measurement and the sensor moves linearly from the wafer edge to the center. Subsequently the sensor measures the entire wafer surface and assesses on a 300 mm wafer in the standard modus (0.9 mm spot) about 60.000 single roughness measurements in 30 s. Very important is an additional rotation (7) of the sensor because the linear detector should be always orien- tated normal to the grinding marks to get the maximum roughness value. As roughness parameter, the variance of the scattered light distribution Aq is calculated (FIGURE 2). ψi are the single scattered angles, M is the center of gravity and p(ψ) is the distribution curve.

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The advantage of Aq is the close relation with the profile slope parameter Rdq which describes surface friction very well. To follow the Semi standards in which the mean roughness Ra is established as roughness value, the Aq parameter was correlated with Ra by comparison measure- ments of different wafers with a confocal micro- scope. Due to the stochastically property of the amplitude distribution of the ground surface there is a rather good correlation between Aq and Ra even when using different grit size of the grinding wheel. But it should be taken into account that Aq is a more versatile parameter, because it reacts on both the vertical and lateral structures of a profile whereas Ra only measures the mean vertical height. This property of Aq could be interesting for characterizing die strength and should be investigated in more details in the future. In FIGURE 3 the measured correlation is shown. Several wafers were in- vestigated on different areas and ground with different grit sizes from #2000 to #8000. In addition, a CMP polished wafer with a Ra value <1nm was measured to check the accuracy of the system. In order to calculate the Ra-value the fitted correlation equation is used in the WaferMaster machine.

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As already mentioned, the scattered light sensor has a second evaluation channel to measure warpage and waviness by means of slope angle analysis. As shown in Fig. 2,the measurement beam is deflected under 2x the local slope angle θ. Therefore, the scattered light distribution is shifted on the linear detector by the angle value M. θ can be measured by using the first statistical moment of the scattered light distribution curve. Knowing the step size ∆x from an encoder and the focal length of the optics, the local height ∆y can be calculated and by sum up, the height profile can be generated.

Results

In FIGURE 4 the roughness results of 3 wafers are shown, each 300 mm size. They all were ground with the same grinding wheel (grit size #4000), but using different grinding machines. In total 40.000 measurements were taken in 25s with the 0.9mm spot. Besidesthe difference in the mean roughness value, it demonstrates in particular that the machines did leave its own characteristic pattern. The interpretation might be interesting to analyze in detail the grinding parameters as feed rate, chuck geometry, rotation speed, and others.

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An example of the simultaneous measurement of roughness, form (warp) and waviness of a 200 mm back grinding wafer can be seen in FIGURE 5. Although the grinding wheel was also grit size #4000, the mean Ra value is a bit higher. From the grinding marks pattern, it can be seen that the rotation was counterclockwise which changes the orientation from left to right. The warp is rather high because no vacuum was used. The waviness was calculated by applying a 50 waves high-pass filter. The filter is working on the circumference which means that the center area is filtered strongly than at the edge and middle area. Different filter method will be used in the future. The waviness structure follows the roughness pattern, but there are also visible some superimposed weak linear stripes from left to right. These stripes are more prominent in the following measurement (FIGURE 6), which is the result of another 200 mm wafer but ground with a #2000 grit wheel. The interesting point is not the higher roughness, which is induced by the coarser grinding wheel, but that the stripes here are more prominent than the waviness pattern of the grinding marks. The peak to valley height evaluated from A to B is more than 1 μm, which is about 10 times the profile height of the grinding marks waviness.

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The linear stripes are probably caused by the previous wire sawing process, which did not vanish after the grinding process. This could happen, because the wafer is fixed by vacuum on the chuck during grinding which makes the surface temporarily flat. When the wafer is released after the grinding process the waviness structures return. This phenomenon is investigated and described by Pei et al [3]. Furthermore, if the chuck is not cleaned very well the same characteristic can create bumps and dimples. An example of dimples is shown in FIGURE 7. The waviness map of a 300 mm polished wafer is covered with 2 larger and some smaller dimples. By using the 0.03 mm sensor spot the larger dimples where measured again with higher local resolution and represented in a 3D map. The width is in the mm range whereas the depth does not exceed 1 μm.

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Another example of high resolution measurement can be seen in Fig. 8. These measurements were done with an x/y-scanning module covering an area of 40 mm x 20 mm, also by using the small spot size of 0.03 mm. The measurements represent the waviness structures (after applying a 25 waves high pass filter). The mean roughness is 5 nm Ra. Near the center of this section another dimple is visible. The selected profile (a) shows the general waviness with a peak to valley height of about 30 nm. Repeatability measurements have shown that structures of 1 nm height could be resolved.

This makes the WaferMaster moreover interesting for the assessment of nanotopography structures to measure the planarization quality after CMP processes. Also, as can be seen in the 3D graphic, the small spot is able to detect single defects (red peak at the right side) and it has to be investigated, what the limit of lowest defects is. Certainly, it cannot compete with the much more powerful scattered light systems, especially designed for small defect detection in the front-end industry, but it is sufficient to use this function in backend processes.

Summary

A new scattered light sensor technique was presented to measure wafer surfaces, particular in the field of back grinding. The sensor combines surface roughness measurement by means of evaluating the variance (Aq) of the scattered light distribution and use additionally the method of deflectometry to assess form (warpage) and waviness. The Ra evaluation is based on correlation measurements with a confocal microscope. It could be shown that the sensitivity of roughness measurements is going down to Ra = 1 nm with an accuracy of 0.1 nm. The advantage of this technique is the speed (25 s for a whole 300 mm wafer scan) and the ruggedness against environmental mechanical noise. The capability of the full area representation of roughness, warpage and waviness opens new possibilities to characterize and improve the grinding processes as well as checking the quality from the edge area to the center completely.

Depending on the packaging design and the sensitivity of the processes which follow after the back grinding, the difference of the roughness from edge to the center and along the circumference, as well as strong warpage, waviness and defects can influence the final function and performance of the singulated chips. Die breakage e.g. directly depends on the roughness and in particular on the grinding marks orientation. Therefore, a fast and continuous measurement of the back-grinding quality can help to improve the yield in the backend process.

Acknowledgement

We would like to give special thanks to Kevin Hsu from Sanpany and Ian Chen, Honjang Global Technology for their kindly support in organizing the wafer samples and to confirm our CFM measurements with an WLI microscope.

References

[1] Michael Raj Marks, Zainuriah Hassan, Kuan Yew Cheong, Ultrathin Wafer Pre-Assembly and Assembly Process Technologies; Critical Reviews in Solid State and Materials Sciences, 40:251–290, 2015, DOI: 10.1080/10408436.2014.992585
[2] Desmond Y.R. Chong, W.E. Lee, B.K. Lim, John H.L. Pang, T.H. Low, Mechanical characterization in failure, strength of silicon dice, 2004 Inter Society Conference on Thermal Phenomena, 2004 IEEE
[3] Z.J. Pei, Graham R. Fisher, J.Liu, Grinding of Silicon Wafers: A review from historical perspectives, international Journal of Machine Tools & Manufacture, 48 (2008) 1297-1307
[4] Seewig, J., Beichert, G., Brodmann, R., Bodschwinna, H., and Wendel, M. 2009. Extraction of shape and roughness using scattering light. In Proceedings of SPIE. Optical metrology, Systems for Industrial Inspection VI 7389.

By Ayo Kajopaiye, Collaborative Technology Platforms, SEMI

What does Smart Manufacturing mean for the future of the electronics manufacturing supply chain?  SEMI members hold many different perspectives, but one thing is clear ─ the impact of Smart Manufacturing will be huge. SEMI is fully involved with many of the activities that center on Smart Manufacturing.

During the North America Standards meetings that took place at SEMI’s new Headquarters in February, the Automation Technology Committee Chapter in Taiwan was successfully chartered.  K.C. Chou, co-chair of the new Committee, believes in SEMI’s role, saying, “SEMI has a strong reputation for successful standardization which is why the Taiwan PCB industry has selected the global SEMI Standards platform to develop consensus on equipment communication and other manufacturing areas where standards are needed to drive down cost.”

What does the formation of this Committee mean for Smart Manufacturing in the PCB industry? “The industry can now use the Committee to drive consensus on how to adopt GEM technology so it can be implemented consistently” says Brian Rubow, director of Client Training and Support at Cimetrix. “Without these standards agreed upon, every equipment that needs to be integrated may have to have different technology adopted, making the process more difficult just to create a line that will produce their product since a lot of custom integration has to be done. However, once a standard is adopted, instead of spending time dealing with protocols, communication methods and messaging scenarios, they will be able to be a lot more productive and focus on building products and not worry about integrated equipment” he continues.

Next steps

The next step for the new Committee is to propose a ballot for distribution that will address adoption of GEM technology. “Anyone who is interested in this technology, now is the best time to get involved and get their ideas into the collaboration,” Rubow adds. He expects the balloting process to begin over the next quarter.

Many other Smart Manufacturing Programs

SEMI also has a Smart Manufacturing Initiative that is being led by a group of industry leaders through the SEMI Smart Manufacturing Advisory Council. This Council works closely with the Smart Manufacturing Special Interest Group which consists of a broader group of members across different regions as they focus on facilitating collective efforts on issues related to smart manufacturing. Also, members that are part of this group are connected to information and resources that can help with the implementation, supply, services or research of smart manufacturing systems. SEMI plans to continue to play an essential role in the emergence of Smart Manufacturing in the electronics industry.

For questions regarding the Smart Manufacturing Special Interest Group and Advisory Council please contact Tom Salmon, VP of Collaborative Technology Platforms – [email protected] or 408-943-6965.

Also be sure to take a look at SEMI’s Smart Manufacturing Central webpage for information related to Smart Manufacturing – www.semi.org/en/smart-manufacturing-central

SEMICON West 2017

Smart Manufacturing topics (Manufacturing, Automotive, and MedTech) will be covered at SEMICON West 2017. Under the “Programs” tab at the top, visit the “Agenda at a Glance” (filter listings to Smart Topics).  Learn more and register now.

Other SEMI shows will also feature Smart Manufacturing topics, including SEMICON Taiwan (September 13-15 in Taipei), SEMICON Europa (November 14-17 in Munich), and SEMICON Japan (December 13-15 in Tokyo).

IC Insights recently released its Update to its 2017 IC Market Drivers Report.  The Update includes IC Insights’ latest outlooks on the smartphone, automotive, PC/tablet and Internet of Things markets.

In the Update, IC Insights scaled back its total semiconductor sales forecast for system functions related to the Internet of Things in 2020 by about $920 million, mostly because of lower revenue projections for connected cities applications (such as smart electric meters and infrastructure supported by government budgets).  The updated forecast still shows total 2017 sales of IoT semiconductors rising about 16.2% to $21.3 billion (with final revenues in 2016 being slightly lowered to $18.3 billion from the previous estimate of $18.4 billion), but the expected compound annual growth rate between 2015 and 2020 has been reduced to 14.9% versus the CAGR of 15.6% in IC Insights’ original projection from December 2016. Total semiconductor sales for IoT system functions are now expected to reach $31.1 billion in 2020 (Figure 1) versus the previous projection of $32.0 billion in the final year of the forecast.

Figure 1

Figure 1

IC Insights’ revised outlook for IoT semiconductor sales by end-use market categories shows that semiconductor revenues for connected cities applications are projected to grow by a CAGR of 8.9% between 2015 and 2020 (down from 9.7% in IC Insights’ original forecast).  Meanwhile, the IoT semiconductor market for wearable systems is expected to show a CAGR of 17.1% (versus 18.8% in the previous projection).  The lower growth projection in chip sales for connected cities systems is a result of anticipated belt tightening in government spending around the world and the slowing of smart meter installations now that the initial wave of deployments has ended in many countries.  Slower growth in semiconductor sales for wearable systems is primarily related to IC Insights’ reduced forecast for smartwatch shipments through 2020.

The updated outlook nudges up semiconductor growth in the industrial Internet category to a CAGR of 24.1% (compared to 24.0% in the December 2016 forecast) and slightly lowers the annual rate of increase in connected homes and connected vehicles to CAGRs of 21.3% and 32.9%, respectively (from 22.7% and 33.1% in the original 2017 report).

By Paula Doe, SEMI

The future of contamination control in the next-generation supply chain for beyond 14nm-node semiconductor processes faces stringent challenges. While Moore’s Law is driving scale reduction, the industry is also facing ever-increasing process sensitivity, integration challenges of new materials and the need for unprecedented purity at process maturity.

“The supply chain needs a paradigm shift in thinking about defect control. What was just process variation for previous technology nodes can now be an excursion!” says Dr. Archita Sengupta, Intel senior GSM Technologist, leading the filtration and related supply chain contamination control program, who will discuss these challenges and possible solutions in the session on key materials issues at SEMICON West 2017 on July 11 in San Francisco at Moscone Center.

There are new materials being used for the first time, and even familiar materials need to be treated with new and different specifications. Even if the needed parameters are correctly specified, there may not be an accurate way to measure those parameters under HVM conditions, at least that most material suppliers can afford.  Chemicals, advanced filtration and purification, chemical delivery systems and equipment manufacturing can all be sources of wafer contamination. “The interaction between the tool and the chemicals is also increasingly important,” she notes. “All this is going to add more cost for the industry supply chain for quality control, but it will cost more in the end if we don’t proactively work together throughout the supply chain to figure out what matters to control and how!”

Stability is key

The most important thing material suppliers can do to meet customer quality demands is to maintain absolute stability of everything about their material and manufacturing process, suggests Jim Mulready, VP Global Quality Assurance, JSR Micro, who will also present at SEMICON West. “Traditional quality control, where the QC data at the end of my line only has to meet the customer’s specifications, doesn’t work,” he says, noting that the material supplier doesn’t have the same process tool, the same substrate, or the same process conditions as the customer, so the testing can’t duplicate the customer’s result. Moreover, the process sensitivity is getting tighter at every generation, with the tolerance of defects often being beyond the supplier’s ability to detect them. So, no specification can ever be precise enough to capture everything the customer really needs.  “Often tightening the specs doesn’t solve the problem,” he notes. “There are plenty of examples of material that was well within spec but didn’t function properly. The problem is not inadequate specs, it’s inadequate attention to other quality tools. The spec is necessary, but not sufficient.”

“The systematic (as opposed to technical) root cause of the material problems I faced as fab materials quality manager at Intel almost always came down to a problem in stability,” says Mulready, where there was a change to the material the supplier didn’t think was important, a change in the processing that they didn’t catch, or a change in the incoming raw material that they didn’t detect. “Material suppliers have to accept that the customers’ definition of quality becomes their definition of quality, and the main rule is to make sure that a material that’s working does not change at all. Consistency is the key for the end user, so it must be for us as well.  A spec alone will not measure or ensure that.  It takes robust change control, process control, and incoming raw material control.”

Semiconductor makers meanwhile, need to start paying attention not just to their immediate suppliers, but also to their suppliers’ supply chain; for example, not just the resist but also the resin and even the monomers used to make it. While the material suppliers need to qualify the incoming material, and serve as a kind of safety valve between the chemical industry and the IC makers, it can be difficult for them to control the supply quality when they are a very minor customer for the commodity chemical suppliers.  Those suppliers in turn may have no interest in investing in the tools needed to measure the particular properties of concern, and there may be a need for the IC customer to help inflict some pressure.

For more details on the SEMICON West 2017 Materials program, “Material Supply Challenges for Current and Future Leading-edge Devices,” organized by SEMI’s Chemical & Gas Manufacturers Group (CGMG), see www.semiconwest.org/programs-catalog/material-supply-leading-edge-devices. To see the full SEMICON West agenda, visit www.semiconwest.org/agenda-glance.

The latest update to the World Fab Forecast report, published on May 31, 2017 by SEMI, reveals record spending for fab construction and fab equipment. Korea, Taiwan, and China all see large investments, and spending in Europe will also increase significantly. In 2017, over US$49 billion will be spent on equipment alone, a record for the semiconductor industry.  Spending on new fab construction is projected to reach over $8 billion, the second largest year on record.  Records will shatter again in 2018, when equipment spending will pass $54 billion, and new fab construction spending is forecast at an all-time high of $10 billion. See Figure.

Figure 1

Figure 1

SEMI reports that these unprecedented high numbers are not only driven by a handful of well-known, established companies, but also by several new Chinese companies entering the scene with large budgets. An increase in overall fab spending (construction and equipment together) of 54 percent year-over-year (YoY) in China is expected.  Total spending rises from $3.5 billion in 2016 to $5.4 billion in 2017, and then to $8.6 billion in 2018, another 60 percent year-over-year (YoY).

Some of these China-based companies are well known, such as Hua Li Microelectronics or SMIC (top investors in 2017 and 2018), though newcomers in the arena, including Yangtze Memory Technology, Fujian Jin Hua Semiconductor, Tsinghua Unigroup, Tacoma Semiconductor, and Hefei Chang Xin Memory, add to the spending surge.

The SEMI World Fab Forecast breaks down fab equipment spending by region. Korea leads both years of our forecast period, with spending of $14.6 billion in 2017 and $15.1 billion in 2018.  In 2017, Taiwan is projected to be the second largest spending region on equipment, but China will take over second place in 2018 as it equips the many new fabs being built in 2016 and 2017.  Americas is in fourth place, projected to spend $5.2 billion in 2017 and $5.5 billion in 2018.  Japan will come in fifth, spending $5.1 billion in 2017 and $5.3 billion in 2018.  Although the Europe/Mideast region is in sixth place with relatively modest investments of $3.8 billion in 2017, this represents remarkable growth for the region, 71 percent more than in 2016; and the region will bump spending another 20 percent in 2018 (to $4.6 billion).

This exciting growth cycle could continue well beyond 2018.  Record fab construction spending of $10 billion for 2018 means new fabs will need to be equipped at least a year down the road, leading to high expectations for good business beyond the current two-year forecast period.

Since the last publication on February 28, the SEMI Industry Research & Statistics team has made 279 changes on 244 facilities/lines. In that time frame, 24 new facilities were added and 4 fab projects were closed.

For insight into semiconductor manufacturing in 2017 and 2018 with details about capex for construction projects, fab equipping, technology levels, and products, visit the SEMI Fab Database webpage and order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,100 facilities including over 60 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.

IBM (NYSE: IBM), its Research Alliance partners GLOBALFOUNDRIES and Samsung, and equipment suppliers have developed an industry-first process to build silicon nanosheet transistors that will enable 5 nanometer (nm) chips. The details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan. In less than two years since developing a 7nm test node chip with 20 billion transistors, scientists have paved the way for 30 billion switches on a fingernail-sized chip.

The resulting increase in performance will help accelerate cognitive computing, the Internet of Things (IoT), and other data-intensive applications delivered in the cloud. The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today’s devices, before needing to be charged.

Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor, instead of the standard FinFET architecture, which is the blueprint for the semiconductor industry up through 7nm node technology.

“For business and society to meet the demands of cognitive and cloud computing in the coming years, advancement in semiconductor technology is essential,” said Arvind Krishna, senior vice president, Hybrid Cloud, and director, IBM Research. “That’s why IBM aggressively pursues new and different architectures and materials that push the limits of this industry, and brings them to market in technologies like mainframes and our cognitive systems.”

The silicon nanosheet transistor demonstration, as detailed in the Research Alliance paper Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET, and published by VLSI, proves that 5nm chips are possible, more powerful, and not too far off in the future.

Compared to the leading edge 10nm technology available in the market, a nanosheet-based 5nm technology can deliver 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance. This improvement enables a significant boost to meeting the future demands of artificial intelligence (AI) systems, virtual reality and mobile devices.

Building a new switch

“This announcement is the latest example of the world-class research that continues to emerge from our groundbreaking public-private partnership in New York,” said Gary Patton, CTO and Head of Worldwide R&D at GLOBALFOUNDRIES. “As we make progress toward commercializing 7nm in 2018 at our Fab 8 manufacturing facility, we are actively pursuing next-generation technologies at 5nm and beyond to maintain technology leadership and enable our customers to produce a smaller, faster, and more cost efficient generation of semiconductors.”

IBM Research has explored nanosheet semiconductor technology for more than 10 years. This work is the first in the industry to demonstrate the feasibility to design and fabricate stacked nanosheet devices with electrical properties superior to FinFET architecture.

This same Extreme Ultraviolet (EUV) lithography approach used to produce the 7nm test node and its 20 billion transistors was applied to the nanosheet transistor architecture. Using EUV lithography, the width of the nanosheets can be adjusted continuously, all within a single manufacturing process or chip design. This adjustability permits the fine-tuning of performance and power for specific circuits – something not possible with today’s FinFET transistor architecture production, which is limited by its current-carrying fin height. Therefore, while FinFET chips can scale to 5nm, simply reducing the amount of space between fins does not provide increased current flow for additional performance.

“Today’s announcement continues the public-private model collaboration with IBM that is energizing SUNY-Polytechnic’s, Albany’s, and New York State’s leadership and innovation in developing next generation technologies,” said Dr. Bahgat Sammakia, Interim President, SUNY Polytechnic Institute. “We believe that enabling the first 5nm transistor is a significant milestone for the entire semiconductor industry as we continue to push beyond the limitations of our current capabilities. SUNY Poly’s partnership with IBM and Empire State Development is a perfect example of how Industry, Government and Academia can successfully collaborate and have a broad and positive impact on society.”

Part of IBM’s $3 billion, five-year investment in chip R&D (announced in 2014), the proof of nanosheet architecture scaling to a 5nm node continues IBM’s legacy of historic contributions to silicon and semiconductor innovation. They include the invention or first implementation of the single cell DRAM, the Dennard Scaling Laws, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator, strained engineering, multi core microprocessors, immersion lithography, high speed SiGe, High-k gate dielectrics, embedded DRAM, 3D chip stacking and Air gap insulators.

IC Insights recently released its May Update to the 2017 McClean Report. This Update included IC Insights’ latest 2017 IC market forecast, a discussion of the 1Q17 semiconductor industry market results, a review of the IC market by electronic system type, a look at the top-25 1Q17 semiconductor suppliers, and an update of the capital spending forecast by company.

Figure 1 shows the “Billion-Dollar Club” list from 2007 through IC Insights’ forecast in 2017. In total, there are 15 companies that are forecast to have semiconductor capital expenditures of ≥$1.0 billion in 2017, up from 11 in 2016 and only 8 in 2013. Infineon and Renesas are expected to move into the major spending ranking this year as each company is aggressively targeting the fast rising automotive semiconductor market. Other companies expected to be added to the ranking this year include Nanya and ST. Moreover, IC Insights believes that a few Chinese companies are likely to break into the “major spenders” ranking over the next couple of years as they ramp up their new fabs. The 15 companies listed, which include four pure-play foundries, are forecast to represent 83% of total worldwide semiconductor industry capital spending in 2017, the highest percentage over the timeperiod shown.

This year, four companies—Intel, Samsung, GlobalFoundries, and SK Hynix— are expected to represent the bulk of the increase in spending. Samsung is forecast to spend $3,200 million more in capital outlays this year than in 2016, Intel $2,375 million more, GlobalFoundries $865 million more, and SK Hynix an additional $812 million. Combined, these four companies are expected to increase their spending by $7,252 million in 2017, or about 90% of the total $8,021 million net jump in total semiconductor industry capital expenditures forecast for this year.

With a 31% increase, the DRAM/SRAM segment is expected to display the largest percentage increase in capital expenditures of the major products types listed this year. With DRAM ASPs surging since the third quarter of 2016, DRAM manufacturers are once again stepping up spending for this segment.

Capital spending for flash memory in 2016 ($14.6 billion) was significantly higher than spending allocated for DRAM ($8.5 billion). Overall, IC Insights believes that essentially all of the spending for flash memory in 2016 and 2017 was and will be dedicated to 3D NAND flash memory process technology as opposed to planar flash memory. A big jump in NAND flash capital spending in 2017 is expected to come from Samsung as it ramps its 3D NAND production in its giant new fab in Pyeongtaek, South Korea.

Figure 1

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By Walt Custer, Custer Consulting Group, and Dan Tracy, SEMI

SEMI’s year-to-date worldwide semiconductor equipment billings year-to-date through March show a 59.6 percent gain to the same period last year.

Understanding volatility in the electronic equipment supply chain can be valuable in forecasting future business activity.  A useful way to compare relevant electronic industry data series is by using 3/12 growth rates.  The 3/12 growth is the ratio of three months of data, compared to the same three months a year earlier.

Chart 1 compares the 3/12 growth rates of four data series:

  • World semiconductor equipment shipments (SEMI; www.semi.org)
  • Taiwan chip foundry sales (company composite maintained by Custer Consulting Group)
  • World semiconductor shipments (SIA, www.semiconductors.org & WSTS, www.wsts.org)
  • World electronic equipment sales (composite of 238 global OEMS maintained by Custer Consulting Group).

supply-chain-dynamics

Highlights

  • Semiconductor capital equipment sales are by far the most volatile of the four series in Chart 1, followed by foundry sales.
  • Foundry sales are a good leading indicator for semiconductor equipment shipments ─ leading SEMI equipment by 3-4 months on a 3/12 growth basis.
  • Foundry growth peaked in November 2016.
  • SEMI equipment growth appears to have peaked in February 2017.
  • Semiconductor shipments may have peaked in March 2017. March semiconductor revenues were up 18.5 percent in 1Q’17 vs 1Q’16 and, although still very strong, their rate of growth appears to have plateaued.

Note that 3/12 values greater than 1.0 indicate growth.  Declining 3/12 values (but greater than 1.0) indicate growth but at a slower rate.  Values below 1.0 indicate contraction.

Based upon Chart 1, semiconductor equipment 3/12 growth will likely reach zero in August or September of this year. Considering the unstable world geopolitical situation, uncertainty clearly exists.

SEMI members can access member-only market data and information at www.semi.org/en/free-market-data-semi-members.

Custer Consulting Group (www.custerconsulting.com) provides market research, business analyses and forecasts for the electronic equipment and solar/photovoltaic supply chains including semiconductors, printed circuit boards & other passive components, photovoltaic cells & modules, EMS, ODM & related assembly activities and materials & process equipment.