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Siemens and Mentor Graphics (NASDAQ: MENT) today announced that they have entered into a merger agreement under which Siemens will acquire Mentor for an enterprise value of $4.5 billion. Mentor’s Board of Directors approved and declared advisable the merger agreement, and Mentor’s Board of Directors recommends the approval and adoption of the merger agreement by the holders of shares of Mentor common stock.

“Siemens is acquiring Mentor as part of its Vision 2020 concept to be the Benchmark for the New Industrial Age. It’s a perfect portfolio fit to further expand our digital leadership and set the pace in the industry,” said Joe Kaeser, President and CEO of Siemens AG.

“With Mentor, we’re acquiring an established technology leader with a talented employee base that will allow us to supplement our world-class industrial software portfolio. It will complement our strong offering in mechanics and software with design, test and simulation of electrical and electronic systems,” said Klaus Helmrich, member of the Managing Board of Siemens.

Mentor is headquartered in Wilsonville, Oregon, U.S., and has employees in 32 countries worldwide. In its fiscal year ended January 31, 2016, Mentor had over 5,700 employees and generated revenue of approximately $1.2 billion with an adjusted operating margin of 20.2%. Siemens expects these attractive margins to continue in the future and contribute significantly to the Product Lifecycle Management (PLM) software business of Siemens Digital Factory (DF) Division, which Mentor will join. Mentor serves a large, diverse customer base of marquee systems companies and IC/semiconductors companies with over 14,000 global accounts across communications, computer, consumer electronics, semiconductor, networking, aerospace, multimedia, and transportation industries. Mentor is viewed as a global leader in strategic industry segments including IC design, test and manufacturing; electronic systems design and analysis; and emerging markets including automotive electronics.

“Combining Mentor’s technology leadership and deep customer relationships with Siemens’ global scale and resources will better enable us to serve the growing needs of our customers, and unlock additional significant opportunities for our employees,” said Walden C. Rhines, chairman and CEO of Mentor. “Siemens is an ideal partner with financial depth and stability, and their resources and additional investment will allow us to innovate even faster and accelerate our vision of creating top-to-bottom automated design solutions for electronic systems. We are excited to join the Siemens family, as it is clear they share the same values and focus on customer success, and are pleased that this transaction provides immediate and certain value to our stockholders.”

Siemens expects to achieve synergies through a combination of revenue growth and anticipated margin expansion, with a total EBIT impact of over €100 million within 4 years from closing the transaction. Additionally, the transaction is expected to be EPS accretive within three years from closing. Closing of the transaction is subject to customary closing conditions and is expected in Q2 of calendar 2017. Mentor will be part of the PLM software business of Siemens’ DF Division. DF is the industry leader in automation technology and a leading provider of PLM software.

“By adding Mentor’s electronic design automation solutions and talented experts to our team, we’re greatly enhancing our core competencies for product design that creates a very precise digital twin of any smart product and production line,” noted Helmrich.

Shares in Mentor Graphics jumped 18.5 percent to $36.37 in early U.S. trading, while Siemens was 1.1 percent higher by 1435 GMT.

The deal will boost its software revenue by about a third from 3.3 billion euros, to around 6 percent of group revenue.

Deutsche Bank and JP Morgan advised Siemens on the transaction, which is expected to close in the second quarter of 2017. Bank of America advised Mentor Graphics.

Researchers at the Fraunhofer Institute for Solar Energy Systems ISE together with the Austrian company EV Group (EVG) have successfully manufactured a silicon-based multi-junction solar cell with two contacts and an efficiency exceeding the theoretical limit of silicon solar cells. For this achievement, the researchers used a “direct wafer bonding” process to transfer a few micrometers of III-V semiconductor material to silicon, a well-known process in the microelectronics industry. After plasma activation, the subcell surfaces are bonded together in vacuum by applying pressure. The atoms on the surface of the III-V subcell form bonds with the silicon atoms, creating a monolithic device. The efficiency achieved by the researchers presents a first-time result for this type of fully integrated silicon-based multi-junction solar cell. The complexity of its inner structure is not evident from its outer appearance: the cell has a simple front and rear contact just as a conventional silicon solar cell and therefore can be integrated into photovoltaic modules in the same manner.

Wafer-bonded III-V / Si multi-junction solar cell with 30.2 percent efficiency ©Fraunhofer ISE/A. Wekkeli

Wafer-bonded III-V / Si multi-junction solar cell with 30.2 percent efficiency ©Fraunhofer ISE/A. Wekkeli

“We are working on methods to surpass the theoretical limits of silicon solar cells,” says Dr. Frank Dimroth, department head at Fraunhofer ISE. “It is our long-standing experience with silicon and III-V technologies that has enabled us to reach this milestone today.” A conversion efficiency of 30.2 percent for the III-V / Si multi-junction solar cell of 4 cm² was measured at Fraunhofer ISE’s calibration laboratory. In comparison, the highest efficiency measured to date for a pure silicon solar cell is 26.3 percent, and the theoretical efficiency limit is 29.4 percent.

The III-V / Si multi-junction solar cell consists of a sequence of subcells stacked on top of each other. So-called “tunnel diodes” internally connect the three subcells made of gallium-indium-phosphide (GaInP), gallium-arsenide (GaAs) and silicon (Si), which span the absorption range of the sun’s spectrum. The GaInP top cell absorbs radiation between 300 and 670 nm. The middle GaAs subcell absorbs radiation between 500 and 890 nm and the bottom Si subcell between 650 and 1180 nm, respectively. The III-V layers are first epitaxially deposited on a GaAs substrate and then bonded to a silicon solar cell structure. Subsequently the GaAs substrate is removed, and a front and rear contact as well as an antireflection coating are applied.

“Key to the success was to find a manufacturing process for silicon solar cells that produces a smooth and highly doped surface which is suitable for wafer bonding as well as accounts for the different needs of silicon and the applied III-V semiconductors,” explains Dr. Jan Benick, team leader at Fraunhofer ISE.

“In developing the process, we relied on our decades of research experience in the development of highest efficiency silicon solar cells.” Institute Director Prof. Eicke Weber expresses his delight: “I am pleased that Fraunhofer ISE has so convincingly succeeded in breaking through the glass ceiling of 30 percent efficiency with its fully integrated silicon-based solar cell with two contacts. With this achievement, we have opened the door for further efficiency improvements for cells based on the long-proven silicon material.”

“The III-V / Si multi-junction solar cell is an impressive demonstration of the possibilities of our ComBond® cluster for resistance-free bonding of different semiconductors without the use of adhesives,” says Markus Wimplinger, Corporate Technology Development and IP Director at EV Group. “Since 2012, we have been working closely with Fraunhofer ISE on this development and today are proud of our team’s excellent achievements.” The direct wafer-bonding process is already used in the microelectronics industry to manufacture computer chips.

On the way to the industrial manufacturing of III-V / Si multi-junction solar cells, the costs of the III-V epitaxy and the connecting technology with silicon must be reduced. There are still great challenges to overcome in this area, which the Fraunhofer ISE researchers intend to solve through future investigations. Fraunhofer ISE’s new Center for High Efficiency Solar Cells, presently being constructed in Freiburg, will provide them with the perfect setting for developing next-generation III-V and silicon solar cell technologies. The ultimate objective is to make high efficiency solar PV modules with efficiencies of over 30 percent possible in the future.

The young researcher Dr. Romain Cariou carried out research on this project at Fraunhofer ISE with the support of a Marie Curie Postdoctoral Fellowship. Funding was provided by the EU project HISTORIC. The work at EVG was supported by the Austrian Ministry for Technology.

Since President Obama took office in 2009, the Administration has focused on promoting innovation for the purposes of strengthening the economy, improving quality of life, and protecting the safety and security of our country.

Last week, the President’s Council of Advisors on Science and Technology (PCAST) announced the formation of a new working group focused on strengthening the U.S. semiconductor industry in ways that benefit the nation’s economic and security interests.

Semiconductors are essential to many aspects of modern life, from cellphones and automobiles to medical diagnostics to reconnaissance satellites and weapon systems. The semiconductor industry directly employs 250,000 workers, is the third largest source of U.S. manufactured exports, and has the highest level of investment in research and development (R&D) as a percentage of sales of any major industry. In addition, the semiconductor industry creates foundational technologies that enable innovation in virtually every sector of the U.S. economy. A loss of leadership in semiconductor innovation and manufacturing could have significant adverse impacts on the U.S. economy and even on national security.

In a world where the supply chains are global, policies being pursued by other countries are posing new challenges to the U.S. semiconductor industry. Specifically, some countries that are important in this domain are subsidizing their domestic semiconductor industry or requiring implicit transfer of technology and intellectual property in exchange for market access. Such policies could lead to overcapacity and dumping, reduce incentives for private-sector R&D in the United States, and thereby slow the pace of semiconductor innovation and realization of the economic and security benefits that such innovation could bring.

The industry may also be approaching technological and economic inflection points. Based on the currently commercialized approach to semiconductor technology, the industry may soon be unable to continue the pace of advance described by “Moore’s Law”—doubling the processing power of chips every 18–24 months—a pace that has brought with it rapid advances in the capabilities of systems that use semiconductors, opened up new applications, and thus fueled economic growth while increasing quality of life and strengthening national security. Indeed, the exponentially growing cost of designing and fabricating higher-performance chips in the conventional mold is already stifling innovation, making it more difficult for startups and new ideas from university research to create new markets—a key source of competitive advantage for America’s entrepreneurial economy.

Additional public and private investments in R&D are almost certain to be required if the past remarkable pace of improvements in price and performance of semiconductors and the benefits deriving therefrom are to continue—R&D that looks to create new technologies that can leapfrog beyond the limits of today’s technology and explore entirely new computer architectures and their integration into systems well beyond the traditional computing sphere, including automotive and other mobile applications.

The time is therefore right for a fresh look at the policy issues shaping innovation and global competition in the semiconductor industry. The new PCAST working group will identify the core challenges facing the semiconductor industry at home and abroad and identify major opportunities for sustaining U.S. leadership. Based on its findings, the working group will deliver a set of recommendations on initial actions the Federal government, industry, and academia could pursue to maintain U.S. leadership in this crucial domain.

The full working group includes the following members:

  • John Holdren (Director, OSTP; PCAST Co-Chair); Working Group Co-Chair
  • Paul Otellini (Former President and CEO, Intel); Working Group Co-Chair
  • Richard Beyer (Former Chairman and CEO, Freescale Semiconductor)
  • Wes Bush (Chairman, CEO, and President, Northrop Grumman)
  • Diana Farrell (President and CEO, JP Morgan Chase Institute)
  • John Hennessy (President Emeritus, Stanford University)
  • Paul Jacobs (Executive Chairman, Qualcomm)
  • Ajit Manocha (Former CEO, GlobalFoundries)
  • Jami Miscik (Co-CEO and Vice Chairman, Kissinger Associates; Co- Chair, President’s Intelligence Advisory Board)
  • Craig Mundie (President, Mundie and Associates; Former Senior Advisor, Microsoft; Member of PCAST)
  • Mike Splinter (Former CEO and Chairman, Applied Materials)
  • Laura Tyson (Distinguished Professor of the Graduate School, UC Berkeley; Former CEA Chair and NEC Director)

Samsung Electronics Co. Ltd. announced today that it is expanding its advanced foundry process technology offerings with the fourth-generation 14-nanometer (nm) process (14LPU) and the third-generation 10nm process (10LPU) to meet the requirements of next generation products ranging from mobile and consumer electronics to data centers and automotives.

Samsung presented these new technology offerings at the Samsung Foundry Forum to foundry customers and partners. The event was held at its Device Solutions America headquarters today, where the company elaborated on the details of new technology offerings including 14LPU and 10LPU.

Samsung’s fourth-generation 14nm process technology, 14LPU, delivers higher performance at the same power and design rules compared to its third-generation 14nm process (14LPC). 14LPU will be optimally suited for high-performance and compute-intensive applications.

Samsung’s third-generation 10nm process, 10LPU, will provide area reduction compared to its previous generations (10LPE and 10LPP). Due to limitations of current lithography technologies, 10LPU is expected to be the most cost-effective cutting-edge process technology in the industry. Together with the second-generation 10nm process (10LPP) that offers an extra performance boost from 10LPE, 10LPU is positioned to meet the needs of an extended range of applications that can benefit from the advanced 10nm process.

On top of the new process offerings, Samsung also updated its 7nm EUV process development status and showcased its 7nm EUV wafer.

“After we announced the industry’s first 10nm mass production in mid-October, we have now also expanded our lineup with new foundry offerings, 14LPU and 10LPU,” said Ben Suh, Senior Vice President of foundry marketing at Samsung Electronics. “Samsung is very confident with our technology definitions that provide design advantages on an aggressive process with manufacturability considerations. We have received tremendous positive market feedback and are looking forward to expanding our leadership in the advanced process technology space.”

Process design kits (PDK) for 14LPU and 10LPU process technologies will be available during the second quarter of 2017.

Netherlands-based ASML Holding NV, a chip industry equipment provider, and Germany-based Carl Zeiss SMT, a business group of Carl Zeiss AG (ZEISS), have agreed to strengthen their long-standing and successful partnership in the semiconductor lithography business. The main objective of this agreement is to facilitate the development of the future generation of Extreme Ultraviolet (EUV) lithography systems due in the first few years of the next decade. This technology will enable the semiconductor industry to produce much higher performance microchips at lower costs.

ZEISS and ASML jointly announce today, that they have agreed on a 24.9% minority stake of ASML in ZEISS’s subsidiary Carl Zeiss SMT, for which ASML will pay ZEISS EUR 1 billion in cash. The companies stated that no further exchange of shares is planned or agreed.

ASML is a key supplier of semiconductor patterning products and services used by the world`s top producers of microchips. With its high-performance optics Carl Zeiss SMT supplies an essential subsystem of ASML’s semiconductor lithography scanners and is ASML`s most important strategic partner. ASML and Carl Zeiss SMT have been in close partnership for more than 30 years. Both firms have grown strongly over the last decades benefiting from each other`s strengths.

A new cycle of investments required for the development of an entirely new optical system for the future generation of EUV, expected to be provided to the chip making industry in the first few years of the next decade, has triggered the partners to take a further step in the collaboration.

“In 2018 the first chips made on current technology EUV scanners are expected to roll off the production lines of our customers. A lot of work is still being done to ensure the introduction of EUV in volume manufacturing, in tight conjunction with our highly successful immersion scanners which we continue to improve. Yet ASML and ZEISS are looking beyond this important milestone. We see a long and successful future for EUV lithography in advanced chip manufacturing and with this agreement we set the right conditions for development of the next generation of EUV by ASML and Carl Zeiss SMT, so that our customers can reap the rewards of their EUV investments up to the end of the next decade,” said Peter Wennink, President and Chief Executive Officer of ASML.

“With this agreement we clear the road for advanced lithography to support the new concepts and designs for future generations of advanced chips. After the many years of fruitful partnership, we see this agreement as a further strong endorsement of our long term cooperation which allows us to further expand our joint leadership that we have already accomplished together”, says Michael Kaschke, President and CEO of ZEISS.

The next generation of EUV optics will offer a higher numerical aperture (NA), making it possible to further reduce critical dimensions in the lithography process. The current EUV systems have an optical system with NA of 0.33 whereas the new optics will have NA larger than 0.5, enabling several generations of geometric chip scaling.

In addition to the agreement of the minority interest, the two companies have also agreed that ASML will support Carl Zeiss SMT`s research and development (R&D) for approximately EUR 220 million as well as capital expenditures and other supply chain investments for approximately EUR 540 million over the next 6 years.

These investments will predominantly be allocated at Carl Zeiss SMT’s main location in Oberkochen, Germany, and will primarily be used for capacity and resource expansions, with positive effects on long-term employment at this location. Carl Zeiss SMT will remain fully integrated into the structure of the ZEISS Group as one of the major and important business groups.

“High-NA is the logical next step for EUV, as it circumvents complex and expensive 0.33 NA EUV multiple patterning. High-NA EUV is a robust way for chips to scale all the way down to the sub-3 nanometer logic node in a single exposure with high productivity and reduced cost per feature. That is several generations from where we are today and underlines our commitment to propel Moore’s law,” said Martin van den Brink, President and Chief Technology Officer at ASML.

Carl Zeiss SMT will pay an annual dividend to its shareholders Carl Zeiss AG and ASML. ASML expects that the minority share transaction will be accretive to its earnings before adjustments related to purchase price accounting and differences in accounting standards. Furthermore, ASML`s contribution to Carl Zeiss SMT`s R&D and capital expenditures will be taken into account in the future pricing of SMT`s next generation EUV optics to ASML.

The transaction has been approved by both companies’ supervisory boards. ASML will fund the transaction from available cash, potentially supplemented by new debt. The transaction is subject to regulatory clearance and is expected to be closed in the second quarter of 2017.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $88.3 billion for the third quarter of 2016, marking the industry’s highest-ever quarterly sales and an increase of 11.5 percent compared to the previous quarter. Sales for the month of September 2016 were $29.4 billion, an increase of 3.6 percent over the September 2015 total of $28.4 billion and 4.2 percent more than the previous month’s total of $28.2 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor market has rebounded markedly in recent months, with September showing the clearest evidence yet of resurgent sales,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The industry posted its highest-ever quarterly sales total, with most regional markets and semiconductor product categories contributing to the gains. Indications are positive for increased sales in the coming months, but it remains to be seen whether the global market will surpass annual sales from last year.”

Regionally, month-to-month sales increased in September across all markets: China (5.4 percent), the Americas (4.6 percent), Asia Pacific/All Other (4.2 percent), Japan (2.3 percent), and Europe (1.6 percent). Compared to the same month last year, sales in September increased in China (12.0 percent), Japan (4.2 percent), and Asia Pacific/All Other (1.7 percent), but decreased in the Americas (-2.4 percent) and Europe (-4.0 percent).

“China stood out in September, leading all regional markets with growth of 5 percent month-to-month and 12 percent year-to-year,” Neuffer said. “Standouts among semiconductor product categories included NAND flash and microprocessors, both of which posted solid month-to-month growth in September.”

September 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.43

5.68

4.6%

Europe

2.71

2.76

1.6%

Japan

2.74

2.80

2.3%

China

8.99

9.47

5.4%

Asia Pacific/All Other

8.37

8.73

4.2%

Total

28.24

29.43

4.2%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.82

5.68

-2.4%

Europe

2.87

2.76

-4.0%

Japan

2.69

2.80

4.2%

China

8.45

9.47

12.0%

Asia Pacific/All Other

8.58

8.73

1.7%

Total

28.41

29.43

3.6%

Three-Month-Moving Average Sales

Market

Apr/May/Jun

Jul/Aug/Sept

% Change

Americas

4.94

5.68

15.0%

Europe

2.68

2.76

3.0%

Japan

2.53

2.80

10.8%

China

8.29

9.47

14.2%

Asia Pacific/All Other

7.97

8.73

9.5%

Total

26.41

29.43

11.5%

van der Pauw measurements with a parameter analyzer are examined followed by a look at Hall effects measurements.

BY MARY ANNE TUPTA, Keithley Instruments Product Line at Tektronix, Cleveland, OH

Semiconductor material research and device testing often involves determining the resistivity and Hall mobility of a sample. The resistivity of a particular semiconductor material primarily depends on the bulk doping used. In a device, the resistivity can affect the capacitance, the series resistance, and the threshold voltage, so it’s important to perform this measurement carefully and accurately.

The resistivity of the semiconductor material is often determined using a four-point probe or Kelvin technique where two of the probes are used to source current and the other two probes are used to measure voltage. Using four probes eliminates measurement errors due to probe resistance, spreading resistance under each probe, and contact resis- tance between each metal probe and the semiconductor material. Because a high impedance voltmeter draws little current, the voltage drops are very small.

One useful Kelvin technique for determining the resistivity of a semiconductor material is the van der Pauw (vdp) method using a parameter analyzer with high input impedance and accurate low current sourcing. This article first looks at van der Pauw measurements with a parameter analyzer followed by a look at Hall effects measurements.

van der Pauw resistivity measurements

The van der Pauw method involves applying a current and measuring voltage using four small contacts on the circumference of a flat, arbitrarily shaped sample of uniform thickness. This method is particularly useful for measuring very small samples because geometric spacing of the contacts is unimportant, meaning that effects due to a sample’s size are irrelevant.

Using this method, the resistivity is derived from a total of eight measurements that are made around the periphery of the sample using the configurations shown in FIGURE 1.

FIGURE 1. van der Pauw resistivity conventions.

FIGURE 1. van der Pauw resistivity conventions.

Once all the voltage measurements are taken, two values of resistivity, ρA and ρB, are derived as follows:

Equation 1

 

where: ρA and ρB are volume resistivities in ohm-cm

ts is the sample thickness in cm

V1–V8 represents the voltages measured by the voltmeter

I is the current through the sample in amperes

fA and fB are geometrical factors based on sample symmetry. They are related to the two resistance ratios QA and QB as shown in the following equations (fA = fB = 1 for perfect symmetry).

QA and QB are calculated using the measured voltages as follows:

Equation 2

Also, Q and f are related as follows:

Equation 3

A plot of this function is shown in FIGURE 2. The value of f can be found from this plot once Q has been calculated.

FIGURE 2. Plot of f vs. Q.

FIGURE 2. Plot of f vs. Q.

Once ρA and ρB are known, the average resistivity (ρAVG) can be determined as follows:

Equation 4

The electrical measurements for determining van der Pauw resistivity require a current source and a voltmeter. To automate measurements, it’s possible to use a programmable switch to switch the current source and the voltmeter to all sides of the sample. However, a parameter analyzer offers greater efficiency.

A parameter analyzer with four source measure units (SMU) and four preamps (for high resistance measurements) is well-suited for performing van der Pauw resis- tivity measurements, and enables measurements of resistances greater than 1012Ω. A key advantage is that each SMU instrument can be configured as a current source or as a voltmeter with no external switching required. This eliminates leakage and offsets errors caused by mechanical switches as well as the need for additional instruments and programming.

For high resistance materials, a current source that can output very small current with a high output impedance is necessary. A differential electrometer with high input impedance is required to minimize loading effects on the sample.

Each terminal of the sample is connected to one SMU instrument, so a parameter analyzer with four SMU instruments is required. A diagram of how the four SMUs are configured for each of the tests is shown in FIGURE 3. For each test, three of the SMU instruments are configured as a current bias and a voltmeter. One of the SMUs applies the test current and the other two SMUs are used as high impedance voltmeters with a test current of zero amps on a low current range (typically 1nA range). The fourth SMU instrument is set to common. The voltage difference is calculated between the two SMU instruments set up as high impedance voltmeters. This measurement setup is duplicated around the sample, with each of the four SMU instruments changing functions in each of the four tests. The test current and voltage differences between the terminals from the four tests are used to calculate resistivity.

FIGURE 3. SMU Instrument Configurations for van der Pauw Measurements.

FIGURE 3. SMU Instrument Configurations for van der Pauw Measurements.

For high resistance samples, it’s necessary to determine the settling time of the measurement. This is done by sourcing current into two terminals of the sample and measuring the voltage difference between the other two terminals. The settling time can be determined by graphing the voltage difference versus the time of the measurement. A timing graph of a very high resistance material is shown in FIGURE 4. Note that settling time needs to be determined every time for different materials; however, it’s not necessary for low resistance materials since they have a short settling time.

FIGURE 4. Voltage vs. time graph of a very high resistance sample.

FIGURE 4. Voltage vs. time graph of a very high resistance sample.

Hall voltage measurements

Hall effect measurements are important to semiconductor material characterization because from the Hall voltage, the conductivity type, carrier density, and mobility can be derived. With an applied magnetic field, the Hall voltage can be measured using the configurations shown in FIGURE 5.

FIGURE 5. Hall voltage measurement configurations.

FIGURE 5. Hall voltage measurement configurations.

With a positive magnetic field, B, current is applied between terminals 1 and 3, and the voltage drop (V2–4+) is measured between terminals 2 and 4. When the current is reversed, the voltage drop (V4–2+) is measured. Next, current is applied between terminals 2 and 4, and the voltage drop (V1–3+) between terminals 1 and 3 is measured. Then the current is reversed and the voltage (V3–1+) is measured again.

Then the magnetic field, B, is reversed and the procedure is repeated again, measuring the four voltages: (V2–4–), (V4–2–), (V1–3–), and (V3–1–).

From the eight Hall voltage measurements, the average Hall coefficient can be calculated as follows:

Equation 5

where: RHC and RHD are Hall coefficients in cm3/C

ts is the sample thickness in cm

V represents the voltages measured by the voltmeter

I is the current through the sample in amperes

B is the magnetic flux in Vs/cm2 (1 Vs/cm2 = 108 gauss)

Once RHC and RHD have been calculated, the average Hall coefficient (RHAVG) can be determined as follows:

Equation 6

From the resistivity (ρAVG) and the Hall coefficient (RHAVG), the mobility (μH) can be calculated:

Equation 7

For successful resistivity measurements, potential sources of errors need to be considered. Here are the errors sources you are most likely to encounter.

Electrostatic Interference — Electrostatic interference occurs when an electrically charged object is brought near an uncharged object. Usually, the effects of the interference are not noticeable because the charge dissi- pates rapidly at low resistance levels. However, high resis- tance materials do not allow the charge to decay quickly and unstable measurements may result. The erroneous readings may be due to either DC or AC electrostatic fields.

To minimize the effects of these fields, an electrostatic shield can be built to enclose the sensitive circuitry. The shield should be made from a conductive material and connected to the low impedance (FORCE LO) terminal of the test instrument. The cabling in the circuit must also be shielded.

Leakage Current — For high resistance samples, leakage current may degrade measurements. The leakage current is due to the insulation resistance of the cables, probes, and test fixturing.

Leakage current may be minimized by using good quality insulators, by reducing humidity, and by using guarding.

A guard is a conductor connected to a low impedance point in the circuit that is nearly at the same potential as the high impedance lead being guarded. Using triax cabling and fixturing will ensure that the high impedance terminal of the sample is guarded. The guard connection will also reduce measurement time since the cable capacitance will no longer affect the time constant of the measurement.

Light — Currents generated by photoconductive effects can degrade measurements, especially on high resistance samples. To prevent this, the sample should be placed in a dark chamber.

Temperature — Thermoelectric voltages may also affect measurement accuracy. Temperature gradients may result if the sample temperature is not uniform. Thermoelectric voltages may also be generated from sample heating caused by the source current. Heating from the source current will more likely affect low resistance samples, because a higher test current is needed to make the voltage measure- ments easier. Temperature fluctuations in the laboratory environment may also affect measurements. Because semiconductors have a relatively large temperature coeffi- cient, temperature variations in the laboratory may need to be compensated for by using correction factors.

Carrier Injection — To prevent minority/majority carrier injection from influencing resistivity measurements, the voltage difference between the two voltage sensing terminals should be kept at less than 100mV, ideally 25mV, since the thermal voltage, kt/q, is approximately 26mV. The test current should be kept as low as possible without affecting the measurement precision.

Conclusion

The van der Pauw technique in conjunction with a parameter analyzer is a proven method for determining the resistivity of very small samples because geometric spacing of the contacts is unimportant. Hall effect measurements are important to semiconductor material characterization for determining conductivity type, carrier density, and mobility. Some parameter analyzers may include built-in configurable tests that include the necessary calculations.

For successful measurements, it’s important to consider potential sources of error including electronics interference, leakage current and environmental factor such as light and temperature. Resistivity can impact the characteristics of a device, serving as reminder of the importance of making accurate and repeatable measurements.

Solid particles in the abatement exhaust must be properly managed, and in some cases, substantially reduced from the gas stream before it is released into the environment.

BY CHRIS JONES, Edwards Vacuum, Ltd., Clevedon, U.K.

Many semiconductor manufacturing processes create solid particles in the process exhaust. Like other exhaust contaminants, these must be properly managed, and in many cases, removed from the stream before it is released into the environment. The permitted release levels vary for particles of different sizes and compositions, depending on their toxicity or potential to damage the environment. Regulations governing particle releases are evolving rapidly. However, the management of particulate flows in process exhaust is also important due to its potential impact on the process itself. Left unmanaged, particulate accumulations can result in shut downs for unplanned maintenance, excessive and premature wear and costly repairs, all of which directly affect the profitability of the manufacturing operation.

Solids may be formed in the exhaust stream of a semiconductor manufacturing process from a number of sources. One important source, though not the focus of this discussion, is the condensation of process gases in vacuum pump exhausts. If not controlled with a thermal management system (e.g. Smart TMS, Edwards) that maintains the pipe surfaces at a sufficiently high temperature, this condensation can quickly accumulate and force a halt to the manufacturing process. This article will discuss issues further downstream in the abatement process, where toxic volatile compounds are converted to more benign forms, some of which form solid particles that must then be removed from the exhaust gases. Many of these solids are oxides formed when gases, such as tungsten hexaflu- oride, silane, organo- and halo- silanes and others, are exposed to heat, air, and water. The particles are typically amorphous, i.e. non-crystalline. Many abatement processes use combustion to supply the heat needed to decompose toxic compounds and chemically convert them to a more harmless form. The particles thus formed have varying sizes and may be hydrophilic (formed from halosilanes), hydrophobic (formed from organsilanes) or mixed (mixed chlorides or silicon, aluminum and boron, for example), depending on the species combusted and the nature of the combustion process. Particle sizes can range from tens of nanometers to tens of microns. As shown in FIGURE 1, the size of the particles depends on, among other factors, the length of the combustion flame. Longer flames maintain the components at high temperature for a longer periods and result in the formation of larger particles.

FIGURE 1. A longer flame maintains the combusting components at higher temperature for a longer time and results in the formation of larger particles.

FIGURE 1. A longer flame maintains the combusting components at higher temperature for a longer time and results in the formation of larger particles.

The behavior of particles once released into the environment varies depending on their sizes. Coarse particles, with diameters ranging from 2.5μm to 10μm, result largely from processes such as erosion, agriculture, or mining and include crustal dust, pollens, fungal spores, biological debris and sea salt. Because of their large size, these particles persist in the atmosphere for only a few hours or days. Fine particles, which range from 2.5μm to 0.1μm and include the particles of concern in semiconductor manufacturing exhaust, may be the direct result of a combustion processes or may also be formed by photochemical reactions between volatile organic compounds (VOC) and oxides in the presence of sunlight. Fine particles can stay suspended in ambient air for days to weeks. Ultrafine particles, less than 0.1μm, are generated by high temperature combustion or formed from the nucleation of atmospheric gases. Ultrafine particles are quickly removed from the atmosphere (minutes to hours) via diffusion to surfaces or coagulation, adsorption and condensing into fine particles.

Regulatory environment

Regulations governing the release of particles into the atmosphere are developing quickly worldwide as scientists expand their knowledge of the particles’ impacts on health and the environment. In addition to regulations governing emissions by particle size, there are specific regulations regarding especially harmful species, such as heavy metals, carcinogens and toxics. For example, the presence of an adsorbed species, like hydrofluoric acid (HF), on oxide particles increases the toxicity of the parent material.

In 2013 the United States Environmental Protection Agency specified an average daily limit of 150μg/m3 for coarse particles and 35μg/m3 for fine particles, and an average annual limit of 12μg/m3 for fine particles (down from 15μg/m3 in 2006). China, as of 2012, imposed limits based on both particle size and type, with permitted daily levels for coarse particles of 50μg/m3 and 150μg/m3 for type I and type II, respectively and 35μg/m3 and 75μg/m3, respectively for fine particles. China also limits annual averages for both sizes and types. The European Commission, the World Health Organization and the Australian National Environmental Council, among others, all specify their own limits. It is clearly incumbent on manufacturers to know and satisfy their local regulations. [1]

Health considerations

The health of employees in manufacturing facilities and people living near manufacturing operations is clearly a high priority for our industry. Epidemiological studies have provided plausible evidence that exposure to particulate material (PM) can impact health in a number of ways, including pulmonary and systemic inflammation, oxidative stress response, protein modification, stimulation of the autonomic nervous system, exaggerated allergic reactions, pro-coagulation activity, and suppression of immune response in the lungs.

Some studies have provided good news as well, specifically, that the amorphous silica particles produced during the abatement of gases used in semiconductor manufacturing have much less impact on lung function than the crystalline silica particles more often encountered in mining and building industries. These studies looked specifically at the effects of pure silica particles, an important caveat. Silica and other dusts that may have acids, such as HF, adsorbed on the particle surface constitute substantially greater health risks than the simple oxide. Other particulate oxides also represent serious health challenges. These include oxides of antimony, arsenic, barium, chromium, cobalt, nickel, phosphorus, tellurium and selenium.

Abatement performance

Just as condensed material deposited in the vacuum lines can shut down the production process, the accumulation of combustion-generated particulates can degrade the performance of the whole facility. In a typical point-of-use (POU) abatement system, after combustion the exhaust gases pass through a series of operations designed to remove particulates and other by-products. In the example shown in FIGURE 2 these include a water weir, quench tanks, a packed-bed scrubber and an atomized spray. Atomizing spray systems, in particular, have been shown to improve solids removal performance from 50 to 75 percent. Blockages can occur at the damper, in duct spurs leading from the abatement to the main duct, in the main duct, before or within the scrubber. In addition to blockages, failure to remove particulate at the primary abatement unit can also lead to environmental discharges and visible plumes at stacks. Any blockage will result in a process shutdown for system maintenance, lasting from a few hours to an entire day.

FIGURE 2. The accumulation of combustion generated particulates can degrade abatement system performance.

FIGURE 2. The accumulation of combustion generated particulates can degrade abatement system performance.

Mitigation options

A number of approaches exist for removing particulates downstream of the abatement system. One solution does not fit all and it is important to pick the one that best addresses the specific challenges. FIGURE 3 shows performance characteristics for various technologies. For example, highly toxic particles may require much higher removal rates than less harmful particles.

FIGURE 3. Performance characteristics for various particle removal technologies downstream of the abatement system. Courtesy: Waste-to-Energy Research and Technology Council (greyed out area not relevant to solids).

FIGURE 3. Performance characteristics for various particle removal technologies downstream of the abatement system. Courtesy: Waste-to-Energy Research and Technology Council (greyed out area not relevant to solids).

Edwards’ standard solution (FIGURE 4) for POU removal of fine particles is a wet electrostatic precipitator (WESP). A WESP uses electrostatic forces to remove particles. It requires power, water and pneumatics and can remove up to 95 percent of silica particles at flow rates of 1m3/ min, 85% at 2m3/min. WESP technology can be scaled to handle an entire facility. In one example, Edwards partnered in the installation of a large scale dual WESP integrated with a packed-bed wet scrubber and designed it to meet the specific challenges of arsenic abatement. The system ultimately demonstrated a 99 percent removal rate to meet the stringent requirements of the Chinese government for this highly toxic substance.

FIGURE 4. POU WESP uses electrostatic forces to remove particulates from the exhaust stream. It can remove up to 95 percent of silica particles at a flow rate of 1m3/min.

FIGURE 4. POU WESP uses electrostatic forces to remove particulates from the exhaust stream. It can remove up to 95 percent of silica particles at a flow rate of 1m3/min.

Alternative technologies that may be appropriate, but have not been evaluated for use in the management of waste gases from semiconductor manufacturing, are the Rotoclone family (from AAF International). POU units handle flow rates of 30m3/min, removing >97 percent of 1μm particles and >99.8 percent of 10μm particles. Duct-based Rotoclones with flow rates up to 1250m3/ min remove as much as 86 percent of 1μm particles and 99 percent of 10μm particles. Rotoclones require power, water, pneumatics and a drain.

More conventionally, a Venturi scrubber can be configured for various flow and removal rates. As a rule, smaller units controlling a low concentration waste stream will be much more expensive per unit of volumetric flow than larger units cleaning high pollutant-load flows. Venturi scrubbers can handle mists and flammable or explosive dusts. They have relatively low maintenance requirements, are simple in design and easy to install. Their collection efficiency can be varied. They can cool hot gases and neutralize corrosive gases. They are susceptible to corrosion and must be protected from freezing. Treated gases may require reheating to avoid a visible water plume. The collected particulate material may be contaminated and not recyclable, requiring expensive disposal of the waste sludge.

Filtration is another alternative for particle removal. It is normally restricted to the management of dry dusts at flow rates of 5 to 250m3/min. Removal rates higher than 99.9 percent are achievable. We have seen a limited number of large filter installations for the removal of hydrophobic silica solids at relative humidities as high as 80 percent. It is not clear how the presence of hydrophilic powder might impact the performance of these facilities.

In cases of highly toxic particles, high efficiency air particle (HEPA) filters can provide very high removal rates, higher than 99.999 percent. However, HEPA filters are appropriate only for very low contaminant concentrations. Edwards has been partnering with third-party suppliers regarding HEPA filtration for highly toxic dusts such as those generated during arsine management. These solutions are often used for highly toxic materials so they are often designed with bag-in-bag-out capability to eliminate potential exposure of maintenance personnel to the removed contaminants. Typically, these critical installations are also designed as dual systems with auto turnover to allow continuous operation of one system while the redundant system is serviced. HEPA technology can scale from POU to full facility.

Conclusion

All of these technologies are available now, but not all have been demonstrated in semicon- ductor manufacturing. Semiconductor manufacturers have long used POU WESPs and Venturi scrubbers and are very familiar with HEPA filtration systems, but primarily for particulate removal for air conditioning. Conventional filters are in operation on flat panel display exhausts (mainly on burner only dry abated CVD processes). Some of the technologies we have described, however, have not been proven in semiconductor applications, but are well developed and widely accepted in other industries. Rotoclone systems, for instance, are UL and CE certified, but have not been SEMI qualified. As semiconductor manufacturing processes continue to evolve, it will behove manufacturers to stay current on available technol- ogies and consider alternatives as performance and cost requirements dictate.

References

1. Review of the health impacts of emission sources, types and levels of particulate matter air pollution in ambient air in NSW; December, 2015; Produced for the NSW Environment Protection Authority and NSW Ministry of Health, Environmental Health Branch.

Qualcomm to acquire NXP


October 27, 2016

Qualcomm Incorporated (NASDAQ:  QCOM) and NXP Semiconductors N.V. (NASDAQ:  NXPI) today announced a definitive agreement, unanimously approved by the boards of directors of both companies, under which Qualcomm will acquire NXP.  According to Qualcomm’s official press release, a subsidiary of Qualcomm will commence a tender offer to acquire all of the issued and outstanding common shares of NXP for $110.00 per share in cash, representing a total enterprise value of approximately $47 billion.

NXP is a developer of high-performance, mixed-signal semiconductor electronics, with products and solutions and leadership positions in automotive, broad-based microcontrollers, secure identification, network processing and RF power.  As a semiconductor solutions supplier to the automotive industry, NXP also has leading positions in automotive infotainment, networking and safety systems, with solutions designed into 14 of the top 15 infotainment customers in 2016.  NXP has a broad customer base, serving more than 25,000 customers through its direct sales channel and global network of distribution channel partners.

“With innovation and invention at our core, Qualcomm has played a critical role in driving the evolution of the mobile industry.  The NXP acquisition accelerates our strategy to extend our leading mobile technology into robust new opportunities, where we will be well positioned to lead by delivering integrated semiconductor solutions at scale,” said Steve Mollenkopf, CEO of Qualcomm Incorporated.  “By joining Qualcomm’s leading SoC capabilities and technology roadmap with NXP’s leading industry sales channels and positions in automotive, security and IoT, we will be even better positioned to empower customers and consumers to realize all the benefits of the intelligently connected world.”

The combined company is expected to have annual revenues of more than $30 billion, serviceable addressable markets of $138 billionin 2020 and leadership positions across mobile, automotive, IoT, security, RF and networking.  The transaction has substantial strategic and financial benefits:

  • Complementary technology leadership in strategically important areas: The transaction combines leadership in general purpose and automotive grade processing, security, automotive safety sensors and RF; enabling more complete system solutions.
    • Mobile: A leader in mobile SoCs, 3G/4G modems and security.
    • Automotive: A leader in global automotive semiconductors, including ADAS, infotainment, safety systems, body and networking, powertrain and chassis, secure access, telematics and connectivity.
    • IoT and Security: A leader in broad-based microcontrollers, secure identification, mobile transactions, payment cards and transit; strength in application processors and connectivity systems.
    • Networking: A leader in network processors for wired and wireless communications and RF sub-segments, Wave-2 11ac/11ad, RF power and BTS systems.
  • Enhanced go-to-market capabilities to serve our customers:  The combination of Qualcomm’s and NXP’s deep customer and ecosystem relationships and distribution channels enables the ability to deliver leading products and platforms at scale in mobile, automotive, IoT, industrial, security and networking.
  • Shared track record of innovation and commitment to operational discipline: Both companies have demonstrated a strong commitment to technology leadership and best-in-class product portfolios with focused investments in R&D.  Qualcomm and NXP have both taken action to position themselves for profitable growth, while maintaining financial and operational discipline.  
  • Substantial financial benefits: Qualcomm expects the transaction to be significantly accretive to non-GAAP EPS immediately upon close.  Qualcomm expects to generate $500 million of annualized run-rate cost synergies within two years after the transaction closes.  The transaction utilizes Qualcomm’s strong balance sheet and will be efficiently financed with offshore cash and new debt. The transaction structure allows tax efficient use of offshore cash flow and enables Qualcomm to reduce leverage rapidly.

Mollenkopf continued, “We have taken significant action to build a foundation for profitable growth and the acquisition of NXP is strongly aligned with our strategy.  Our companies both have substantial expertise in delivering industry-leading solutions to our global customers, built upon a shared commitment to technology innovation, focused R&D investments and strong financial and operational discipline.”

“The combination of Qualcomm and NXP will bring together all technologies required to realize our vision of secure connections for the smarter world, combining advanced computing and ubiquitous connectivity with security and high performance mixed-signal solutions including microcontrollers. Jointly we will be able to provide more complete solutions which will allow us to further enhance our leadership positions, and expand the already strong partnerships with our broad customer base, especially in automotive, consumer and industrial IoT and device level security,” said Rick Clemmer, NXP Chief Executive Officer. “United in a common strategy, the complementary nature of our technologies and the scale of our portfolios will give us the ability to drive an accelerated level of innovation and value for the whole ecosystem. Such a strong fit will bring opportunities for our employees and customers, as well as provide immediate attractive value for our shareholders, in creating the semiconductor industry powerhouse.”

Sir Peter Bonfield, Chairman of NXP’s Board of Directors, said, “This is a major step in my ten years’ Chairmanship of NXP, and I am very pleased to see that the board of NXP has unanimously approved the proposed transaction and fully supports and recommends the offer for acceptance to NXP shareholders.”

Gigaphoton Inc., a manufacturer of light sources used in lithography, has announced success in achieving a world record 5% conversion efficiency with 100W of average output in stable operation and a high duty rate of 95%. This comes as a result of perfecting a pilot light source1 designed for operation in semiconductor mass production lines that utilize Laser-Produced Plasma (LPP) light sources for EUV scanners, which the company is currently engaged in developing.

To date, Gigaphoton has developed a number of innovative technologies and improvements, which include sub 20 μm micro droplet supply technology; a high luminous-quality main pulse beam that combines an improved solid-state pre-pulse laser with a newly introduced Mitsubishi Electric product designated as a high frequency discharge excitation-type three-axis orthogonal CO2 laser amplifier; improvements in energy control technology; and a debris removal technology developed by Gigaphoton that operates via magnetic fields. These advancements have all contributed to accomplishing 130W or better continuous operation on a prototype machine, an achievement announced earlier this year in July. This latest pilot light source incorporates these new technologies in a system designed based on the assumption of integrating an EUV scanner.

The pilot light source has successfully achieved 5% conversion efficiency with 105W of average output in stable operation and a high duty rate of 95% (a rate that measures light emission time versus operating time), which is a more demanding workload than the prototype underwent. This is in line with the 100W average output that governs throughput in semiconductor production, and is considered a performance level that exceeds the requirements of users today. The success achieved in this operational demonstration confirms that the realization of cutting edge semiconductor production lines is just around the corner.

Hakaru Mizoguchi, Vice President & CTO of Gigaphoton says,　”Our success in achieving a world record 5% conversion efficiency while attaining a 100W average output in stable operation and high duty rate of 95% with our pilot light source―which is designed to operate in state-of-the-art semiconductor mass production lines―shows that we are very close to the market introduction stage for EUV light sources that will be capable of delivering stable operation, high output, and low running costs. We are confident that Gigaphoton’s advanced technological capabilities and development efforts will not only accelerate the development of EUV scanners for mass production, which is the next generation of technology in lithography, but will also support overall development in the semiconductor industry and contribute to the realization of an IoT based society.”