Tag Archives: letter-wafer-top

SEMI recently completed its annual silicon shipment forecast for the semiconductor industry. This forecast provides an outlook for the demand in silicon units for the period 2016–2018. The SEMI forecast shows polished and epitaxial silicon shipments totaling 10,444 million square inches in 2016; 10,642 million square inches in 2017; and 10,897 million square inches in 2018 (refer to table below). Total wafer shipments this year are expected to exceed the market high set in 2015 and are forecast to continue shipping at record levels in 2017 and 2018.

“Silicon shipment volumes have been gaining strength in recent months, after a soft start at the beginning of the year,” said Denny McGuirk, president and CEO of SEMI. “This positive momentum is expected to continue and result in modest annual growth for the segment this year, 2017 and into 2018.”

2016 Silicon Shipment Forecast

Total Electronic Grade Silicon Slices* – Does not Include Non-Polished Wafers

(Millions of Square Inches, MSI)

Actual

Forecast

2014

2015

2016

2017

2018

MSI

9,826

10,269

10,444

10,642

10,897

Annual Growth

11%

5%

2%

2%

2%

Source: SEMI, October 2016

* Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

Total wafer demand is expected to return to historical growth rates over the next five years. However, what is uncharacteristic of the past is the wide range of decline and growth that will be logged by specific product categories and technologies. Semico’s recent report Semico Wafer Demand Model Update Q3 2016 indicates that the compound annual growth rates by detailed product breakouts range from a -4.1% decrease all the way up to 11.3% growth, exemplifying the diverse applications within the semiconductor industry.

“The products experiencing growth or decline have a significant impact on the need for certain types of production capacity such as 200mm versus 300mm; logic, memory or other; and advanced versus mature process technology”, says Joanne Itow, Managing Director Manufacturing for Semico. “The process technologies covered in wafer demand model ranges from >1000nm down to 7nm.”

Key findings include:

* Semiconductor revenues are expected to fall 2.5% in 2016
* Total wafer demand in 2016 is expected to exceed 100 million 300mm wafer equivalents
* The main reason for the increase in wafer demand in 2016 is due to continued increases in Other MOS Logic (Automotive, Consumer, Audio, etc.), NAND, DRAM, Discretes/Sensors and Optoelectronics
* DRAM chip revenue is expected to decline 14.7% in 2016
Semico Research’s report, Semico Wafer Demand Model Update Q3 2016, study number MA112-16 , includes an excel spreadsheet which provides wafer demand by 18 product categories and 14 technology nodes over a 10 year time frame from 2010 to 2020. There is also a summary write-up which provides insight into the recent changes compared to the previous quarter.

Other data contained in the report:
* Wafer demand by product (discrete/sensor, Opto, Analog, Communications, MCU, MPU, DRAM, NAND, NOR, SRAM, etc.) by process node (≥1000nm-7nm)
* Silicon wafer shipments from 2010-2020

200mm fabs on the rise


October 11, 2016

One year after the debut of the industry’s first 200mm Fab Outlook report, SEMI has issued an October 2016 update, with the improved and expanded report forecasting 200mm fab trends out to 2020.  This extensive report features trends from 2009 to 2020, showing how 200mm fab activities and capacity have changed worldwide.  SEMI’s analysts updated information on almost 200 facilities, including new facilities and closures of existing facilities.

Examining 200mm capacity over the years, the highest level of 200mm capacity was recorded in 2007 and the lowest following this peak in 2009 (see figure). The capacity decline from 2007 to 2009 was driven by the 2008/2009 global financial crisis, which caused the closure of many facilities, and the transition of memory and MPU fabrication to 300mm fabs from 200mm.

Global_200mm_chart_700px

Since 2009, installed 200mm fab capacity has increased, and by 2020, 200mm capacity is expected to reach 5.5 million wafers per month (wpm), though still less than the 2007 peak.  According to SEMI’s data, by 2019, installed capacity will reach close to 5.38 million wpm, almost as high as capacity in 2006.  From 2015 to 2020, 200mm facilities are forecast to add 618,000 wpm net capacity. This increase is a combination of fabs adding capacity and fabs losing capacity

Two applications account for the growing demand for 200mm: mobile devices and IoT. Rising fab capacity from 2015 to 2020 will be driven by MEMS devices, Power, Foundry and Analog.  By region, the greatest increases in capacity are expected to be in China, Southeast Asia, Americas, and Taiwan. Another trend is also observed: 200mm fabs are increasing the capacity to provide process capability below 120nm. Higher capacity does not mean more fabs, but fewer, larger fabs. In fact, the number of fabs in 2020 is almost the same as the count seen in 2009.  So 2020 capacity heads toward industry highs while in comparison 2009 had the lowest levels off the 2007 peak.

The Global 200mm Fab Outlook to 2020, published by SEMI in October 2016, includes two files: a 92-page pdf file featuring trend charts, tables and summaries and an Excel file covering 2009 to 2020 detailing on quarterly basis and fab-by-fab developments.

Enormous financial and technology hurdles continue to plague the development of 450mm wafers. Ambitious goals to put 450mm wafers to use have been scaled back.  IC manufacturers are instead maximizing their manufacturing efficiency using 300mm and 200mm wafers.  IC Insights’ Global Wafer Capacity 2016-2020 report shows that worldwide capacity by wafer size was dominated by 300mm wafers in 2015 and is forecast to continue increasing through 2020 (Figure 1).

Figure 1

Figure 1

  • 300mm wafers represented 63.1% of worldwide capacity at the end of 2015 and are forecast to increase to about 68% by the end of 2020.
  • The share of the industry’s monthly wafer capacity represented by 200mm wafers is expected to drop from 28.3% in 2015 to 25.3% in 2020. But, 200mm wafer capacity is predicted to increase every year over the next several years.
  • Capacity for wafers of ≤150mm diameter is forecast to remain relatively flat during the forecast period.

The number of 300mm wafer fabrication facilities in operation is forecast to keep increasing through 2020 (Figure 2). For the most part, 300mm fabs are, and will continue to be, limited to production of high-volume, commodity-type devices like DRAMs and flash memories; image sensors and power management devices; and complex logic and microcomponent ICs with large die sizes; and by foundries, which can fill a 300mm fab by combining wafer orders from many sources.

Figure 2

Figure 2

  • The number of active volume-production 300mm fabs declined for the first time in 2013. A few fabs that were scheduled to open in 2013 were delayed until 2014. In addition, two large 300mm fabs owned by ProMOS closed in 2013.
  • At the end of 2015, there were 95 production-class IC fabs utilizing 300mm wafers (there are numerous R&D IC fabs and a few high-volume fabs around the globe that make “non-IC” products using 300mm wafers, but these are not included in the count).
  • Currently, there are eight 300mm wafer fabs scheduled to open in 2017, which would be the highest number in one year since 2014 when nine were added.
  • By the end of 2020 there are expected to be 22 more fabs in operation, bringing the total number of 300mm fabs used for IC fabrication to 117. The peak number of 300mm fabs may be somewhere around 125. For comparison, the most volume-production 200mm wafer fabs in operation was 210 (in December 2015 there were 148).

KLA-Tencor Corporation (NASDAQ:  KLAC) and Lam Research Corp. (NASDAQ:  LRCX) today announced that they have agreed to terminate their proposed merger agreement. The parties decided to it was not in the best interests of their respective stakeholders to continue pursuing the merger after the U.S. Department of Justice advised KLA-Tencor and Lam Research that it would not continue with a consent decree that the parties had been negotiating. No termination fees will be payable by either the Company or Lam Research in connection with the termination of the Merger Agreement.

“Although we are disappointed with this outcome, KLA-Tencor’s performance over the past several quarters demonstrates the Company is executing our strategies at a high level and creating compelling value for the industry and for our stockholders,” commented Rick Wallace, President and Chief Executive Officer of KLA-Tencor.

“Today our customer engagement and market leadership is strong and KLA-Tencor is delivering superior financial results. Growth and earnings momentum is expected to continue as we go forward, fueled by new products in the marketplace today, and with many more products in the pipeline,” continued Mr. Wallace. “Additionally, our collaboration over the past year with Lam Research and with our customers has affirmed the value of closer cooperation between process and process control for new, enabling solutions. For that reason, we plan to explore collaboration opportunities with Lam Research around programs identified as beneficial to our customers.”

After the initial announcement of the proposed merger, which was expected to close mid-year 2016, analysts voiced concern over whether the deal would be approved. Robert Maire of Semiconductor Advisors wrote: “We think this is going to be the obvious biggest issue after the failed AMAT & TEL merger.  We think there will likely be opposition in the semi industry but probably less so than we heard the screaming related to AMAT/TEL.”

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $28.0 billion for the month of August 2016, an increase of 3.5 percent compared to the previous month’s total of $27.1 billion and an uptick of 0.5 percent over the August 2015 total of $27.9 billion. August marked the market’s largest month-to-month growth since May 2013 and its first year-to-year growth since June 2015. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Following months of sluggish global semiconductor sales, the global market recently has shown signs of a rebound, punctuated by solid growth in August,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Americas market was particularly encouraging, topping 6 percent month-to-month growth for the first time in nearly three years to lead all regional markets. China also stood out, posting by far the strongest year-to-year growth of all regions in August. All told, global sales are still behind last year’s pace, but appear to be on the right track as 2017 draws closer.”

Month-to-month sales increased across all regions: the Americas (6.3 percent), Japan (4.8 percent), China (3.1 percent), Asia Pacific/All Other (2.7 percent), and Europe (0.7 percent). Year-to-year sales increased in China (7.1 percent) and Japan (2.2 percent), but fell in Asia Pacific/All Other (-2.7 percent), the Americas (-3.1 percent), and Europe (-3.3 percent).

 

August 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.10

5.43

6.3%

Europe

2.70

2.71

0.7%

Japan

2.60

2.73

4.8%

China

8.56

8.82

3.1%

Asia Pacific/All Other

8.12

8.34

2.7%

Total

27.08

28.03

3.5%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.60

5.43

-3.1%

Europe

2.81

2.71

-3.3%

Japan

2.67

2.73

2.2%

China

8.23

8.82

7.1%

Asia Pacific/All Other

8.57

8.34

-2.7%

Total

27.88

28.03

0.5%

Three-Month-Moving Average Sales

Market

Mar/Apr/May

Jun/Jul/Aug

% Change

Americas

4.79

5.43

13.2%

Europe

2.63

2.71

3.3%

Japan

2.55

2.73

6.9%

China

8.09

8.82

9.0%

Asia Pacific/All Other

8.00

8.34

4.2%

Total

26.07

28.03

7.5%

IC Insights recently released its September Update to the 2016 McClean Report. This Update included Part 2 of an extensive analysis of the IC foundry business. An excerpt from the September Update, describing foundry sales by feature size, is shown below.

Figure 1

Figure 1

TSMC has long been the technology leader among the major pure-play foundries. As shown in Figure 1, 54% of TSMC’s 2016 revenue is expected to come from <40nm processing. GlobalFoundries, which has dedicated a large portion of its capacity to making advanced processors over the past few years, also generates a large portion of its sales based on leading-edge process technology and feature sizes. In 2016, 52% of GlobalFoundries’ sales are forecast to come from <40nm production.

Although GlobalFoundries and TSMC are forecast to have a similar share of their sales dedicated to <40nm technology this year, TSMC is expected to have almost 6x the sales volume at <40nm as compared to GlobalFoundries in 2016 ($15.6 billion for TSMC and $2.6 billion for GlobalFoundries). In contrast, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production.

Because TSMC has a very large percentage of its sales targeting <40nm production, its revenue per wafer is forecast to increase at a CAGR of 3% from 2011 through 2016 as compared to a -1% CAGR expected for the total revenue per wafer average of GlobalFoundries, UMC, and SMIC over this same timeperiod. Only 2% of SMIC’s 2016 sales are expected to come from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so low as compared to TSMC and GlobalFoundries.

It is interesting to note that the increase in pure-play foundry sales this year is forecast to be almost entirely due to <40nm feature size device sales (Figure 2). Although it is expected to represent 60% of total pure-play foundry sales in 2016, the ≥40nm pure-play IC foundry market is forecast to be flat this year. In contrast, the leading-edge <40nm pure-play foundry market in 2016 is expected to surge by 23%, increasing by a hefty $3.6 billion.

Figure 2

Figure 2

By David W. Price and Douglas G. Sutherland

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which examined the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing. 

Introduction

In a previous Process Watch article [1], we showed that big excursions are usually easy to detect but finding small excursions requires a combination of high capture rate and low noise. We also made the point that, in our experience, it’s usually the smaller excursions which end up costing the fab more in lost product. Catastrophic excursions have a large initial impact but are almost always detected quickly. By contrast, smaller “micro-excursions” sometimes last for weeks, exposing hundreds or thousands of lots to suppressed yield.

Figure 1 shows an example of a micro-excursion. For reference, the top chart depicts what is actually happening in the fab with an excursion occurring at lot number 300. The middle chart shows the same excursion through the eyes of an effective inspection strategy; while there is some noise due to sampling and imperfect capture rate, it is generally possible to identify the excursion within a few lots. The bottom chart shows how this excursion would look if the fab employed a compromised inspection strategy—low capture rate, high capture rate variability, or a large number of defects that are not of interest; in this case, dozens of lots are exposed before the fab engineer can identify the excursion with enough confidence to take corrective action.

Figure 1. Illustration of a micro-excursion. Top: what is actually happening in the fab. Middle: the excursion through the lens of an effective control strategy (average 2.5 exposed lots). Bottom: the excursion from the perspective of a compromised inspection strategy (~40 exposed lots).

Figure 1. Illustration of a micro-excursion. Top: what is actually happening in the fab. Middle: the excursion through the lens of an effective control strategy (average 2.5 exposed lots). Bottom: the excursion from the perspective of a compromised inspection strategy (~40 exposed lots).

Unfortunately, the scenario depicted in the bottom of Figure 1 is all too common. Seemingly innocuous cost-saving tactics such as reduced sampling or using a less sensitive inspector can quickly render a control strategy to be ineffective [2]. Moreover, the fab may gain a false sense of security that the layer is being effectively monitored by virtue of its ability to find the larger excursions. 

Micro-Excursions 

Table 1 illustrates the difference between catastrophic and micro-excursions. As the name implies, micro-excursions are subtle shifts away from the baseline. Of course, excursions may also take the form of anything in between these two.

Table 1: Catastrophic vs. Micro-Excursions

Table 1: Catastrophic vs. Micro-Excursions

Such baseline shifts happen to most, if not all, process tools—after all, that’s why fabs employ rigorous preventative maintenance (PM) schedules. But PM’s are expensive (parts, labor, lost production time), therefore fabs tend to put them off as long as possible.

Because the individual micro-excursions are so small, they are difficult observe from end-of-line (EOL) yield data. They are frequently only seen in EOL yield data through the cumulative impact of dozens of micro-excursions occurring simultaneously; even then it more often appears to be baseline yield loss. As a result, fab engineers sometimes use the terms “salami slicing” or “penny shaving” since these phrases describe how a series of many small actions can, as an accumulated whole, produce a large result [3].

Micro-excursions are typically brought to an end because: (a) a fab detects them and puts the tool responsible for the excursion down; or, (b) the fab gets lucky and a regular PM resolves the problem and restores the tool to its baseline. In the latter case, the fab may never know there was a problem.

The Superposition of Multiple Simultaneous Micro-Excursions

To understand the combined impact of these multiple micro-excursions, it is important to recognize:

  1. Micro-excursions on different layers (different process tools) will come and go at different times
  2. Micro-excursions have different magnitudes in defectivity or baseline shift
  3. Micro-excursions have different durations

In other words, each micro-excursion has a characteristic phase, amplitude and wavelength. Indeed, it is helpful to imagine individual micro-excursions as wave forms which combine to create a cumulative wave form. Mathematically, we can apply the Principle of Superposition [4] to model the resulting impact on yield from the contributing micro-excursions.

Figure 2 illustrates the cumulative effect of one, five, and 10 micro-excursions happening simultaneously in a 1,000 step semiconductor process. In this case, we are assuming a baseline yield of 90 percent, that each micro-excursion has a magnitude of 2 percent baseline yield loss, and that they are detected on the 10th lot after it starts. As expected, the impact of a single micro-excursion is negligible but the combined impact is large.

Figure 2. The cumulative impact of one, five, and 10 simultaneous micro-excursions happening in a 1,000 step process: increased yield loss and yield variation.

Figure 2. The cumulative impact of one, five, and 10 simultaneous micro-excursions happening in a 1,000 step process: increased yield loss and yield variation.

It is interesting to note that the bottom curve in Figure 2 would seem to suggest that the fab is suffering from a baseline yield problem. However, what appears to be 80 percent baseline yield is actually 90 percent baseline yield with multiple simultaneous micro-excursions, which brings the average yield down to 80 percent. This distinction is important since it points to different approaches in how the fab might go about improving the average yield. A true baseline yield problem would suggest that the fab devote resources to run experiments to evaluate potential process improvements (design of experiments (DOEs), split lot experiments, failure analysis, etc.). These activities would ultimately prove frustrating as the engineers would be trying to pinpoint a dozen constantly-changing sources of yield loss.

The fab engineer who correctly surmises that this yield loss is, in fact, driven by micro-excursions would instead focus on implementing tighter process tool monitoring strategies. Specifically, they would examine the sensitivity and frequency of process tool monitor inspections; depending on the process tool, these monitors could be bare wafer inspectors on blanket wafers and/or laser scanning inspectors on product wafers. The goal is to ensure these inspections provide timely detection of small micro-excursions, not just the big excursions.

The impact of an improved process tool monitoring strategy can be seen in Figure 3. By improving the capture rate (sensitivity), reducing the number of non-critical defects (by doing pre/post inspections or using an effective binning routine), and reducing other sources of noise, the fab can bring the exposed product down from 40 lots to 2.5 lots. This, in turn, significantly reduces the yield loss and yield variation.

Figure 3. The impact of 10 simultaneous micro-excursions for the fab with a compromised inspection strategy (brown curve, ~40 lots at risk), and a fab with an effective process tool monitoring strategy (blue curve, ~2.5 lots at risk).

Figure 3. The impact of 10 simultaneous micro-excursions for the fab with a compromised inspection strategy (brown curve, ~40 lots at risk), and a fab with an effective process tool monitoring strategy (blue curve, ~2.5 lots at risk).

Summary

Most fabs do a good job of finding the catastrophic defect excursions. Micro-excursions are much more common and much harder to detect. There are usually very small excursions happening simultaneously at many different layers that go completely undetected. The superposition of these micro-excursions leads to unexplained yield loss and unexplained yield variation.

As a yield engineer, you must be wary of this. An inspection strategy that guards only against catastrophic excursions can create the false sense of security that the layer is being effectively monitored—when in reality you are missing many of these smaller events that chip away or “salami slice” your yield.

References:

About the Author: 

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

IC Insights recently released its September Update to the 2016 McClean Report. This Update included Part 2 of an extensive analysis of the IC foundry industry and a look at the current state of the merger and acquisition surge in the semiconductor industry. An excerpt from the M&A portion of this Update is shown below.

After an historic surge in semiconductor merger and acquisition agreements in 2015, the torrid pace of transactions has eased (until recently), but 2016 is already the second-largest year ever for chip industry M&A announcements, thanks to three major deals struck in 3Q16 that have a combined total value of $51.0 billion. As of the middle of September, announced semiconductor acquisition agreements this year have a combined value of $55.3 billion compared to the all-time high of $103.8 billion reached in all of 2015 (Figure 1). Through the first three quarters of 2015, semiconductor acquisition pacts had a combined value of about $79.1 billion, which is 43% higher than the total of the purchasing agreements reached in the same period of 2016, based on M&A data compiled by IC Insights.

In many ways, 2016 has become a sequel to the M&A mania that erupted in 2015, when semiconductor acquisitions accelerated because a growing number of suppliers turned to purchase agreements to offset slower growth in major existing end-use equipment applications (such as smartphones, PCs, and tablets) and to broaden their businesses to serve huge new market potentials, including the Internet of Things (IoT), wearable electronics, and strong segments in embedded electronics, like highly-automated automotive systems. China’s goal of boosting its domestic IC industry is also driving M&A. In the first half of 2016, it appeared the enormous wave of semiconductor acquisitions in 2015 had subsided substantially, with the value of transactions announced between January and June being just $4.3 billion compared to $72.6 billion in the same six-month period in 1H15. However, three large acquisition agreements announced in 3Q16, including SoftBank’s purchase of ARM, Analog Devices’ intended purchase of Linear Technology, and Renesas’ potential acquisition of Intersil) have insured that 2016 will be second only to 2015 in terms of the total value of announced semiconductor M&A transactions.

Figure 1

Figure 1

A major difference between the huge wave of semiconductor acquisitions in 2015 and the nearly 20 deals being struck in 2016 is that a significant number of transactions this year are for parts of businesses, divisions, product lines, technologies, or certain assets of companies.  This year has seen a surge in the agreements in which semiconductor companies are divesting or filling out product lines and technologies for newly honed strategies in the second half of this decade.

Solid State Technology announced today that its premier semiconductor manufacturing conference and networking event, The ConFab, will be held at the iconic Hotel del Coronado in San Diego on May 14-17, 2017. A 30% increase in attendance in 2016 with a similar uplift expected in 2017, makes the venue an ideal meeting location as The ConFab continues to expand.

    

For more than 12 years, The ConFab, an invitation-only executive conference, has been the destination for key industry influencers and decision-makers to connect and collaborate on critical issues.

“The semiconductor industry is maturing, yet opportunities abound,” said Pete Singer, Editor-in-Chief of Solid State Technology and Conference Chair of The ConFab. “The Internet of Things (IoT) is exploding, which will result in a demand for “things” such as sensors and actuators, as well as cloud computing. 5G is also coming and will be the key technology for access to the cloud.”

The ConFab is the best place to seek a deeper understanding on these and other important issues, offering a unique blend of market insights, technology forecasts and strategic assessments of the challenges and opportunities facing semiconductor manufacturers. “In changing times, it’s critical for people to get together in a relaxed setting, learn what’s new, connect with old friends, make new acquaintances and find new business opportunities,” Singer added.

Dave Mount

David Mount

Solid State Technology is also pleased to announce the addition of David J. Mount to The ConFab team as marketing and business development manager. Mount has a rich history in the semiconductor manufacturing equipment business and will be instrumental in guiding continued growth, and expanding into new high growth areas.

Mainstream semiconductor technology will remain the central focus of The ConFab, and the conference will be expanded with additional speakers, panelists, and VIP attendees that will participate from other fast growing and emerging areas. These include biomedical, automotive, IoT, MEMS, LEDs, displays, thin film batteries, photonics and advanced packaging. From both the device maker and the equipment supplier perspective, The ConFab 2017 is a must-attend networking conference for business leaders.

The ConFab conference program is guided by a stellar Advisory Board, with high level representatives from GLOBALFOUNDRIES, Texas Instruments, TSMC, Cisco, Samsung, Intel, Lam Research, KLA-Tencor, ASE, NVIDIA, the Fab Owners Association and elsewhere.

Details on the invitation-only conference are at: www.theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at [email protected]. For details on attending as a guest or qualifying as a VIP, contact Sally Bixby at [email protected].