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A look at control of process uniformity across the wafer during plasma etch processes.

BY STEPHEN HWANG and KEREN KANARIK, Lam Research Corporation, Fremont, CA

Controlling process variability to achieve repeatable results has always been important for meeting yield and device performance requirements. With every advance in technology and change in design rule, tighter process controls are needed. In all of these cases, there are multiple sources of variability, often generalized as: within die, across wafer, wafer to wafer, and chamber to chamber. Typically, less than one third of the overall variation is allowed for variation across the wafer. For example, at the 14 nm node, the allowable variation for gate critical dimensions (CDs) is less than 2.4 nm, of which only about 0.84 nm is allowed for variation across the wafer [1]. At the 5 nm node, the allowable variation across the wafer may be less than 0.5 nm, or equivalent to two or three silicon atoms. In this article, we will discuss control of process uniformity across the wafer during plasma etch processes, its evolution in the industry, and some key focus areas.

A fundamental challenge in controlling uniformity in etch processes is the complexity of a plasma. Achieving the desired etch result (e.g., post-etch profile with selectivity to different film materials) requires managing the ratio of different ions and neutrals (e.g., Ar+, C4F8, C4F6+, O, O2+). Since the same plasma generates both types of species, the relative amount of ions to neutrals is strongly coupled. As a result, the impact of parameters typically used to control the plasma (e.g., source power and chamber pressure) are also interdependent.

Improving uniformity through design

Since the start of single-wafer processing in the early 1980s, etch chambers have been designed to produce similar plasma conditions on every location on the wafer to achieve uniform process results. This is especially challenging since there can be inherent electrical and chemical discontinuities at the edge (FIGURE 1) that affect uniformity across the wafer. Voltage gradients are created at the wafer edge due to the change from a biased surface to a grounded or floating surface. This bends the plasma sheath at the wafer edge, which changes the trajectory of ions relative to the wafer. The chemical potential discontinuity is analogous and produces concentration gradients for different species across the wafer. The gradients are caused by multiple phenomena, including variation in reactant consumption and by-products emissions rates at the center relative to the edge, as well as differences in temperature between the chamber and wafer that cause different absorption rates of chemical species.

Lam_Research_Figure_01

FIGURE 1. Discontinuities caused by the wafer edge create gradients that impact uniformity across the surface, with a significant impact at the edge.

 

Many chamber design changes have been implemented over the years to improve radial symmetry (FIGURE 2a). For example, a key hardware parameter for capacitively coupled plasma (CCP) chambers is the gap between the cathode and anode. Historically, the gap would be designed to provide the most uniform etch for a given power, pressure, and mixture of gas chemistries. On inductively coupled plasma (ICP) chambers, the gas injection location was a key design feature that would vary by process. In aluminum etch chambers, the reactant gas was delivered from a showerhead above the wafer. For silicon etch, the reactant gases were injected from around the perimeter of the wafer, but then evolved so that the gas was injected from above the center of the wafer.

FIGURE 2. Process non-uniformity has both radial and non- radial components (A). On a wafer map showing overall non- uniformity, removal of radial asymmetry allows isolating the more challenging non-radial component (B).

FIGURE 2. Process non-uniformity has both radial and non- radial components (A). On a wafer map showing overall non- uniformity, removal of radial asymmetry allows isolating the more challenging non-radial component (B).

With continuous optimization of chamber design, non-radial patterns became more apparent. On a uniformity map, the average of all the points within every radius can be taken and subtracted from the map, which leaves the more difficult asymmetric portion (FIGURE 2b). With this awareness, focus shifted toward elimi- nating asymmetries in the chamber design.

In retrospect, some of these improvements seem obvious. For instance, up to the late 1990s, it was not uncommon to have etch chambers with the turbomolecular pump located to the side of the wafer. This design created a side- to-side pattern due to the convective flow of reactants and by-products laterally across the wafer. By moving the pumps under the wafer, the flow became radially symmetric, thereby eliminating the process asymmetry.

In other cases, the source of asymmetry was more subtle. One interesting non-uniformity corrected with design was a problematic side-to-side pattern on the wafer that had a seemingly random orien- tation chamber-to-chamber. After extensive investigation to eliminate possible sources in the chamber hardware, the pattern was correlated with the Earth’s magnetic field (FIGURE 3). This example demon- strates the sensitivity of plasma processes, even to minor external influences. Although not specifically a chamber issue, the problem was corrected by applying special shielding with high magnetic-permeability materials around the chamber.

FIGURE 3. Non-uniformity induced by the Earth’s magnetic field was identified in an etch process (A). Applying magnetic shielding corrected the problem and provided uniform etch results (B).

FIGURE 3. Non-uniformity induced by the Earth’s magnetic field was identified in an etch process (A). Applying magnetic shielding corrected the problem and provided uniform etch results (B).

 

Development of process tuning capabilities

As etch processes became more varied and complex, fixed chamber designs were not sufficiently flexible to meet increasingly stringent requirements since it was not practical to provide a specific uniformity kit optimized for each etch process. Moreover, it was more challenging to achieve uniform results when etch technology transitioned from processing 200 mm to 300 mm wafers in the early 2000s. As a result, tuning capabilities were developed to deliver the uniformity control needed for a wide range of processes and larger wafer sizes.

By the early 2000s, the first uniformity tuning knobs focused on controlling the chemistry over the wafer. This was done in several ways, for example by splitting the main reactant gases into different locations or by adding tuning gases at separate locations from the main reactant gas. Since then, a number of tunable parameters have been identified for etch processes (Table 1). Ideally, orthogonal (independent) tuning knobs are used in order to match compensation as closely as possible to root causes. This provides the greatest impact on the process while limiting impact on other parameters. For example, in many dielectric etch processes, the etch rate is limited by the flux of ions from the plasma. Since gas injection doesn’t significantly impact plasma density uniformity, Lam Research developed tunable gap technology for CCP chambers to achieve uniform flux of ions across the wafer for a given set of process conditions.

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Over the years, continued development has focused on increasing the spatial resolution for better control across the wafer. For example, gas was at first only injected from the center location above the wafer. Then, additional capability was added that allowed controlling the ratio of gas directed to the center or edge of the wafer. Several years later, an additional gas injection location was added around the periphery of the wafer. To use wafer temperature as a control knob, different heating or cooling zones can be added to an electrostatic chuck (ESC), which holds the wafer. Historically, the number of temperature zones has increased from one to two (by 2002) to four radial zones (by 2006) to improve the radial uniformity of CDs. Since temperature directly affects CD uniformity (CDU), this is an effective way to tackle one of the most critical uniformity challenges.

Some of the most complex process flows today rely on these sophisticated tuning capabilities. Innovations that drive continuous scaling, such as 3D FinFET devices, advanced memory schemes, and double/quadruple patterning techniques, add to the challenge of reducing variability due to the increasing number of steps within the integration flows. Even if the uniformity for individual unit processes (including etch) are relatively good, their combined impact can be significant, and there is need to compensate somewhere in the flow.

When the uniformity profile of a step in the sequence, upstream or downstream, is known and difficult to correct, the profile of an etch step can be modified. For example, if one step is center fast, etch can compensate by being edge fast. This may sound simple, but it is actually quite difficult to achieve the level of process control that can essentially provide a mirror image of the non-uniformity in another process. Fortunately, plasma etch is one process that has matured to being capable of this level of control.

Uniformity control today

After many years of innovation, uniformity control capabilities now have the following characteristics:
• A high degree of granularity (numerous independent tuning locations across the wafer)
• Active tuning of both radial and non-radial patterns
• The ability to compensate for non-unifor- mities upstream and downstream of the etch process

One strategy being used at Lam to achieve the degree of control now needed is providing numerous independent heaters or micro-zones to control the wafer temperature, which is a critical parameter impacting CD uniformity. For example, using more than 100 localized heaters on one etch chamber delivers significantly higher spatial resolution than a system using only two or four heater zones for the entire wafer. Control of numerous individual heaters tunes both radial and non-radial patterns, whereas only center-middle-edge tuning was possible in previous generations (FIGURE 4).

FIGURE 4. Active uniformity control has evolved from limited radial tuning of large areas of the wafer to independent tuning of ever smaller regions across the wafer, enabling control of both radial and non-radial uniformity.

FIGURE 4. Active uniformity control has evolved from limited radial tuning of large areas of the wafer to independent tuning of ever smaller regions across the wafer, enabling control of both radial and non-radial uniformity.

With such high granularity, it is challenging for an individual engineer to manually determine the appropriate settings for so many heaters that will achieve a target thermal pattern across the wafer. To address this issue, advanced algorithms and controls with special temperature calibrations were developed so that the system automatically controls the heaters. Moreover, it can be difficult to determine the thermal map profile that will achieve the required process uniformity. Sophisticated software algorithms have also been developed to use process trends, chamber calibration data, and wafer metrology information to automatically create the appropriate thermal maps. With this capability, incoming non-uniformity can be reduced to less than 0.5 nm CDU after etch (FIGURE 5).

FIGURE 5. Proprietary hardware and software map incoming CDs and adjust etch process conditions in the numerous micro- zones across the wafer to compensate for variability from upstream processes.

FIGURE 5. Proprietary hardware and software map incoming CDs and adjust etch process conditions in the numerous micro- zones across the wafer to compensate for variability from upstream processes.

Future focus areas

Beyond the uniformity challenges discussed, performance at the edge of the wafer – the outer 10mm, where up to 10% of the die may be located – is an increasingly important area of future focus for improving yield. In this region, uniformity control is dominated by the electrical discontinuities at the edge of the wafer that can cause sheath bending. The impacted region of sheath bending is much smaller (~10-15 mm from the edge) compared to chemical or thermal effects (50-70 or 30-50 mm, respectively). While fixed edge hardware can be redesigned for optimal uniformity, new technologies are in development to provide in situ tunability of the sheath at the wafer edge.

Looking ahead, we can expect more types of control knobs and further granularity for finer tuning along with a greater focus on automation. Compensatory process control should continue to develop and be used as process modules become increasingly complex.

REFERENCES

1. ITRS 2013: Table FEP 12 Etch Process Technology Requirements

The year 2016 is not expected to be a good one for the total memory market and the main culprit is DRAM. Declining shipments of desktop and notebook computers, the biggest users of DRAM, as well as declining tablet PC shipments and slowing growth of smartphone units have created excess inventory and suppliers have been forced to greatly reduce average selling prices in order to move parts. A DRAM ASP decline of 16% coupled with a forecast 3% decline in DRAM unit shipments is expected to result in the DRAM market declining 19% in 2016 (Figure 1), lowest among the 33 IC product categories IC Insights tracks in detail. This steep decline will be a drag on growth for the total memory market (-11%) and for the total IC market (-2%) in 2016.

Figure 1

Figure 1

Big swings in average selling price are not new to the DRAM market. Annual DRAM average selling price increases of 48% and 26% in 2013 and 2014 propelled the DRAM market to more than 30% growth each year. In fact, the DRAM market was the strongest growing IC product segment in each of those years (Figure 2). Then, marketshare grabs and excess inventory started the cycle of steep price cuts in the second half of 2015 and that continued through the first half of 2016.

Figure 2

Figure 2

Figure 3 plots changes in annual DRAM average selling prices starting in 2007.  Looking more like the profile of an alpine mountain range, DRAM ASP growth has taken several dramatic upward and downward turns since 2007, confirming the volatility of this IC market segment. When coupled with strength or weakness in DRAM unit shipments, bit volume demand, and the amount of capacity and capital spending dedicated to DRAM production each year, this market can turn quickly up or down.

Figure 3

Figure 3

On a positive note, DRAM ASPs strengthened in late 2Q16 and are forecast to continue growing through the balance of 2016 and into 2017.  The boost to DRAM ASP is expected to come from demand for enterprise (server) systems, which have been selling well due to the need to process “big data” (e.g., the Cloud and the Internet of Things).  Also, low-voltage DRAM continues to enjoy solid demand for use in mobile platforms, particularly smartphones.  Demand from new smartphone models is expected to help contribute to increasing DRAM ASPs through the end of this year and into 2017.

The upward DRAM ASP trend may be short lived, however, as two China-based companies, Sino King Technology in Hefei, China, and Fujian Jin Hua IC Company, plan to enter the DRAM marketplace beginning in late 2017 or early 2018.  It remains to be seen what devices and what technology the two new entrants will offer but their presence in the market could signal that another round of price declines is around the corner.

Further trends and analysis relating to DRAM and the total memory market through 2020 are covered in the 250 plus-page Mid-Year Update to the 2016 edition of The McClean Report.

Overall revenue for the power semiconductors market globally dropped slightly in 2015, due primarily to macroeconomic factors and application-specific issues, according to a new report from IHS Markit (Nasdaq: INFO), a world leader in critical information, analytics and solutions.

The global market for power semiconductors fell 2.6 percent to $34 billion in 2015, the report says. Discrete power semiconductor product revenue declined 10.1 percent, while power module revenues decreased by 11.4 percent and power integrated-circuit (IC) revenues increased by 4.5 percent overall.

The report identifies Infineon Technologies as last year’s leading power semiconductor manufacturer, with 12 percent of the market, Texas Instruments with 11 percent and STMicroelectronics with 6 percent.

“While Texas Instruments previously led the market in 2014, the company was overtaken by Infineon Technologies in 2015, following its acquisition of International Rectifier and LS Power Semitech,” said Richard Eden, senior analyst, IHS Markit. “Infineon was the leading global supplier of both discrete power semiconductors and power modules, and the fourth-largest supplier of power management ICs. Infineon has been the leading supplier of discretes for several years, but overtook Mitsubishi Electric to lead the power module market for the first time in 2015, again, due to the International Rectifier and LS Power Semitech acquisitions.”

Figure 1

Figure 1

According to the latest Power Semiconductor Market Share Report from IHS Markit, while Infineon Technologies’ acquisition of International Rectifier was the largest acquisition last year, several other deals also changed the terrain of the power semiconductor market landscape. Key deals in 2015 included the following: MediaTek acquired RichTek; Microchip acquired Micrel; NXP Semiconductors acquired Freescale Semiconductor; NXP Semiconductors also created WeEn Semiconductors, a joint venture with Beijing JianGuang Asset Management Co. Ltd (JAC Capital); CSR Times Electric merged with China CNR Corporation to form CRRC Times Electric; and ROHM Semiconductor acquired Powervation.

“Companies were active in acquisitions for several reasons — especially the low financing cost in multiple regions of the world, which meant that borrowing rates in the United States and European Central bank were nearly zero,” said Jonathan Liao, senior analyst, IHS Markit. “In addition, the acquiring company typically increases its revenues and margins by taking the acquired company’s existing customers and sales without incurring marketing, advertising and other additional costs.”

The Power Semiconductor Market Share Report, part of the Power Semiconductor Intelligence Service from IHS Markit, offers insight into the global market for power semiconductor discretes, modules and integrated circuits. This year’s report includes Power ICs for the first time, as well as discrete power semiconductors and power semiconductor modules. For more information about purchasing IHS Markit information, contact the sales department at [email protected].

By Yoichiro Ando, SEMI Japan

The 2016 global semiconductor market is forecast to decrease by 2.4 percent from the previous year according to the World Semiconductor Trade Statistics (WSTS). SEMI forecasts that the global semiconductor manufacturing equipment market will be effectively flat this year. However, SEMI also forecasts double-digit growth in 2017 with significant new fab construction starts in 2016 and 2017 that will drive later equipment. The forecast foresees the Japan market will shrink through 2017. This article provides insight behind those forecast numbers.

Overview

Large-scale investments in 300mm wafer lines in Japan are primarily made by three companies: Toshiba (NAND Flash), Sony (image sensors) and Micron Memory Japan (DRAM). The logic players’ investments are largely for upgrading and expanding existing capacity; the companies producing power, surface acoustic wave (SAW), and automotive semiconductor devices are actively adding capacity by constructing new fabs and expanding existing fabs. These activities are planned on 200mm or smaller wafers, so the investments are smaller in terms of dollar values. However, they are important to Japan’s semiconductor industry in the coming Internet of Things (IoT) age.

Toshiba plans a new mega fab

Toshiba continues to expanding its 300 mm NAND fabs in Yokkaichi in 2015 and 2016 ─ including the second phase construction of Fab 5, new Fab 2 for 3D NAND flash memory production, and plan for a new fab (Fab 6).

Toshiba New Fab 2

Toshiba’s new Fab 2 cleanroom (Source: Toshiba)

The new Fab 6 will be dedicated to 3D NAND flash memory production, and is planned to be built in an adjacent area of the current Yokkaichi factory site. Detailed plans of the construction (such as construction period, production capacity, and investment to manufacturing instrument used) will be decided in FY 2016 based on market trends. Fab 6 is expected to be built in FY 2017. Production capacity of the fab is projected to be more than 200,000 wafers per month (300mm wafers) at full capacity.

Toshiba and Western Digital announced a plan in July 2016 to invest a total of 1.5 trillion JPY for the next three years in Yokkaichi operations. This investment will be for the construction of the new fab as well as for updating equipment for existing fabs such as new Fab 2 and Fab 5.

Sony expands 300mm capacity

Sony is also actively expanding its 300mm wafer fabs for increased production of complementary metal-oxide-semiconductor (CMOS) image sensors. Sony plans to expand production capacity not only with its existing lines but also to acquire fabs from other companies. Specifically, Sony acquired Tsuruoka factory in Yamagata prefecture in 2014 from Renesas Electronics Corporation, and it is now operated as Yamagata Technology Center (TEC) of Sony Semiconductor Manufacturing Corporation, which is a semiconductor production subsidiary of Sony Corporation. In 2015, Sony acquired the 300mm line of the Toshiba Oita factory, for production of CMOS image sensors.

Sony plans to invest 70 billion JPY in FY 2016, and expand image sensor production capacity ─ now 70,000 wafers per month as of first quarter of 2016. The restoration of Kumamoto TEC damaged by the Kumamoto earthquake would make investment in other TECs decrease.

Micron and TowerJazz

Micron Technology operates a 300mm fab in Hiroshima (Micron Memory Japan Fab 15). The fab manufactures DRAM with 12nm process technology. Micron invested US$750 million in 2015 and $500 million in 2016 for the technology upgrades. The capacity has been flat in these two years.

Panasonic TowerJazz Semiconductor, a Panasonic and TowerJazz joint venture, operates a 300mm foundry fab in Uozu. The company invested $10 million in 2015 and plans to invest the same amount in 2016 to improve the productivity.

Investments in 200mm and smaller wafer lines

Other major semiconductor manufacturers primarily invest in existing fabs and lines for maintenances and productivity improvements. Therefore, investment amount is modest. However, these fabs will be the major source for semiconductor devices of the Internet of Things applications.

  • Renesas Electronics Corporation plans upkeep of production capacity of Kumamoto fab (200mm wafer fab) and Naka fab (300mm wafer fab).
  • Fujitsu enhances Fab B2 of Mie Fujitsu Semiconductor Limited, which provides foundry services with 300mm wafer lines. Taiwan’s major foundry UMC participated in capital of Mie Fujitsu Semiconductor Limited, and assists with 40nm process technology.
  • Rohm Co., Ltd. plans to invest more than 10 billion JPY in enhancement of 200mm lines of fab and others in the headquarters.
  • Fuji Electric Co., Ltd. continues enhancement of its 200mm wafer lines for IGBT of Yamanashi plant in FY 2016. Fuji Electric further expands its SiC power device production capacity by enhancing 200mm wafer lines at Matsumoto fab.
  • Mitsubishi Electric Corporation manufactures power devices at 200mm wafer line of Kumamoto fab. Mitsubishi Electric continues enhancement of power device production capacity.
  • Shindengen Electric Manufacturing Co., Ltd. is enhancing its power semiconductor module production by adding a new line each for Akita Shindengen Co., Ltd. and Higashine Shindengen Co., Ltd. from FY 2015.

Electronic Parts and Optoelectronic Devices

The electronic parts companies are emerging as new fab owners in Japan. Their recent activities are summarized below:

  • New Japan Radio Co., Ltd. continues enhancement of production capacity of SAW devices and GaAs ICs at its Kawagoe fab in 2016.
  • Hamamatsu Photonics K.K. continues enhancement of MEMS fabrication facility (Fab 13) which started operation in March 2014.
  • Upkeep of new clean room of Toyota Motor Corporation, which started operation in 2014, is now underway. Currently, this line is used for research and development, and trial production of SiC devices.
  • Murata Manufacturing Company, Ltd. is building a new fab for SAW filter production at its headquarter factory in Toyama. The new fab construction will be completed in September 2016. Total investment to the facility is planned to be 12 billion JPY. Then it will be equipped with 200 mm (mostly secondary) equipment.
  • Taiyo Yuden Co., Ltd. continues its enhancement plan of Oume fab in FY 2016, which was acquired from Hitachi in 2013 for SAW device production.
  • TDK agreed to acquire 125mm wafer lines in Tsuruoka Factory from Renesas Electronics Corporation in November 2015. TDK plans to enhance its production capacity of super miniature electronic components at this plant. Production will start in FY 2016 after replacement of manufacturing equipment to conform to products to be manufactured. Investment will continue in FY 2016 as well for startup of the mass production and maintenance at this plant.

SEMI World Fab Forecast

To obtain line-by-line investment and capacity trends in Japan and other regions in the world, SEMI Fab Forecast is a powerful and affordable tool. The report is in easy to use, with Excel spreadsheet format that covers six quarters of actual data and six quarters of forecast on over 1,000 fab/lines. For further information, please see www.semi.org/en/MarketInfo/FabDatabase.

Connect with Japan Semiconductor Industry at SEMICON Japan
SEMICON Japan (December 14-16, Tokyo) offers excellent opportunities to interact and connect with the Japan semiconductor industry. To join the exhibition, please see www.semiconjapan.org/en/exhibit.

Over the past 20 years, China has become increasingly frustrated over the gap between its IC imports and indigenous IC production (Figure 1).  It has oftentimes been quoted over the last couple of years that China’s imports of semiconductors exceeds that of oil.

In its upcoming Mid-Year Update to The McClean Report 2016 (released at the end of this week), IC Insights examines the “Three-Phase” history of China’s attempt at strengthening its position in the IC industry that started in earnest in the late 1990s (Figure 2).

Figure 1

Figure 1

Figure 2

Figure 2

In the late 1990s, China began to contemplate ways to grow its indigenous IC industry and assisted in creating Hua Hong NEC, which was founded in 1997 as a joint venture between Shanghai Hua Hong and Japan-based NEC (it merged with Grace in 2011).  Then, as part of the country’s 10th Five Year Plan (2000-2005), establishing a strong China-based IC foundry industry became a priority.  As a result, pure play foundries SMIC and Grace (now Hua Hong Semiconductor) were both founded in 2000 and XMC was founded in 2006.  This effort is categorized by IC Insights as Phase 1 of China’s IC industry strategy.

In the early 2000s, to help boost the sales of its indigenous foundries, as well as ride the strong wave of fabless IC supplier growth, the Chinese government began attempts to foster a positive environment for the creation of Chinese fabless companies. It should be noted that eight of the current top 10 Chinese fabless IC suppliers were started between 2001 and 2004 and seven of them were in the top 50 worldwide ranking of fabless IC companies last year. This stage of China’s IC industry strategy is labeled by IC Insights as Phase 2.

IC Insights believes that Phase 3 of China’s attempt at creating a strong China-based IC industry began in 2014, just before the start of its 13th Five Year Plan which runs from 2015 through 2020.  As discussed in detail in the Mid-Year Update, this Phase is being supported by a huge “war chest” of cash that is intended to be used to purchase IC companies and their associated intellectual property, provide additional funding to China’s existing IC producers (e.g., SMIC, Grace, XMC, etc.), and to help establish new IC producers (e.g., Sino King Technology, Fujian Jin Hua, etc.).

In 1Q16, the U.S. Department of Commerce slapped an export ban on U.S. IC suppliers’ shipments of ICs to China-based telecom giant ZTE in response to the company allegedly shipping telecommunications equipment to Iran while it was under trade sanctions by the U.S. This ban, if fully enacted, would have a devastating effect on ZTE’s telecom equipment sales (including mobile phones). Thus far, the export ban has been postponed until August 30, 2016 pending further investigation by the U.S. Department of Commerce.

The situation regarding ZTE and the abrupt announcement earlier this year of export controls on the company by the U.S. government sent shock waves throughout the Chinese government as well as China’s electronic system manufacturers.  At this point in time, such potentially drastic measures taken by the U.S. government against such a large Chinese electronics company has bolstered the Chinese government’s resolve to make China more self-sufficient regarding IC component production, spurring increased emphasis on “Phase Three.”

The Semiconductor Industry Association (SIA) announced the release of the 2015 International Technology Roadmap for Semiconductors (ITRS), a collaborative report that surveys the technological challenges and opportunities for the semiconductor industry through 2030. The ITRS seeks to identify future technical obstacles and shortfalls, so the industry and research community can collaborate effectively to overcome them and build the next generation of semiconductors – the enabling technology of modern electronics. The current report marks the final installment of the ITRS.

“For a quarter-century, the Roadmap has been an important guidepost for evaluating and advancing semiconductor innovation,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The latest and final installment provides key findings about the future of semiconductor technology and serves as a useful bridge to the next wave of semiconductor research initiatives.”

Faced with ever-evolving research needs and technology challenges, industry leaders have decided to conclude the ITRS and transition to new ways to advance semiconductor research and bring about the next generation of semiconductor innovations. While the final ITRS report charts a path for existing technology research, additional research is needed as we transition to an even more connected world, enabled by innovations like the Internet of Things. Some of these technology challenges were outlined in a recent SIA-Semiconductor Research Corporation (SRC) report, “Rebooting the IT Revolution,” but work continues to define research gaps and implement new research programs.

The ITRS is sponsored by five regions of the world – Europe, Japan, Korea, Taiwan, and the United States. Through the cooperative efforts of the global chip manufacturers and equipment suppliers, research communities and consortia, the ITRS has identified critical gaps, technical needs, and potential solutions related to semiconductor technology.

“SIA appreciates the hard work, dedication, and expertise of those involved with the ITRS over the years and looks forward to continuing the industry’s work to strengthen semiconductor research and maintain the pipeline of semiconductor innovations that fuel the digital economy,” Neuffer said.

By Pete Singer, Editor-in-Chief

Last year, Rudolph Technologies, Inc. announced the widespread adoption and success of its newest macro defect inspection tool, the NSX® 330 Series. The NSX 330 Series provides high-speed macro defect inspection with 2D\3D metrology for advanced packaging applications, which are being developed primarily to support mobility. The company said it had been “quickly and enthusiastically adopted,” garnering repeat orders from top foundries, integrated device manufacturers (IDMs) and outsourced assembly and test (OSAT) manufacturers.

The NSX 330 Series offers an array of metrology capabilities for both 2D and 3D metrology applications, including 100 percent bump height and coplanarity measurements. The NSX 330 series has now been further improved by incorporating a high speed bump laser triangulation sensor and the highly accurate VT-SS distance and thickness sensor. “We specifically offer these capabilities on a single platform because they improve total measurement accuracy on complex materials which have troubled the industry for some time,” said Scott Balak, director, inspection product management, Rudolph Technologies Inc. (Bloomington, MN).

Figure 1 illustrates the problem. The goal is to measure the actual bump height and overall coplanarity from bump top to polyimide (PI) surface. If one or more bumps are too high or too low, the other bumps won’t connect. A high-speed laser triangulation sensor attempts to see through the polyimide (PI) layer, which is typically 3-6 microns thick. “The problem is that polyimide isn’t completely transparent, so when the triangulation sensor attempts to detect the bottom of this PI layer, it is actually finding it somewhere in the middle. The current industry’s work around is to assume a PI thickness and apply a PI layer offset; however, PI thickness variation limits the accuracy of this approach,” Balak explained.

Figure 1

Figure 1

Inaccurate measurements create unnecessary review work. Because bumps may have acceptable coplanarity, but they are incorrectly flagged for further evaluation. “Customers use the review mode to determine if the bump is actually too big, or too small” Balak said.

Enter Rudolph’s Visible Thickness and Shape Sensor (VT-SS) sensor, which can concurrently measure the transparent layer thickness as well as the metal feature step height above the surface of the transparent layer. This is achieved through the integration of reflectometry and visible light interferometry principles. The direct reflection from the transparent layer provides direct thickness measurement of the transparent material, while the interferometry captures topography (distance from the sensor), allowing the system to measure the thickness of the opaque metals by scanning over the edge of the feature.

“Rudolph samples multiple bumps with both the laser triangulation and VT-SS sensors to accurately obtain a measurement average of wafer PI thickness while simultaneously calibrating the triangulation sensor with an accurate PI offset for the specific wafer being measured.,” Balak said. “The properly calibrated triangulation sensor then quickly and accurately measures millions of bumps per wafer correctly flagging bad bumps and eliminating the need to review good product. Wafer results are then sent to our Discover Analysis solution where customers can analyze correlations between defectivity and process metrology to improve the overall process. Whether it is understanding wafer and lot level trends or specific individual bumps; Discover provides the drill down capability required for root cause analysis.”

By Pete Singer, Editor-in-Chief

On Wednesday, Solid State Technology and SEMI announced the recipient of the 2016 “Best of West” Award — Coventor — for its SEMulator3D. The award recognizes important product and technology developments in the electronics manufacturing supply chain. The Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.

Coventor won the “Best-of-West” award for its SEMulator 3D modeling software. Left to right, SEMI’s Karen Savala, Dinesh Bettadapur, vice president, business development at Coventor, who received the award, and Pete Singer, Editor-in-Chief of Solid State Technology.

Coventor won the “Best-of-West” award for its SEMulator 3D modeling software. Left to right, SEMI’s Karen Savala, Dinesh Bettadapur, vice president, business development at Coventor, who received the award, and Pete Singer, Editor-in-Chief of Solid State Technology.

Coventor’s SEMulator3D is a 3D semiconductor process modeling platform that can predictively model any fabrication process applied to any semiconductor design. Starting from a “virtual” silicon wafer, the product performs a series of unit processes like those in the fab to create highly accurate 3D computer models of the predicted structures on wafer.

“It’s a very powerful software modeling platform that has been widely adopted for advanced process development and integration for 10nm, 7nm nodes and beyond,” said Dinesh Bettadapur, vice president, business development at Coventor. Bettadapur accepted the award in the Coventor booth, presented by Solid State Technology’s Pete Singer and SEMI’s Karen Savala.

Bettadapur noted that advanced devices are increasingly becoming 3D, whether it’s finFET structures, 3D NAND or gate-all-around. “We enable you to both visualize the device you’re trying to build in advance without running a single wafer, and also accurately predict process variations,” he said.

Using unique physics-driven 3D modeling technology, the SEMulator3D modeling engine can model a wide variety of unit process steps. Each process step requires only a few geometric and physical input parameters that are easy to understand and calibrate. Just as in an actual fab, upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity, etc.) interact with each other and design data in a complex way to impact the final device structure.

“You can analyze any process variation, whether it’s film thicknesses, sidewall angles, etch depths, litho biases and so forth. You can vary any process parameter that you have entered in our process simulator and then look at the upstream and downstream process effects,” Bettadapur said.

Starting from input design data, SEMulator3D follows an integrated process flow description to create the virtual equivalent of the complex 3D structures created in the fab. Because the full integrated process sequence is modeled, SEMulator3D has the ability to predict downstream ramifications of process changes that would otherwise require build-and-test cycles in the fab.

On display at Coventor’s booth is 3D sculpture modeled on 14nm FinFET Technology (see photo). This piece received the grand prize at the Design Automation Conference (DAC) last month.

The piece was produced on a state-of-the-art 3D printer from Stratasys, using SEMulator3D to generate the data. The effort was supported by GrabCad, a digital manufacturing hub that helps designers and engineers build great products faster.

With SEMulator3D, Coventor created a large model of 14nm FinFET transistors, across a wide area of SRAM design, at high resolution, integrated from starting wafer through Metal 3, with some artistic cut-outs for visibility.   The resulting model reinforced all the key advanced capabilities of SEMulator3D, including multietch, visibility-limited deposition, selective epitaxy and many others.

As DAC grand prize winner, the 14nm FinFET 3D Sculpture will now be moved to the Computer History Museum in Mountain View, CA where it will be on display for one year.

Hear more about the SEMulator 3D and all of the Best of West finalists today at the Best of West Showcase in the Advanced Manufacturing Forum at TechXPOT South from 2:00pm-3:30pm.

SEMulator3D Viewer, showing a hypothetical 22nm FinFET SRAM cell

SEMulator3D Viewer, showing a hypothetical 22nm FinFET SRAM cell

By Pete Singer, Editor-in-Chief

Fan-out wafer level packaging (FOWLP) is gaining traction, leading to higher I/Os and larger formats, and new mobile displays are pushing the limits of pixel per inch (PPI) while also moving to larger formats. Both trends are driving new requirements for lithography equipment, including steppers, track systems and photoresists. Both packages and displays are employing new types of materials and thinner substrates as well. “There’s a lot of commonality between the advanced display technologies and packaging technologies,” said Rich Rogoff, vice president and general manager of Rudolph’s Lithography Systems Group. “The step-and-repeat system approach is ideally suited to address those challenges.”

Key lithographic challenges of advanced packaging and displays are shown in Figure 1.

Figure 1. Key lithographic challenges of advanced packaging and displays are shown.

Figure 1. Key lithographic challenges of advanced packaging and displays are shown.

Rogoff said another big challenge is the ability to manage what he calls dimensionally unstable material. “These are materials that change with time, with temperature, with humidity and with process steps, every time they come back through a lithography step they can change form. Steppers have to be able to deal with that,” he said.

Rogoff also said he’s seeing changes in imaging chemistries which are creating another challenges. “We’re doing things now from broadband resist to i-line resist, from thin-films to thick films, to dry films to organic chemistries. It’s all over the field here with respect to what types of chemistries are being used to image, and the challenge is of course when going from a thick material to a thin material and varied compositions, you get a much different kind of imaging characteristic. Really you need to be able to manage all of those without having to change your lithography system,” he said.

In packaging applications, large topography is yet another challenge. In a fan-out type of situation, there can be significant differences in heights between the substrate and the die, for example. “You’re having to image through, in some cases, >20 microns of photoresist for a two or three micron line, and that becomes a very big challenge,” Rogoff said. “The package size and the display sizes are also getting bigger, and so you need to try to get as much as you can into one imaging field. The lenses need to have a very large field of view.”

FOWLP, where individual die are connected on redistribution layer, is expected to lead to a major change in process equipment. Today, die are “reconstituted” on a wafer. In the future, as volume increases, a move to high density panels is expected. “As the demand goes up, certainly panels make the most sense,” Rogoff said.

Earlier this year, Rudolph announced that a leading outsourced assembly and test facility (OSAT) has placed an order for the JetStep Lithography System for the semiconductor advanced packaging industry’s first panel manufacturing line. “That’s the first true panel fan-out application that’s moving forward, especially in the OSAT world,” Rogoff said.

While the stepper part of the litho equation is ready for “panelization,” the rest of the industry infrastructure is working from two directions. One, from printed-circuit board type solutions where thick resist are dry films. The other, from the display side, uses thin chemical resists. “Somehow we have to bridge the gap between a thin film and a thick film,” Rogoff said. “These are some of the infrastructure things that are still being worked out, but I think those are relatively easy to solve.”

Elvino da Silveira, Rudolph’s vice president of marketing, said he’s seen some recent changes. “Last year, when we were talking to the various customer and partners that we interact with in terms of the panel level fan out, everybody was really focused on doing reconstituted panels, the face-down type chips. Basically taking the EWLB process and scaling it up to the panel level. As time has gone on, and with TSMC bringing out InFO and so forth, there have been several players that are more open to doing this on a carrier. It adds some costs, but at least based on the general feedback we’ve gotten from some of the industry , scaling up to the larger substrate offsets the additional cost of the carrier,” he said.

Figure 2 (presented at SEMI’s Industry Strategy Symposium in January by Babak Sabi, corporate vice president, director, assembly and test technology department, Intel Corp.) shows the expected progression of packaging technology as IO density increases. Flip chip, ball grid array on the left (the orange box) has 15-60 micron feature sizes depending on the layer and the type of feature being exposed.

Figure 2. As IO density increases, new packaging technologies will be required (SWIFT, SLIT, SLIM and INFO-WLP are trademarks of Amkor, ASE and TSMC). Source: Intel (SEMI Industry Strategy Symposium 2016)

Figure 2. As IO density increases, new packaging technologies will be required (SWIFT, SLIT, SLIM and INFO-WLP are trademarks of Amkor, ASE and TSMC). Source: Intel (SEMI Industry Strategy Symposium 2016)

The next generation, (the yellow box) indicates fan out packaging. “We’re still more towards that boundary between the orange and the yellow, because really no one’s producing sub-five microns in HVM today. Most of it is between 5 and 10,” da Silveira said.

The next level (the green box) indicates embedded technology, such as Intel’s Embedded Multi-die Interconnect Bridge (EMIB). Instead of using a large silicon interposer typically found in other 2.5D approaches, EMIB uses a very small bridge die, with multiple routing layers. Here, the IOs are getting much higher, and the feature sizes are getting pushed toward two microns. As technology moves from the yellow box to the green box, expect a switch from wafers to panels.

200mm fabs reawakening


July 13, 2016

By David Lammers, Contributing Editor

Buoyed by strong investments in China, 200mm wafer production is seeing a re-awakening, with overall 200mm capacity expected to match its previous 2006 peak level by 2019 (Figure 1).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Speaking at a SEMI/Gartner market symposium at SEMICON West, SEMI senior analyst Christian Dieseldorff said over the next few years “we don’t see 200mm fabs closing, in fact we see new ones beginning operation. To me, that is just amazing.”

The numbers back up the rebound. Excluding LEDs, the installed capacity of 200mm fabs will reach about 5.3 million wafers per month (wspm) in 2018, almost matching the 2007 peak of 5.6 million wspm. As shown in Figure 1, By 2019 as new 200mm fabs start up in China, 200mm wafer production will surge beyond the previous 2007 peak, a surprising achievement for a wafer generation that began more than 25 years ago. Figure 2 shows how capacity, which held steady for years, is now on the increase.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Case in point: On the opening day of Semicon West, Beijing Yangdong Micro announced a new OLED 200mm fab that will be opening in the second half of 2018 to make OLED drivers, according to Dieseldorff.

Over the past few years, Japan-based companies have closed 10 200mm fabs, mostly outdated logic facilities, while expanding production of discrete power and analog ICs on 200mm wafers. But with China opening several new 200mm fabs and the expansions of existing 200mm fabs worldwide, SEMI sees an additional 274,000 wafer starts per month of 200mm production over the 2015-2018 period, adding expansions and additional fabs, and subtracting closed facilities.

“One message from our research is that we believe the existing 200mm fabs are full. Companies have done what they can to expand and move tools around, and that is coming to an end,” he said. SEMI reckons that 19 new 200mm fabs have been built since 2010, at least six of them in China.

SEMI’s Christian Dieseldorff.

SEMI’s Christian Dieseldorff.

Dieseldorff touched on a vexing challenge to the 200mm expansion: the availability of 200mm equipment. “People have problems getting 200mm equipment, used and even new. The (200mm) market is not well understood by some companies,” he said. With a shortage of used 200mm equipment likely to continue, the major equipment companies are building new 200mm tools, part of what Dieseldorff described as an “awakening” of 200mm manufacturing.

 

China is serious

Sam Wang, a research vice president at Gartner who focuses on the foundry sector, voiced several concerns related to 200mm production at the SEMI/Gartner symposium. While SMIC (which has a mix of 200mm and 300mm fabs) has seen consistently healthy annual growth, the five second-tier Chinese foundries – — Shanghai Huahong Grace, CSMC, HuaLi, XMC, and ASMC — saw declining revenues year-over-year in 2015. Overall, China-based foundries accounted for just 7.8 percent of total foundry capacity last year, and the overall growth rate by Chinese foundries “is way below the expectations of the Chinese government,” Wang said.

The challenge, he said, is for China’s foundries which rely largely on legacy production to grow revenues in a competitive market. And things are not getting any easier. While production of has shown overall strength in units, Wang cautioned that price pressures are growing for many of the ICs made on 200mm wafers. Fingerprint sensor ICs, for example, have dropped in price by 30 percent recently. Moreover, “the installation of legacy nodes in 300mm fabs by large foundries has caused concern to foundries who depend solely on 200 mm.”

But Wang emphasized China’s determination to expand its semiconductor production. “China is really serious. Believe it,” he said.

New markets, new demand

The smart phone revolution has energized 200mm production, adding to a growing appetite for MEMS sensors, analog, and power ICs. Going forward, the Internet of Things, new medical devices, and flexible and wearable products may drive new demand, speakers said at the symposium.

Jason Marsh, director of technology for the government and industry-backed NextFlex R&D alliance based in San Jose, Calif., said many companies see “real potential” in making products which have “an unobtrusive form factor that doesn’t alter the physical environment.” He cited one application: a monitoring device worn by hospital patients that would reduce the occurrence of bed sores. These types of devices can be made with “comparatively yesteryear (semiconductor) technology” but require new packaging and system-level expertise.

Legacy devices made on 200mm wafers could get a boost from the increasing ability to combine several chips made with different technologies into fan out chip scale packages (FO CSPs). Bill Chen, a senior advisor at ASE Group, showed several examples of FO CSPs which combine legacy ICs with processors made on leading-edge nodes. “When we started this wafer-level development around 2000 we thought it would be a niche. But now about 30 percent of the ICs used in smart phones are in wafer-level CSPs. It just took a lot of time for the market forces to come along.”

More coverage from this year’s SEMICON West can be found here.