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By Jean-Eric Michallet, Leti Vice President for Sales and Marketing

The pervasiveness of the Internet of Things (IoT) and its connections ranging from $1 objects to connected cars requires security to be reliable, simple, safe and affordable. Because the Internet of Things is made up of objects (hardware) connected to a network (software), security has to be factored in from the application or use’s conception. In short, assuring IoT security will require strategies to manage the entire value and supply chains.

Attendees at the recent Leti Innovation Day 2016 in Lyon, France, heard several variations of that message from industry experts and Leti scientists, against a backdrop of a proliferation of security and data threats.

Didier Lamouche, CEO of Oberthur Technologies, a provider of embedded security software products and services, noted industry forecasts of 10 billion connected devices shipped annually by 2020. This amounts to an exponential increase in security risks, as well. “This is the wave we have to catch,” he said.

Security is a brand problem

Recalling the 2013 data breach at Target in the U.S., in which 40 million credit and debit card numbers and 70 million items of customer personal information were compromised, Lamouche said that cybersecurity is not only a problem for security officers and CIOs. It has become a problem for CEOs and board of directors, as the 2014 resignation of Target CEO Gregg Steinhafel showed. In fact, he said, cybersecurity is becoming a brand problem, because of the severe damage fraud and data breaches can cause for a company.

Retail is not the only at-risk industry. Lamouche noted that more than 76 million Sony PlayStation user accounts were breached and 3.6 million connected vehicles in the U.S. and Europe have been hacked.

In recent years, “card not present” (CNP) transactions, primarily online purchases, accounted for approximately 65 percent of fraud in Europe, Australia and Canada, and 49 percent in the U.S., which still amounted to $6 billion in 2014.

Credits cards with continuously updated security codes

To address the growth of CNP fraud, Oberthur has developed MOTION CODE for credit card issuers. It secures online transactions by automatically and randomly updating a cryptogram security code on the back of the card. If the card is lost or stolen, it can be rendered useless quickly.

Keynoting the session on “Strengthening Security with Advanced Technologies,” Jean-Marie Saint-Paul, Europe application director for Mentor Graphics, outlined numerous security challenges involving hardware. 

Who can you trust?

Thieves looking for ways to steal money, companies looking for competitors’ vulnerabilities and even users “playing” with the system can create risks. The supply chain presents numerous risks, as well. Specific hardware challenges include:

  • A “vast space” of possible intrusions during IC, printed circuit board and embedded design and in the supply chain
  • Unknown bugs and frequent field updates that open back doors for attackers
  • The “fading of a trusted foundry” and proposed solutions that may not be viable
  • Counterfeit ICs that cause economic loss similar to yield loss discovered much later
  • For mission-critical apps, fake ICs that compromise devices risking security and safety

“Whatever structure we put in place, we have to put it in place with something we trust,” he said.

Digital disruption across the board

Borrowing information from IBM, Saint-Paul closed his presentation with a slide that highlights some of the most disruptive changes in business, industry and society at large that digital technology has enabled.

  • World’s largest taxi company owns no taxis (Uber)
  • Largest accommodation provider owns no real estate (Airbnb)
  • Largest phone company owns no telco infrastructure (Skype)
  • World’s most valuable retailer owns no inventory (Alibaba)
  • Most popular media owner creates no content (Facebook)
  • Fastest-growing banks have no actual money (SocietyOne)
  • World’s largest movie house owns no cinemas (Netflix)
  • Largest software vendors don’t write apps (Apple, Google)

The slide also asked when disruption will happen in semiconductors and electronics, when the world’s largest trusted foundry will own no fab or equipment, the top trusted contract manufacturer will own no assembly line and the leading secure electronics supplier will not purchase boards or chips. Will it be true? Maybe not, Saint-Paul said, but the industry needs some new models to reinvent itself.

Sameer Sharma, general manager of Intel’s IoT Group, said the IoT will provide pervasive, real-time intelligence from the physical world to data centers and the cloud: mobile devices via networks, and industrial and home applications via gateways. He cited a projection of 50 billion devices sharing 44 zetabytes of data.

Intel and Leti recently signed a multi-year collaboration agreement involving a variety of subjects such as making the IoT more secure, enabling 5G networks and device innovation, and driving the future of high-performance computing. 

85 percent of systems not connected

Combining revealing statistics from the past with projections about the direction the industry is headed, Sharma noted that the rapidly evolving digital era is spurring transformation across many fields, supported by a shift to open standards. Fixed-function ASICs are giving way to programmable architectures, dedicated appliances are now parts of virtualized systems, and purpose-built hardware is transforming into general-purpose hardware and software-defined functions.

Dramatically declining costs are a key driver for this transformation. In the past 10 years, the costs for sensors have fallen 2x, the cost of bandwidth has dropped 40x and the cost of processing 60x.

One of the most arresting facts Sharma shared relates to the huge potential, and need, for more hardware and software systems to keep up with the exponential growth of connected devices. Eighty-five percent of deployed systems are not connected and do not share data with each other or the cloud.

IoT threat landscape

Even so, Sharma said, attacks on IoT devices will increase rapidly due to hyper-growth in the number of connected objects, “poor security hygiene” and high value of data on those devices. A recent study of IoT devices showed that an average of “25 holes or risks of compromising the home network” were found on every device evaluated.

Sharma outlined a path to IoT security paved by infrastructure, end-to-end security, and 5G network and connectivity and standards. He said the Intel IoT Platform offers secure, scalable and interoperable building blocks for data acquisition, analytics and actions to improve business and peoples’ lives. Like other speakers, Sharma emphasized that security must be part of system concept and design.

“Security cannot be an add-on. Those days are gone,” he said.

Devices to protect biological, radiological and chemical data

Leti’s Alain Merle noted that privacy and security far outweigh other user concerns about connected devices. Integration in advanced technology, a focus of Leti R&D, is required, including use of security primitives, or low-level cryptographic algorithms. Secure IoT nodes face a complex array of potential weaknesses beyond physical attacks, such as attacks through communication interfaces, fault injection (glitches, light, laser, electromagnetism) and software, in which a single error can open the door to a hacker.

Beyond its cybersecurity programs, Leti is working with its partners to develop dedicated security devices to protect biological, radiological, chemical and weapons data. CESTI is Leti’s evaluation laboratory to determine whether security components and devices are designed and manufactured to prevent breaches and whether they are capable of withstanding attacks from terrorists, criminals or others.

The CESTI lab has evaluated products from leading companies such as SAFRAN, Samsung, ATMEL, STMicroelectronics, Gemalto, Oberthur and Inside Secure. The lab is part of Leti’s Strategic Security and Defense Programs, which promotes the development of innovative security solutions for information and communication (ICT) technologies for transfer to defense and commercial markets.

‘System approach with partners’

In her closing remarks, Leti CEO Marie Semeria noted that reliability, security and privacy are “must haves” to support the many key uses of digital technology. “Leti relies on a combination of hardware and software, so we pursue system approaches with our partners,” she said.

Focusing on micro- and nanotechnologies, architectures, tools and design methodologies, Semeria underlined that Leti is a worldwide recognized important center of competencies in developing innovations to propose efficient and reliable elements & architectures for emergent computing systems. She highlighted several recent Leti innovations for the Internet of Things and advanced computing for health, automotive and other sectors.

Leti has unique know-how and access to shielding, sensors, architectures and embedded software technologies for designing ASICs and SOCs for security applications. Moreover, its unique concentration of experts in materials, technologies integration, design and systems, even in biology and clinical domains, allows Leti to make the best trade offs possible between security, such as resistance to attacks, and application constraints, such as power, cost and performance.

Leti will celebrate its 50th anniversary next year as part of Leti Innovation Day in Grenoble.

The 2015 market for semiconductor silicon wafers fell 5.3% to $7.2B on a record 10.4 BSI Si shipped, according to a new report, “Silicon Wafers Market & Supply Chain 2016, a TECHCET Critical Materials Report.” The silicon demand outlook for 2016 is expected to increase 6.8% to 11.1 BSI, largely due to the strength of the memory market. Issues with wafer supply will likely continue, as demand for 300mm polished wafers increases beyond capacity. Certain 200mm wafers are also in a tight supply situation given strong demand growth from the discrete device fabs coupled with limited supplier capacity, as explained in TECHCET’s report. Declining ASPs are expected as competition for China’s 200mm wafer demand increases and the 300mm market continues its evolution toward polished wafer usage.

Although shipments of silicon by area recovered after 2009, prices have still not recov- ered to 2008 (pre-US housing / WW credit crisis) levels. TECHCET expects aggregate Si ASPs to fall slightly in 2016 before firming or modestly increasing in 2017.

SOI wafer price increases, which started in 2014 due to a temporary supply-demand im- balance, have stabilized as new capacity has come online. Some pricing pressure is anticipated in 2016 as new players vie for market share.

The timeline for 450mm wafer piloting has been pushed out to 2019 with a ramp in 2020. While Intel remains bullish, TSMC, Samsung and Global Foundries have not yet joined the 450mm investment track. As a result, only Shin Etsu Handotai (S.E.H.) and SUMCO have invested in 450mm wafer development to date.

The top 5 silicon wafer producers account for roughly 97% of 300mm polished and epi- taxial wafers sales (by revenue). S.E.H. and SUMCO together account for over 55% of that 300mm revenue and more than 60% of the top 5’s total sales. China has no appreciable market share in the wafer market however, although acquisitions could change this in the future.

For more information on the wafer market, including details on the SOI market, please see TECHCET’s Critical Materials Report on Wafers, at https://techcet.com/product/silicon-wafers/.

asmlThe Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced Martin van den Brink, president and chief technology officer at ASML Holding and renowned pioneer in semiconductor manufacturing technology, has been named the 2016 recipient of SIA’s highest honor, the Robert N. Noyce Award. SIA presents the Noyce Award annually in recognition of a leader who has made outstanding contributions to the semiconductor industry in technology or public policy. Van den Brink will accept the award at the annual SIA Award Dinner on Thursday, Nov. 10 in San Jose, an event that will commemorate the 25thanniversary of the Noyce Award.

Many past award recipients will be in attendance to celebrate the anniversary, including the following semiconductor industry leaders and founders: Dr. Craig Barrett, Dr. Morris Chang, John Daane, Dr. John E. Kelly III, Stanley Mazor, Jim Morgan, Jerry Sanders, George Scalise, Mike Splinter, Ray Stata, Rich Templeton, and Pat Weber.

“Throughout his distinguished career, Martin van den Brink has been a true semiconductor industry innovator, champion, and visionary, pioneering optical lithography methods that have given rise to the smaller, faster, more efficient chips that underpin modern technology,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Martin’s myriad accomplishments over the last 30 years have strengthened our industry and fundamentally transformed semiconductor manufacturing. On behalf of the SIA board of directors, it is a pleasure to announce Martin’s selection as the 2016 Robert N. Noyce Award recipient in recognition of his outstanding achievements.”

During Van den Brink’s three decades at ASML, he has led transformative advances in optical lithography procedures used to manufacture semiconductors. Optical lithography, a microfabrication process in which light-sensitive chemicals are used to transfer circuit patterns onto chip wafers, is the primary technology used for the production of semiconductors and has allowed for the continued miniaturization of chips. Thanks in large part to Van den Brink’s technological leadership, ASML is now the world’s largest supplier of optical lithography equipment for the global semiconductor industry.

Van den Brink was one of ASML’s first employees, joining when the company was founded in 1984. He has held various engineering positions since that time, including Vice President, Technology and Executive Vice President, Marketing & Technology. He has served on ASML’s Board of Management since 1999 and was appointed President and CTO on July 1, 2013. Van den Brink earned a degree in Electrical Engineering from HTS Arnhem, and a degree in Physics from the University of Twente, the Netherlands.

“I’m extremely gratified to accept this honor and enter the company of previous Noyce Award recipients, many of whom I’m proud to call friends, colleagues, and mentors,” said Van den Brink. “Throughout my career, I have been privileged to work with some of the finest scientists, engineers, and researchers in the world, individuals who have helped strengthen the semiconductor industry, the tech sector, and the global economy. It is with them in mind that I thankfully accept this award and look forward to continuing to work alongside them to advance semiconductor innovation.”

The Noyce Award is named in honor of semiconductor industry pioneer Robert N. Noyce, co-founder of Fairchild Semiconductor and Intel.

“I’m also pleased that we will be joined at this event by so many of the past winners of the Noyce Award who have built this industry and driven its success over the years,” Neuffer said. “This event will be a unique opportunity to celebrate the industry and the promise for the future.”

SMIC acquires LFoundry


June 27, 2016

Semiconductor Manufacturing International Corporation, the largest and most advanced foundry in mainland China, jointly announces with LFoundry Europe GmbH (“LFE”) and Marsica Innovation S.p.A. (“MI”), the signing of an agreement on June 24, 2016 to purchase a 70% stake of LFoundry for a consideration of 49 million EUR.

LFoundry is an integrated circuit wafer foundry headquartered in Italy, which is owned by LFE and MI. At the closing, SMIC, LFE and MI will own 70%, 15% and 15% of the corporate capital of the target respectively. This acquisition benefits both SMIC and LFoundry, through increased combined scale, strengthened overall technology portfolios, and expanded market opportunities for both parties to gain footing in new market sectors.

This also represents the Mainland China IC foundry industry’s first successful acquisition of an overseas-based manufacturer, which marks a major step forward in internationalizing SMIC; furthermore, through this acquisition, SMIC has formally entered into the global automotive electronics market.

As the leading semiconductor foundry in Mainland China, in the first quarter of 2016, SMIC recorded profit for the 16th consecutive quarter with revenue of US$634.3 million, an increase of over 24% year-on-year. In 2015, SMIC recorded annual revenue of US$2.24 billion. In fiscal year 2015, LFoundry revenue reached 218 million EUR.

This acquisition will bring both companies additional room for business expansion. At present, SMIC’s total capacity includes 162,000 8-inch wafers per month and 62,500 12-inch wafers per month, which represents a total 8-inch equivalent capacity of 302,600 wafers per month. LFoundry’s capacity amounts to 40,000 8-inch wafers per month. Thus, by consolidating the entities, overall total capacity would increase by 13%; this combined capacity will provide increased flexibility and business opportunities for supporting both SMIC and LFoundry customers.

SMIC has a diversified technology portfolio, including applications such as radio frequency (“RF”), connectivity, power management IC’s (“PMIC”), CMOS image sensors (“CIS”), embedded memory, MEMS, and others—mainly for the communications and consumer markets. Complementarily, LFoundry’s key focus is primarily in automotive, security, and industrial related applications including CIS, smart power, touch display driver IC’s (“TDDI”), embedded memory, and others. Such consolidation of technologies will broaden the overall technology portfolios and enlarge the areas of future development for both SMIC and LFoundry.

Dr. Tzu-Yin Chiu, the CEO and Executive Director of SMIC said, “The successful completion of the LFoundry srl acquisition agreement is an important step in our global strategy. Both SMIC and LFoundry will mutually benefit from the shared technology, products, human talents and complementary markets. This will additionally expand our production scale and allows us to service the automotive IC market and for LFoundry to enter into China’s consumer electronics market, thus bolstering our overall development and growth. Through the acquisition, communication and cooperation in the semiconductor industry between China and Europe has been further enhanced, and contributes to the mutual success of the integrated circuit industry in both regions. In the future SMIC will continue to enhance, strengthen, and further expand leadership in the global semiconductor ecosystem.”

Sergio Galbiati, the Managing Director of MI and Chairman of LFoundry srl, said, “This is the beginning of a new era for LFoundry and our Italian fab. We are pleased to become part of a very strong worldwide player, SMIC. Together we can further improve LFoundry’s strength on optical sensor related technology, which is well recognized worldwide, and continue to contribute to the growth of technology in Europe, thanks to our partnerships with many relevant players. The agreement with SMIC will enable us to have a stronger level playing field in Europe.”

Günther Ernst, the Managing Director of LFE and CEO of LFoundry srl, said, “We have made significant efforts in achieving technology excellence. The agreement with SMIC will further enable us to better use our own manufacturing capacity and have access to SMIC’s extremely diverse technology offerings while taking advantage of SMIC’s commercial network and overall capacity. As part of SMIC, LFoundry will continue to pioneer technology to help our customers achieve success and drive value for our partners and employees around the world. We look forward to working closely with the SMIC team to ensure a smooth transition.”

By Douglas G. Sutherland and David W. Price

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which examined the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing.

In the early stages of development, having more process control can help reduce both the number and duration of cycles-of-learning (the iterations required to solve a particular problem). In high volume manufacturing a well-thought-out process control strategy can increase baseline yield and, at the same time, limit yield loss due to excursions. At all stages, an effective process control strategy is required to ensure that the fab is operating at its lowest possible cost. In addition to minimizing production costs, adding process control steps can, counterintuitively, also minimize cycle time.

Figure 1 shows a conceptual plot of how cycle time would vary as a function of the number of process control steps. On the left hand side of the chart where there are no metrology and inspection (M&I) steps in place, the cycle time is effectively infinite. If a lot reaches the end of the line and has zero yield there is no way to isolate the problem. Theoretically one could isolate the problem by trial and error, but with only 100 process steps and only two parameters each, there would be 2100 (1.3 x 1030) possible combinations. Even testing one parameter per second, it would take much longer than the age of the universe to exhaust all possible combinations of the parameter space.

Figure 1. Cycle Time (CT) versus the number of process control (metrology and inspection) steps. In zone 1, the fab is information starved and unable to find yield excursions and isolate the underlying problems. In zone 3, the fab is getting more information than it can use. In zone 2, the fab has achieved balance – with a number of process control steps that minimizes the cycle time.

Figure 1. Cycle Time (CT) versus the number of process control (metrology and inspection) steps. In zone 1, the fab is information starved and unable to find yield excursions and isolate the underlying problems. In zone 3, the fab is getting more information than it can use. In zone 2, the fab has achieved balance – with a number of process control steps that minimizes the cycle time.

As process control steps are added the cycle time comes down from an effectively infinite value to some manageable number. At some point the cycle time will reach a minimum value. Beyond this point, adding in further process control steps will actually cause the cycle time to increase linearly with the number of added steps. The optimal amount of process control will always be a trade-off between minimizing cycle time, minimizing excursion cost, and maximizing baseline yield. The latter two usually have a much greater financial impact.

Adding process control steps can reduce a fab’s cycle time, but how does that work? A full treatment of cycle time (Queuing Theory) is far beyond the scope of this article, however at a high level, it can be broken down into a few manageable components. The total cycle time (CT) is the sum of the queue time (the time a lot spends waiting for a process tool to become available) and the processing time itself. Since the processing time is fixed, the only way to reduce CT is to concentrate on the queue time (Q). From Queueing Theory it can be shown that Q can be expressed by the product of three separate functions4,

Q = f(u) f(a) f(v)                                                                                           eqn 1

where f(u), f(a) and f(v) are, respectively, functions of utilization, availability and variability. The first two functions will always be finite, therefore it becomes clear that Q = 0 only when f(v) = 0. Put another way, reducing variability in the fab reduces the queue time, and if we remove all variability from the system the queue time will drop identically to zero and the CT will be equal to just the processing time.

Figure 2 shows a plot of CT as a function of utilization for three different levels of variability: zero, medium and high. The Y-axis measures cycle time in units of total processing time called the X-factor. When the variability is zero all the lots move through the fab in lock-step; there is no increase in CT with increasing utilization and all tools could be run, theoretically, at 100 percent utilization. In this case the queue time is zero and the CT is equal to the total processing time for all the steps (CT=1). As soon as some variability is introduced, the CT starts to increase exponentially with utilization and the more variability there is, the more dramatic the increase becomes.

Figure 2. Cycle time versus Utilization for three different levels of variability: High, Medium and Zero.

Figure 2. Cycle time versus Utilization for three different levels of variability: High, Medium and Zero.

Variability in the fab comes from many sources: in the lot arrival rate, in the frequency of maintenance requirements, and in the time required for that maintenance to be performed are just a few of the sources. An excursion—a lot that is out of control—affects all of the above.

Having more process control points will not immediately change the number of excursions in a fab but it will immediately improve the efficiency with which the fab reacts to them.

In fact, over time, having more process control points can also reduce the number of excursions because it increases a fab’s rate of learning.

Consider a lot that has been flagged for having a defect count that was beyond the control limit for process step N. If, as shown in figure 3a, there was another inspection point between process steps N and N-1, then the problem can be immediately isolated. Only the tool at step N (the process tool the offending lot went through) needs to be put down and only the lots that went through that tool since the last good inspection need to be put on hold for disposition.

By contrast, consider what would happen in figure 3b where the last inspection point was five steps ago at process step N-5. Practices differ from fab to fab, however in the worst case scenario, all ten tools that the lot went through would be put down and all lots that went through any of those tools would have to be put on hold. Instead of a minor disruption involving a single process tool and a few lots, entire modules and dozens of lots can be directly affected. Indirectly, it affects the entire fab.

Figure 3. (a) One process step between inspection points. (b) Five process steps between inspection points.

Figure 3. (a) One process step between inspection points. (b) Five process steps between inspection points.

Figure 3 shows that implementing fewer inspection steps has a threefold impact on cycle time:

  1. More process tools are involved and must be taken offline
  2. Each process tool is down for a much longer period of time because it takes longer to isolate the problem
  3. More wafers are in the impacted section of the production line. These wafers must be dispositioned

The variability introduced by these three impacts will also propagate through the fab; they constrict the flow of work in progress (WIP) through the fab, creating a WIP bubble that affects the lot arrival rate (increased variability) at every station downstream. All of these factors contribute to fab-wide variability and because of the re-entrant nature of the process flow, they add to the cycle time of every single lot in the fab.

When an excursion occurs, the resulting disruption impacts the cycle time of every lot in the fab and it quickly becomes a vicious cycle. The more excursions that happen during a given lot’s cycle time, the longer that cycle time will be. And the longer the cycle time is, the more likely it is that that lot will be in the fab when the next excursion occurs.

Adding inspection steps will add a small, known amount of cycle time to those lots that get inspected, but due to sampling (not every lot gets inspected) it will have a much smaller impact on the average. When an excursion does occur, comparatively few process tools will have to be put down and the module owner will be able to isolate the problem much sooner. The total disruption to the fab (the variability) will be reduced and the cycle time of all lots will be improved.

This counter-intuitive concept has been borne out by several fabs that have both added inspection steps and reduced cycle time simultaneously. Adding process control steps contributes to fab efficiency on several levels: accelerating R&D and ramp phases, increasing baseline yield, limiting the duration of excursions, and reducing cycle time. In short, a better-controlled process is a more efficient process.

The next article in this series will discuss the impact of process control to cycle time on so-called “hot lots” typically run during early ramp.

References:

  • “Process Watch: Fab Managers Don’t Like Surprises,” Solid State Technology, December 2014.
  • “Process Watch: Time is The Enemy of Profitability,” Solid State Technology, May 2015.
  • “Economic Impact of Measurement in the Semiconductor Industry,” Planning Report 07-2, National Institute of Standards and Technology, U.S. Department of Commerce, December 2007.
  • Hopp, W. J., and Spearman, M. L. Factory Physics (2nd). (New York: Irwin, McGraw-Hill, 2001), 325.

About the Authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Despite slower growth for the automotive industry and exchange rate fluctuations, the automotive semiconductor market grew at a modest 0.2 percent year over year, reaching $29 billion in 2015, according to IHS (NYSE: IHS), a global source of critical information and insight.

A flurry of mergers and acquisitions last year caused the competitive landscape to shift, including the merger of NXP and Freescale, which created the largest automotive semiconductor supplier in 2015 with a market share of 14.3 percent, IHS said. The acquisition of International Rectifier (IR) helped Infineon overtake Renesas to secure the second-ranked position, with a market share of 9.8 percent. Renesas slipped to third-ranked position in 2015, with a market share of 9.1 percent, followed by STMicroelectronics and Texas Instruments.

“The acquisition of Freescale by NXP created a powerhouse for the automotive market. NXP increased its strength in automotive infotainment systems, thanks to the robust double-digit growth of its i.MX processors,” said Ahad Buksh, automotive semiconductor analyst for IHS Technology. “NXP’s analog integrated circuits also grew by double digits, thanks to the increased penetration rate of keyless-entry systems and in-vehicle networking technologies.”

NXP will now target the machine vision and sensor fusion markets with the S32V family of processors for autonomous functions, according to the IHS Automotive Semiconductor Intelligence Service Even on the radar front, NXP now has a broad portfolio of long- and mid-range silicon-germanium (SiGe) radar chips, as well as short-range complementary metal-oxide semiconductor (CMOS) radar chips under development. “The fusion of magnetic sensors from NXP, with pressure and inertial sensors from Freescale, has created a significant sensor supplier,” Buksh said.

The inclusion of IR, and a strong presence in advanced driver assistance systems (ADAS), hybrid electric vehicles and other growing applications helped Infineon grow 5.5 percent in 2015. Infineon’s 77 gigahertz (GHz) radar system integrated circuit (RASIC) chip family strengthened its position in ADAS. Its 32-bit microcontroller (MCU) solutions, based on TriCore architectures, reinforced the company’s position in the powertrain and chassis and safety domains.

The dollar-to-yen exchange rate worked against the revenue ranking for Renesas for the third consecutive year. A major share of Renesas business is with Japanese customers, which is primarily conducted in yen. Even though Renesas’ automotive semiconductor revenue fell 12 percent, when measured in dollars, the revenue actually grew by about 1 percent in yen. Renesas’ strength continues to be its MCU solutions, where the company is still the leading supplier globally.

STMicroelectronics’ automotive revenue declined 2 percent year over year; however, a larger part of the decline can be attributed to the lower exchange rate of the Euro against the U.S. dollar in 2015, which dropped 20 percent last year. STMicroelectronics’ broad- based portfolio and its presence in every growing automotive domain of the market helped the company maintain its revenue as well as it did. Apart from securing multiple design wins with American and European automotive manufacturers, the company is also strengthening its relationships with Chinese auto manufacturers. Radio and navigation solutions from STMicroelectronics were installed in numerous new vehicle models in 2015.

Texas Instruments has thrived in the automotive semiconductor market for the fourth consecutive year. Year-over-year revenue increased by 16.6 percent in 2015. The company’s success story is not based on any one particular vehicle domain. In fact, while all domains have enjoyed double-digit increases, infotainment, ADAS and hybrid-electric vehicles were the primary drivers of growth.

IHS_Auto_Semis_Ranking_2015

Other suppliers making inroads in automotive

After the acquisition of CSR, Qualcomm rose from its 42nd ranking in year 2014, to become the 20th largest supplier of automotive semiconductors in 2015. Qualcomm has a strong presence in cellular baseband solutions, with its Snapdragon and Gobi processors; while CSR’s strength lies in wireless application ICs — especially for Bluetooth and Wi-Fi. Qualcomm is now the sixth largest supplier of semiconductors in the infotainment domain.

Moving from 83rd position in 2011 to 37th in 2015, nVidia has used its experience, and its valuable partnership with Audi, to gain momentum in the automotive market. The non-safety critical status of the infotainment domain was a logical stepping stone to carve out a position in the automotive market, but now the company is also moving toward ADAS and other safety applications. The company has had particular success with its Tegra processors.

Due to the consolidation of Freescale, Osram entered the top-10 ranking of automotive suppliers for the first time in 2015. Osram is the global leader in automotive lighting and has enjoyed double-digit growth over the past three years, thanks to the increasing penetration of light-emitting diodes (LEDs) in new vehicles.

Today, at the 2016 Symposia on VLSI Technology & Circuits, nano-electronics research center imec presented gate-all-around (GAA) n- and p-MOSFET devices made of vertically stacked horizontal silicon (Si) nanowires (NWs) with a diameter of only 8nm. The devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices.

GAA devices architectures offer optimal electrostatic control, thereby enabling ultimate CMOS device scaling. In addition, horizontal NWs are a natural extension of RMG finFETs, in contrast to vertical NWs which require more disruptive technology changes. Furthermore, stacking of NWs maximizes the drive current per footprint. Imec successfully combined these three aspects, and, for the first time, demonstrated vertically stacked horizontal Si NWs at scaled dimensions: 8-nm-diameter wires, 45-nm lateral pitch, and 20-nm vertical separation.

Compared to the conventional bulk FinFET flow, imec implemented two major differences in the process flow. First, shallow trench isolation (STI) densification at 750°C resulted to preserve sharp silicon-germanium (SiGe)/Si interfaces, which is essential for well-controlled Si NW release. Second, a low-complexity ground plane doping scheme was applied, suppressing the bottom parasitic channel.

“By demonstrating stacked nanowires with solid electrostatic control, at scaled dimensions, and using an industry-relevant RMG process on bulk silicon substrates, imec has achieved breakthrough results that can pave the way to realizing sub-10nm technology nodes,” stated Dan Mocuta, Director Logic Device and Integration at imec. “The upcoming research phase will focus on achieving even denser pitches and on leveraging this knowledge to develop gate-all-around lateral nanowire CMOS devices.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, SK Hynix, Samsung, TSMC, Huawei, Qualcomm and Sony.

TEM images of an NMOS GAASiNWFET(LG=70nm):(a)overview of the SiNW array; (b)detailed view of two stacked SiNWs

TEM images of an NMOS GAASiNWFET(LG=70nm):(a)overview of the SiNW array; (b)detailed view of two stacked SiNWs

The Semiconductor Industry Association (SIA) this week announced worldwide sales of semiconductors reached $25.8 billion for the month of April 2016, a decrease of 1.0 percent from last month’s total of $26.1 billion and 6.2 percent lower than the April 2015 total of $27.6 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, a new WSTS industry forecast projects decreased annual semiconductor sales in 2016, followed by slight market growth in 2017 and 2018.

“Global semiconductor sales decreased marginally in April, continuing a recent trend of market sluggishness driven by soft demand and a range of macroeconomic headwinds,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Despite a cumulative decrease across all product categories, year-to-year sales of microprocessors and analog products increased modestly, perhaps foreshadowing stronger sales ahead. The latest industry forecast suggests global sales may indeed rebound somewhat in the second half of 2016, but still fall short of last year’s total. The global market is projected to grow slightly in 2017 and 2018.”

Regionally, year-to-year sales increased in Japan (2.2 percent) and China (0.3 percent), but decreased in Asia Pacific/All Other (-8.2 percent), Europe (-8.6 percent), and the Americas (-14.8 percent). Compared with last month, sales were up slightly Japan(0.2 percent) and Asia Pacific/All Other (0.1 percent), but down in Europe (-0.8 percent), China (-1.8 percent), and the Americas (-2.2 percent).

Additionally, SIA today endorsed the WSTS Spring 2016 global semiconductor sales forecast, which projects the industry’s worldwide sales will be $327.2 billion in 2016, a 2.4 percent decrease from the 2015 sales total. WSTS projects year-to-year decreases across all regional markets for 2016: Europe (-0.1 percent), Asia Pacific (-1.2 percent), Japan (-1.7 percent), and the Americas (-7.3 percent). On the positive side, WSTS predicts growth in 2016 for several semiconductor product categories, including discretes, analog, and MCU products.

Beyond 2016, the semiconductor market is expected to grow at a modest pace across all regions. WSTS forecasts 2.0 percent growth globally for 2017 ($333.7 billion in total sales) and 2.2 percent growth for 2018 ($340.9 billion). WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

April 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

4.89

4.78

-2.2%

Europe

2.66

2.64

-0.8%

Japan

2.59

2.60

0.2%

China

7.93

7.79

-1.8%

Asia Pacific/All Other

8.02

8.03

0.1%

Total

26.09

25.84

-1.0%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.61

4.78

-14.8%

Europe

2.89

2.64

-8.6%

Japan

2.54

2.60

2.2%

China

7.77

7.79

0.3%

Asia Pacific/All Other

8.74

8.03

-8.2%

Total

27.56

25.84

-6.2%

Three-Month-Moving Average Sales

Market

Nov/Dec/Jan

Feb/Mar/Apr

% Change

Americas

5.41

4.78

-11.7%

Europe

2.70

2.64

-2.4%

Japan

2.49

2.60

4.3%

China

8.42

7.79

-7.4%

Asia Pacific/All Other

7.87

8.03

2.0%

Total

26.89

25.84

-3.9%

Media Contact 

By Debra Vogler, SEMI

A forum of industry experts at SEMICON West 2016 will discuss the challenges associated with getting from node 10 — which seems set for HVM — to nodes 7 and 5. Confirmed speakers at the “Node 10 to Node 5 ─ Dealing with the Slower Pace of Traditional Scaling (Track 2)” session on Tuesday, July 12, 2:00pm-4:00pm, are Lode Lauwers (imec), Guy Blalock (IM Flash), Kelvin Low (Samsung), Mike Chudzik (Applied Materials), Kevin Heidrich (Nanometrics), and David Dutton (Silvaco). SEMI interviewed Lauwers and Chudzik to see what challenges they see ahead as the industry progresses from node 7 to node 5.

According to Mike Chudzik, senior director, Cross-Business Unit Modules Team at Applied Materials, “The top tw or three process development challenges facing the industry at node 7 are RC reduction, RC reduction, and RC reduction,” Chudzik told SEMI. “At the 7nm node, parasitic resistance and parasitic capacitance delays are predicted to be greater than the inherent transistor delay.” Among the solutions he cites are new materials such as cobalt for the contact fill, lower-k spacers, and integration solutions, such as air-gap and replacement contact schemes. “While FinFETs are expected to scale to the 7nm node, their days are numbered. If you want to scale to the true historical 0.7X 7nm node, it’s a challenge for FinFETs because continuing to scale the gate length requires scaling the fin width.” He also explained that the variability in patterned fins will cause serious device performance challenges at near 5nm fin width on account of quantum confinement. “Something new like gate-all-around (GAA) devices are needed to fuel the next-generation of device scaling.”

Figure 1: At the 7nm node (CD of 13nm), the resistance of the TiN/W fill materials for the contact plug is expected to become higher than the interfacial contact resistance. SOURCE: Applied Materials

Figure 1: At the 7nm node (CD of 13nm), the resistance of the TiN/W fill materials for the contact plug is expected to become higher than the interfacial contact resistance. SOURCE: Applied Materials

Among the materials challenges in getting to nodes 7 and 5 are cobalt implementation for the contact, and Si/SiGe superlattices for the 5nm node, explained Chudzik. “The former challenge concerns replacing tungsten in the contact plug, and the latter is needed to form horizontal GAA structures.” Figure 1 shows that at the 7nm node (CD of 13nm) the resistance of the TiN/W fill material for the contact plug is expected to become higher than the interfacial contact resistance. “A TiN/Co solution provides relief.”

In addition to improving the performance of the interconnect, Lode Lauwers, VP, business development for CMOS technology at imec, told SEMI that getting to node 7 will require very advanced fin technology combined with a patterning solution. Looking ahead to node 5, he said it is expected that the fin will still be the reference technology, along with the introduction of new materials such as SiGe, and a high concentration of Ge in the channel as a mobility improvement, and possibly even the consideration of III-V materials (particularly at N5) (see Figures 2 and 3).

Figure 2: Performance and energy efficiency roadmap: devices architectures. SOURCE: imec

Figure 2: Performance and energy efficiency roadmap: devices architectures. SOURCE: imec

Figure 3: Performance and energy efficiency roadmap: transistor features that are driving the logic roadmap. SOURCE: imec

Figure 3: Performance and energy efficiency roadmap: transistor features that are driving the logic roadmap. SOURCE: imec

In looking out towards the horizon, Lauwers pointed out that the industry has to consider alternatives to the fin because there is an engineering limit to how small the fin dimensions can be made. “There is the possibility that at node 5 the industry will consider alternatives to the traditional fin, said Lauwers. “For example, the GAA structure (also referred to as a lateral or horizontal nanowire, HGAA) is superior in terms of gate control and will have better leakage control. That means you will be able to have better performance over a lower supply voltage with a lower threshold voltage.”

Beyond HGAA structures, Lauwers observed that the industry could move to a vertical nanowire structure (VGAA). But there are several contenders (see Figure 2). “It’s not up to imec to choose and it’s too early to say what will be the right option,” Lauwers told SEMI. “Maybe for certain applications or a certain technology positioning, a device maker might make a different compromise.”

In addition to imec and Applied Materials, speakers from IM Flash, Nanometrics, Samsung, and Silvaco will present at the “Scaling: Node 10 to Node 5” session of the three-day Advanced Manufacturing Forum (see Schedule-at-a-Glance) at SEMICON West 2016 which takes place July 12-14 in San Francisco, Calif.