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Today, SEMI announced that 19 new fabs and lines are forecasted to begin construction in 2016 and 2017, according to the latest update of the SEMI World Fab Forecast report. While semiconductor fab equipment spending is off to a slow start in 2016, it is expected to gain momentum through the end of the year. For 2016, 1.5 percent growth over 2015 is expected while 13 percent growth is forecast in 2017.

Fab equipment spending ─ including new, secondary, and in-house ─ was down 2 percent in 2015. However, activity in the 3D NAND, 10nm Logic, and Foundry segments is expected to push equipment spending up to US$36 billion in 2016, 1.5 percent over 2015, and to $40.7 billion in 2017, up 13 percent. Equipment will be purchased for existing fabs, lines that are being converted to leading-edge technology, as well as equipment going into new fabs and lines that began construction in the prior year.

Table 1 shows the regions where new fabs and lines are expected to be built in 2016 and 2017. These projects have a probability of 60 percent or higher, according to SEMI’s data. While some projects are already underway, others may be subject to delays or pushed into the following year. The SEMI World Fab Forecast report, published May 31, 2016, provides more details about the construction boom.

new fab lines

Breaking down the 19 projects by wafer size, 12 of the fabs and lines are for 300mm (12-inch), four for 200mm, and three LED fabs (150mm, 100mm, and 50mm). Not including LEDs, the potential installed capacity of all these fabs and lines is estimated at almost 210,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2016 and 330,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2017.

In addition to announced and planned new fabs and lines, SEMI’s World Fab Forecast provides information about existing fabs and lines with associated construction spending, e.g. when a cleanroom is converted to a larger wafer size or a different product type.

In addition, the transition to leading-edge technologies (as we can see in planar technologies, but also in 3D technologies) creates a reduction in installed capacity within an existing fab. To compensate for this reduction, more conversions of older fabs may take place, but also additional new fabs and lines may begin construction.

For insight into semiconductor manufacturing in 2016 and 2017 with details about capex for construction projects, fab equipping, technology levels, and products, visit the SEMI Fab Database webpage and order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,100 facilities including over 60 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.

The 2015 analog market grew 2% to $47.0 billion.  Combined sales of general-purpose analog products (amplifiers/comparators, interface, power management, an signal conversion devices) increased 2% to $19.1 billion and sales of application-specific analog devices also improved 2% to $27.9 billion. Among analog IC products the market for signal conversion devices showed the largest increase in 2015, growing 14% to $2.9 billion.

IC Insights’ ranking of top analog IC suppliers for 2015 is shown in Figure 1.  Collectively, these 10 companies accounted for 56% of global analog sales last year, down slightly from 57% in 2014. Among the top suppliers, nine had analog sales in excess of $1.0 billion; five of these had sales in excess of $2.0 billion.  Only tenth-ranked Renesas fell short of the $1.0 billion mark.  With a 10% increase, NXP’s analog sales outperformed the total analog market by the widest margin (Figure 1).

Figure 1

Figure 1

Texas Instruments was again the leading supplier of analog devices in 2015 with $8.3 billion in sales, which was good for 18% marketshare.  TI’s analog sales slightly surpassed the combined revenue of the next three-largest analog suppliers, and represented 69% of its total semiconductor revenue last year.  TI has always been a major player in analog, but beginning in 2009, it doubled down on its long-term efforts to dominate this market segment. That year, TI became the first company to manufacture analog devices on 300mm equipment.  It purchased 300mm manufacturing tools from defunct Qimonda and transferred it to its existing fabs in Texas to build analog ICs.  In 2010, TI acquired two wafer fabs operated by Spansion in Aizu-Wakamatsu, Japan, and a fully equipped 200mm fab in Chengdu, China from Cension Semiconductor Manufacturing.  Both facilities were converted and immediately put to use making analog ICs.  In April 2011, TI acquired National Semiconductor—its rival in many analog markets—for $6.5 billion.

TI also strengthened its analog position by transitioning to 300mm manufacturing capacity at its newer RFAB and its older DMOS 6 fabs.  Aside from boosting its analog manufacturing capacity, moving to 300mm wafer helped reduce total production costs by 40%, according to the company.

Other changes seen in the 2015 ranking include Infineon moving up one place to become the second-largest analog supplier and Skyworks Solutions moving up two spots to #3.  ST slipped from #2 in 2014 to #5 in the 2015 ranking following its 13% decline in analog sales, which it attributed to soft equipment sales (computer, consumer, automotive, industrial) among its primary customers. Collectively, Infineon, NXP, and ST—Europe’s three-largest IC suppliers—accounted for 15% analog marketshare last year.

Skyworks continues to enjoy solid analog sales due to design wins with smartphones providers around the world. Skyworks Solutions makes analog and mixed signal semiconductors for Apple, Samsung, and other suppliers of mobile devices.  Many of Skyworks’ power amplifier components are found in Apple’s iPhone 6 models.  It has been estimated that Skyworks supplies $4 worth of content for every iPhone 6 handset.

Although highly focused in mobile markets, Skyworks plans to expand into the automotive, home, and wearable markets to develop its presence in applications linked to the Internet of Things.  Analog ICs such as audio amplifiers, op amps, and analog switches are building blocks for creating wearable applications. Skyworks’ wireless technology is used in General Electric healthcare equipment, and the company recently sealed a deal to supply high-performance filter solutions to Panasonic.

Analog Devices’ analog sales grew 2% last year.  One of its key analog ICs is a device that enables 3D/Force Touch, a feature available on the Apple Watch, the latest iPhones, and new generations of the iPad, that uses tiny electrodes to distinguish between a light tap and a deep press to trigger contextually specific controls.

IC Insights forecasts the total analog market to grow 4% this year, reaching $49.1 billion and then surpass the $50.0 billion mark for the first time in 2017 as analog sales climb to an expected $51.4 billion. From 2015 to 2020, the analog market is forecast to grow at a compound annual growth rate of 6%, one point higher than the total IC market.

Communication and computer systems are forecast to be two of the three largest system applications for IC sales in every global region—Americas, Europe, Japan, and Asia-Pacific—this year, according to data presented in the upcoming Update to the 2016 edition of IC Insights’ IC Market Drivers, A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits. Communications applications are expected to capture nearly 43% of IC sales in Asia-Pacific and 39% of the revenue in the Americas region this year. Communications and computer applications are forecast to tie as the largest end-use markets in Japan while in Europe, communications apps are forecast to trail computer applications with 23.5% of ICs sales (Figure 1).

Figure 1

Figure 1

Consumer systems are forecast to be the third-largest end-use category for ICs in the Americas and Asia-Pacific regions in 2016. Automotive is expected to be the second-largest system application for ICs in Europe, which has been a bastion for automotive electronics systems development. Each of Europe’s three largest IC manufacturers—Infineon, ST, and NXP—is annually ranked among the top suppliers of automotive ICs. In addition, the automotive segment is forecast to edge ahead of the consumer segment in Japan in 2016 to become the third-largest end-use market for ICs in that country.

Collectively, communications, computers, and consumer systems are projected to account for 86.4% of IC sales in the Americas this year (an increase of half a percentage point from 2015) and 89.5% in Asia-Pacific (a decrease of half a percentage point from 2015). This year, communications, computer, and automotive applications are forecast to represent 73.5% of IC sales in Japan and 78.8% of IC sales in Europe, the same percentage as in 2015.

For more than three decades, computer applications were the largest market for IC sales but that changed in 2013 when the global communications IC market took over the top spot due to steady strong growth in smartphones and weakening demand for desktop and notebook personal computers. Figure 2 shows that globally, communications systems are now forecast to represent 39.3% of the $291.3 billion IC market in 2016 compared to 34.7% for computers, and 10.7% for consumer, which has gradually been losing marketshare for several years. IC sales to the automotive market are forecast to represent only about 7.4% of the total IC sales this year but from 2015-2019, this segment is projected to rise by a compound average growth rate (CAGR) of 8.0%, fastest among all the end-use applications.

Figure 2

Figure 2

Additional details on end-use markets for ICs are included in the 2016 edition of IC Insights’ IC Market Drivers—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits.

For the first time, scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM).

The current memory landscape spans from venerable DRAM to hard disk drives to ubiquitous flash. But in the last several years PCM has attracted the industry’s attention as a potential universal memory technology based on its combination of read/write speed, endurance, non-volatility and density. For example, PCM doesn’t lose data when powered off, unlike DRAM, and the technology can endure at least 10 million write cycles, compared to an average flash USB stick, which tops out at 3,000 write cycles.

This research breakthrough provides fast and easy storage to capture the exponential growth of data from mobile devices and the Internet of Things.

For the first time, scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM). This research breakthrough provides fast and easy storage to capture the exponential growth of data from mobile devices and the Internet of Things. In this photo, IBM scientist , Nikolaos Papandreou holds the PCM chip under a magnifying lens in his lab. (Credit: IBM Research)

For the first time, scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM). This research breakthrough provides fast and easy storage to capture the exponential growth of data from mobile devices and the Internet of Things. In this photo, IBM scientist , Nikolaos Papandreou holds the PCM chip under a magnifying lens in his lab. (Credit: IBM Research)

Applications 

IBM scientists envision standalone PCM as well as hybrid applications, which combine PCM and flash storage together, with PCM as an extremely fast cache. For example, a mobile phone’s operating system could be stored in PCM, enabling the phone to launch in a few seconds. In the enterprise space, entire databases could be stored in PCM for blazing fast query processing for time-critical online applications, such as financial transactions.

Machine learning algorithms using large datasets will also see a speed boost by reducing the latency overhead when reading the data between iterations.

How PCM Works 

PCM materials exhibit two stable states, the amorphous (without a clearly defined structure) and crystalline (with structure) phases, of low and high electrical conductivity, respectively.

For the first time, scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM). In this photo, the experimental multi-bit PCM chip used by IBM scientists is connected to a standard integrated circuit board. The chip consists of a 2 × 2 Mcell array with a 4- bank interleaved architecture. The memory array size is 2 × 1000 μm × 800 μm. The PCM cells are based on doped-chalcogenide alloy and were integrated into the prototype chip serving as a characterization vehicle in 90nm CMOS baseline technology. (Credit: IBM Research)

For the first time, scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM). In this photo, the experimental multi-bit PCM chip used by IBM scientists is connected to a standard integrated circuit board. The chip consists of a 2 × 2 Mcell array with a 4- bank interleaved architecture. The memory array size is 2 × 1000 μm × 800 μm. The PCM cells are based on doped-chalcogenide alloy and were integrated into the prototype chip serving as a characterization vehicle in 90nm CMOS baseline technology. (Credit: IBM Research)

To store a ‘0’ or a ‘1’, known as bits, on a PCM cell, a high or medium electrical current is applied to the material. A ‘0’ can be programmed to be written in the amorphous phase or a ‘1’ in the crystalline phase, or vice versa. Then to read the bit back, a low voltage is applied. This is how re-writable Blue-ray Discs* store videos.

Previously scientists at IBM and other institutes have successfully demonstrated the ability to store 1 bit per cell in PCM, but today at the IEEE International Memory Workshop in Paris, IBM scientists are presenting, for the first time, successfully storing 3 bits per cell in a 64k-cell array at elevated temperatures and after 1 million endurance cycles.

“Phase change memory is the first instantiation of a universal memory with properties of both DRAM and flash, thus answering one of the grand challenges of our industry,” said Dr. Haris Pozidis, an author of the paper and the manager of non-volatile memory research at IBM Research – Zurich. “Reaching 3 bits per cell is a significant milestone because at this density the cost of PCM will be significantly less than DRAM and closer to flash.”

To achieve multi-bit storage IBM scientists have developed two innovative enabling technologies: a set of drift-immune cell-state metrics and drift-tolerant coding and detection schemes.

More specifically, the new cell-state metrics measure a physical property of the PCM cell that remains stable over time, and are thus insensitive to drift, which affects the stability of the cell’s electrical conductivity with time. To provide additional robustness of the stored data in a cell over ambient temperature fluctuations a novel coding and detection scheme is employed. This scheme adaptively modifies the level thresholds that are used to detect the cell’s stored data so that they follow variations due to temperature change. As a result, the cell state can be read reliably over long time periods after the memory is programmed, thus offering non-volatility.

“Combined these advancements address the key challenges of multi-bit PCM, including drift, variability, temperature sensitivity and endurance cycling,” said Dr. Evangelos Eleftheriou, IBM Fellow.

The experimental multi-bit PCM chip used by IBM scientists is connected to a standard integrated circuit board. The chip consists of a 2 × 2 Mcell array with a 4- bank interleaved architecture. The memory array size is 2 × 1000 μm × 800 μm. The PCM cells are based on doped-chalcogenide alloy and were integrated into the prototype chip serving as a characterization vehicle in 90 nm CMOS baseline technology.

OpenPOWER 

At the 2016 OpenPOWER Summit in San Jose, CA, last month, IBM scientists demonstrated, for the first time, phase-change memory attached to POWER8-based servers (made by IBM and TYAN® Computer Corp.) via the CAPI (Coherent Accelerator Processor Interface) protocol. This technology leverages the low latency and small access granularity of PCM, the efficiency of the OpenPOWER architecture and the CAPI protocol. In the demonstration the scientists measured very low and consistent latency for 128-byte read/writes between the PCM chips and the POWER8 processor.

For more information on today’s announcement watch this video: https://youtu.be/q3dIw3uAyE8. Continue the conversation at @IBMResearch #3bitPCM.

By Debra Vogler, SEMI

The semiconductor industry is nothing if not persistent — it’s been working away at developing extreme ultraviolet lithography (EUVL) for many years. Though its production insertion target has slipped over the years, some say that the industry is getting closer to its introduction at the 5nm node. But it’s also true that some may be hedging their bets.

Whatever camp you fall into, the discussion is sure to be lively as a team of experts tackles the status of advanced lithography options that can get the industry from node 10 to node 5 (session “Lithography: Charting a Path, or Paths, between Nodes 10 and 5”, part of the Advanced Manufacturing Forum) at SEMICON West 2016 (July 12, 10:30am-12:30pm). Confirmed speakers for this event include Robert Aitken (ARM), Stephen Renwick (Nikon Research Corporation of America), Ben Rathsack (TEL), Mike Lercel (ASML), Mark Slezak (JSR Micro, Inc.), and Harry Levinson (GLOBALFOUNDRIES). The session will be moderated by Lithoguru’s Chris Mack. SEMI interviewed some of the session speakers to get a preview of the issues most likely to be addressed.

Equipment status

Mike Lercel, director of product marketing at ASML, told SEMI that his company is very confident that EUVL will be ready for next-generation nodes, having demonstrated progress on the NXE:3350B, which is intended for volume production: achieving 1,368 wafers per day at the ASML factory, and excellent imaging and overlay performance at >80W. He further noted that the company’s logic customers will take EUV into production in 2018-2019, so it needs to ship in volume a year before — likewise for DRAM. “We believe that EUV is cost-competitive around 1,500 good wafers per day, but the crossover point may be lower depending on the customer and the application.”

Having already achieved the productivity milestone of 1,368 wafers per day makes EUVL cost-competitive or break-even for many applications, said Lercel, primarily because multiple patterning is becoming too difficult and EUV is needed to reduce this complexity. “Additionally, we’ve exposed more than 300,000 wafers on multiple NXE:3300 scanners at customer sites and that has accelerated our rates of learning. A 125W EUV source setting has been qualified and is ready for field rollout, and we demonstrated 200W source power at ASML.” He also noted that the company has a robust EUVL product roadmap, including a high-NA EUV scanner, which will take it into the next decade and beyond. “As long as the industry continues to scale and we are not close to reaching devices’ physical limits, there will be a need for EUV.”

Lercel acknowledged that EUVL productivity must continue to be improved and throughput is closely connected to source power and tool reliability. “We’ve derived new understandings from plasma modeling and computational lithography that have enabled us to significantly increase our conversion efficiency,” said Lercel. “This was a key contributing factor in our latest 200W achievement and builds confidence in our ability to reach 250W by the end of the year, which is the source power required for 1,500 wafers per day.”

Materials and infrastructure for EUVL

There are still a number of challenges remaining for the infrastructure needed to support EUVL. Among them are actinic inspections for blanks and resists. “Deposition tools and post-pellicle mask inspection must catch up to support EUVL,” said Lercel, who told SEMI that notable progress has already been made on E-beam mask inspection high-volume manufacturing (HVM) tools and on an actinic blank inspection tool development program led by the EUVL Infrastructure Development Center (EIDEC).

In other developments reported by Lercel, Zeiss is working on an AIMS tool for defect disposition; and at imec’s EUV Resist Manufacturing & Qualification Center (EUV RMQC), the industry-wide manufacturing infrastructure and quality control capabilities needed to take EUVL into HVM are being finalized. Other R&D efforts are continuing to improve EUV blank quality process and yield — defects are now reaching single digits said Lercel. ASML is also in the process of commercializing a pellicle. Significant gaps still exist with respect to a blank multi-layer deposition tool that needs to have improved defect results. “Multiple deposition techniques are being evaluated to define the HVM tool approach,” said Lercel. “And post-pellicle mask inspection (APMI) is not on timeline for insertion,” so the industry needs other options.

Regarding EUVL resists, Mark Slezak, executive vice-president, at JSR Micro, Inc., told SEMI that short-term, the materials industry is continuing to evolve and improve chemically amplified systems that are allowing technical requirements to be met at 7nm (see Figure 1 for examples of recent performance data). “Longer term, the industry is focused on new alternative approaches to chemically amplified systems with a variety of techniques, including molecular resists, nano-particles, and advanced sensitizers,” said Slezak, who will also present at SEMICON West 2016. “Additionally, in the case of both 193i and EUV, the material industry is working on post-development solutions, such as chemical shrink, pattern collapse mitigation, and combinations with DSA (directed self-assembly) that enable further imaging extensions.”

Figure 1: Examples of recent progress in patterning materials.  Source: ASML, PSI, and imec

Figure 1: Examples of recent progress in patterning materials.
Source: ASML, PSI, and imec

As a company, JSR Micro is preparing to provide scaled-up EUV materials in a HVM setting, including advanced quality control, as early as the end of 2016, Slezak told SEMI. “However, we see that the most likely insertion point for significant volumes is in the 2018 time period.”

Overall outlook

Chris Mack summed up the industry’s current dilemma with respect to EUVL and getting from node 10 to node 5. “The whole idea of continuing on the Moore’s Law progression is to reduce the cost of a transistor by shrinking it,” Mack told SEMI. “We’ve seen a flattening of the cost/transistor trends over time lately, and I think there are some serious questions as to whether or not any specific new technology node from 10nm on will actually result in a lower cost/transistor — and if it doesn’t, there won’t be much motivation for designs to migrate to these nodes.”

Mack further observed that the cost of lithography already accounts for more than 50% of the cost of making a chip, and possibly even as high as 70% depending on the design. “As those costs escalate with each node, we worry that the cost savings won’t be enough to compensate for the higher design costs.” Citing conventional wisdom, Mack noted that the rule-of-thumb with respect to the break-even point for deciding to use EUVL is that it has to be able to cost-effectively replace three 193nm immersion steps (or masks). While there are a lot of assumptions that go into the cost-of-ownership models, Mack explained that if throughput levels can get to around 60-90wph, that would make one EUV layer cost-competitive with three 193nm immersion exposures. “I think most people agree that EUV would then be worthwhile to do. The hope is to be able to do that at the 5nm node.”

Aside from the actual technical challenges that remain to be solved before EUVL can be inserted into HVM, the major hurdle is time. “People are planning the 7nm logic node right now,” said Mack, “and no one is willing to commit to EUV for 7nm because it’s not ready.” He further explained that TSMC has said publicly it plans to exercise EUV in parallel with 193i manufacturing for the 7nm node and then implement EUV in manufacturing at the 5nm node. That would place it at around the 2020 time frame. “If EUV hits its schedule between now and 2018/2019, then we may see TSMC commit to using EUV at 5nm.” Conversely, if the EUV schedule slips and is still too risky to implement, then when 2019 comes around, it could very well be that EUVL will be pushed out even further. “Because foundries have to accept design rules about two years before manufacturing begins, and because the design rules for multiple-patterning 193 immersion are very different from single-patterning EUV, TSMC and other foundries will have to make their call about two years from now.”

For DRAM, Mack says there is still a desire for EUV to be successful, but the window is rapidly disappearing. “We might see more chip stacking as a solution going forward for DRAM,” said Mack, but “then we could see 193nm immersion SADP (single immersion double-patterning) for 20nm DRAM.” Below 20nm DRAM, If EUV isn’t ready, Mack says that chip stacking would be the solution, which leaves EUV for logic, primarily at 5nm.

“Here’s where an interesting phenomenon happens,” Mack told SEMI. “The classic view of Moore’s Law — a doubling of the number of components on a chip every two years — has been carrying on for over 50 years. Current trends are redefining the meaning of Moore’s Law (see Figure 2).”

The industry is seeing a slow-down in, i.e., 3-year cycles instead of 2-year cycles. “If that trend continues and EUV is late, that would give some breathing room for EUV to catch up. So it might be ready in time for the 5nm node.”

Figure 2: Moore’s Law trend. Courtesy: Chris Mack

Figure 2: Moore’s Law trend. Courtesy: Chris Mack

These speakers and more will present at SEMICON West 2016 (July 12-14) in San Francisco, Calif. The new SEMICON West offers eight forums: Extended Supply Chain, Advanced Manufacturing Chain Forum, Advanced Packaging Forum, Test Forum, Sustainable Manufacturing Forum, Silicon Innovation Forum, Flexible Hybrid Electronics Forum, and World of IoT Forum. Register before June 3 and save $50.

IC Insights will release its May Update to the 2016 McClean Report later this month.  This Update includes a discussion of the 1Q16 semiconductor industry market results, an update of the capital spending forecast by company, a review of the IC market by electronic system type, and a look at the top-25 1Q16 semiconductor suppliers (the top 20 1Q16 semiconductor suppliers are covered in this research bulletin).

The top-20 worldwide semiconductor (IC and O S D—optoelectronic, sensor, and discrete) sales ranking for 1Q16 is shown in Figure 1.  It includes eight suppliers headquartered in the U.S., three in Japan, three in Taiwan, three in Europe, two in South Korea, and one in Singapore, a relatively broad representation of geographic regions.

The top-20 ranking includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and six fabless companies. If the three pure-play foundries were excluded from the top-20 ranking, U.S.-based IDM ON Semiconductor ($817 million), China-based fabless supplier HiSilicon ($810 million), and Japan-based IDM Sharp ($800 million) would have been ranked in the 18th, 19th, and 20th positions, respectively.

IC Insights includes foundries in the top-20 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted.  With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers.  As shown in the listing, the foundries and fabless companies are identified.  In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

Overall, the top-20 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

Figure 1

Figure 1

In total, the top-20 semiconductor companies’ sales declined by 6% in 1Q16/1Q15, one point less than the total worldwide semiconductor industry decline of 7%.  Although, in total, the top-20 1Q16 semiconductor companies registered a moderate 6% drop, there were seven companies that displayed a double-digit 1Q16/1Q15 decline and three that registered a ≥25% fall (with memory giants Micron and SK Hynix posting the worst results).  Half of the top-20 companies had sales of at least $2.0 billion in 1Q16.  As shown, it took $832 million in quarterly sales just to make it into the 1Q16 top-20 semiconductor supplier list.

There was one new entrant into the top-20 ranking in 1Q16—U.S.-based fabless supplier AMD.  AMD had a particularly rough 1Q16 and saw its sales drop 19% year-over-year to $832 million, which was about half the $1,589 million in sales the company logged just over two years ago in 4Q13.  Although AMD did not have a good 1Q16, Japan-based Sharp, the only company that fell from the top-20 ranking, faired even worse with its 1Q16/1Q15 sales plunging by 30%!

In order to allow for more useful year-over-year comparisons, acquired/merged semiconductor company sales results were combined for both 1Q15 and 1Q16, regardless of when the acquisition or merger occurred.  For example, although Intel’s acquisition of Altera did not close until late December of 2015, Altera’s 1Q15 sales ($435 million) were added to Intel’s 1Q15 sales ($11,632 million) to come up with the $12,067 million shown in Figure 1 for Intel’s 1Q15 sales.  The same method was used to calculate the 1Q15 sales for Broadcom Ltd. (Avago/Broadcom), NXP (NXP/Freescale), and GlobalFoundries (GlobalFoundries/IBM).

Apple is an anomaly in the top-20 ranking with regards to major semiconductor suppliers. The company designs and uses its processors only in its own products—there are no sales of the company’s MPUs to other system makers. Apple’s custom ARM-based SoC processors had a “sales value” of $1,390 million in 1Q16, up 10% from $1,260 million in 1Q15.  Apple’s MPUs have been used in 13 iPhone handset designs since 2007 and a dozen iPad tablet models since 2010 as well as in iPod portable media players, smartwatches, and Apple TV units.  Apple’s custom processors—such as the 64-bit A9 used in iPhone 6s and 6s Plus handsets introduced in September 2015 and the new iPhone 6SE launched in March 2016—are made by pure-play foundry TSMC and IDM foundry Samsung.

Intel remained firmly in control of the number one spot in 1Q16.  In fact, it increased its lead over Samsung’s semiconductor sales from 29% in 1Q15 to 40% in 1Q16.  The biggest moves in the ranking were made by the new Broadcom Ltd. (Avago/Broadcom) and Nvidia, each of which jumped up three positions in 1Q16 as compared to 1Q15.

As would be expected, given the possible acquisitions and mergers that could/will occur this year (e.g., Microchip/Atmel), as well as any new ones that may develop, the top-20 semiconductor ranking is likely to undergo a significant amount of upheaval over the next few years as the semiconductor industry continues along its path to maturity.

Worldwide semiconductor capital spending is projected to decline 2 percent in 2016, to $62.8 billion, according to Gartner, Inc. (see Table 1). This is up from the estimated 4.7 percent decline in Gartner’s previous quarterly forecast.

“While the first quarter 2016 forecast has improved from a projected decline of 4.7 percent in the previous quarter’s forecast, the 2 percent decline in the market for 2016 is still bleak,” said David Christensen, senior research analyst at Gartner. “Excess inventory and weak demand for PCs, tablets, and mobile products continue to plague the semiconductor industry, resulting in a slow growth rate that began in late 2015 and is continuing into 2016.”

Table 1

Worldwide Semiconductor Capital Spending and Equipment Spending Forecast, 2015-2018 (Millions of Dollars)

2015

2016

2017

2018

Semiconductor Capital Spending ($M)

64,062.9

62,795.3

65,528.5

70,009.5

Growth (%)

-0.8

-2.0

4.4

6.8

Wafer-Level Manufacturing Equipment ($M)

33,248.1

32,642.0

34,897.6

37,641.1

Growth (%)

-1.1

-1.8

6.9

7.9

Wafer Fab Equipment ($M)

31,485.4

30,841.9

32,930.3

35,443.4

Growth (%)

-1.3

-2.0

6.8

7.6

Wafer-Level Packaging and Assembly Equipment ($M)

1,762.7

1,800.2

1,967.3

2,197.7

Growth (%)

4.1

2.1

9.3

11.7

Source: Gartner (May 2016)

“The slowdown in the devices market has driven semiconductor producers to be conservative with their capital spending plans,” said Mr. Christensen. “This year, leading semiconductor manufacturers are responding to anticipated weak demand from semiconductors and preparing for new growth in leading-edge technologies in 2017.”

In addition, the aggressive pursuit of semiconductor manufacturing capability by the Chinese government is an issue that cannot be ignored by the semiconductor manufacturing industry. In the last year, there has been consolidation and merger and acquisition (M&A) activity with specific offers from various Chinese-based entities, indicating the aggressiveness of the Chinese. This will dramatically affect the competitive landscape of global semiconductor manufacturing in the next few years, as China is now a major market for semiconductor usage and manufacturing.

Looking forward, the market is expected to return to growth in 2017. Increased demand for 10 nanometer (nm) and 3D NAND process development in memory and logic/foundry will drive overall spending to grow 4.4 percent in 2017.

This research is produced by Gartner’s Semiconductor Manufacturing program. This research program, which is part of the overall semiconductor research group, provides a comprehensive view of the entire semiconductor industry, from manufacturing to device and application market trends. Additional analysis on the outlook for the semiconductor market can be found at “Forecast Analysis: Capital Spending and Semiconductor Manufacturing Equipment, Worldwide, 1Q16.”

Atomic force microscopy is essential for obtaining three-dimensional information of crystal defects.

ARDAVAN ZANDIATASHBARA, PATRICK A. TAYLORB, BYONG KIMA, YOUNG-KOOK YOOA, KEIBOCK LEEA, AHJIN JOC, JU SUK LEEC, SANG-JOON CHOC, and SANG-IL PARKC

a) Park Systems Inc., Santa Clara, CA, USA b) SunEdison Semiconductor, St Peters, MO c) Park Systems Corp., Suwon, Korea

As integrated devices continue to shrink, incoming bare silicon wafer defectivity requirements become more and more stringent. The inspection of bare silicon wafers for surface defects is predominantly accomplished by measuring the difference in laser light scattering (LLS) between the clean surface and a surface defect, where the intensity of the scattered signal is compared to the LLS of a standard latex sphere. The actual surface defectivity can originate from added particles, topological defects, and crystal imperfections. To be able to reduce the number of defects one must know the source of the defect. LLS inspection can only give defectivity counts and a relative size. Therefore, one must rely on defect review techniques such as SEM and AFM to determine the nature and origin of the defects.

SEM provides two-dimensional aerial images of the defects which lacks the information about depth or height of the defects. On the other hand, AFM can provide three- dimensional topography images of the defects with the highest vertical resolution among all techniques[1]. The shortcomings of conventional AFM systems were low throughput, limited tip life, and arduous efforts for locating the DOI on the 300 mm wafers. To address the limitations of conventional of AFM systems for defect review, ADR AFM has been introduced for 300 mm wafers recently[2].

We used ADR AFM in this study for studying the defects found by LLS inspection tool.
In this study we focus on very small crystal imperfec- tions which are not easily observed by LLS without some means to make them larger. We have used a decorative etching technique to highlight crystal imperfections to be studied by LLS, SEM, and AFM. The defect analysis can only be accomplished with accurate and reproducible defect coordinate transfer between analysis tools. Here we show how we have successfully and reliably found and characterized the decorated defects by ADR AFM.

ADR AFM procedure

The process in ADR AFM is depicted in FIGURE 1. During this process, the defects of interest are located accurately and imaged non-destructively. Two factors are essential in order to achieve these objectives. First proper linkage between ADR AFM and LLS inspection tool is required to minimize the positioning errors and locate the defects accurately. The linkage for blank wafers is achieved by sample coordinate alignment. Generally there are no alignment markers or fiducials available on blank wafers to be used for alignment. Therefore ADR AFM uses specialized vision to perform the sample alignment properly. Another important factor in AFM defect review is non-contact mode imaging which is required for non-destructive imaging of the samples while preserving AFM tip life such that the tip can last throughout the process for multiple defects.

FIGURE 1. The schematic shows ADR AFM process for this study. After completing coordinate mapping, ADR AFM will automatically perform survey scan, zoom-in scan, processing, analysis, and classification for each defect.

FIGURE 1. The schematic shows ADR AFM process for this study. After completing coordinate mapping, ADR AFM will automatically perform survey scan, zoom-in scan, processing, analysis, and classification for each defect.

Coordinate alignment

Sample coordinate alignment is needed for proper linkage between the stage coordinates of ADR AFM andLLS inspection tool. In the case of blank wafers, no fiducial or alignment marker exists on the sample to be used for sample alignment. To overcome this challenge, a coarse alignment followed by a fine alignment is performed. In the coarse alignment, three randomly selected peripheral and the notch or an angular reference are selected to correct for translational and rotational errors. This is followed by a fine alignment to eliminate positioning errors due to non-affinity between the stage coordi- nates of ADR AFM and LLS inspection tool. A few large defects with known inspection coordinates are used for performing fine alignment. Since the defects are hardly visible in a standard AFM optical image, an enhanced vision is used to locate the defects in the optics of the ADR AFM and utilize the defects as aligner markers. Upon the sample alignment, ADR AFM is able to locate additional defects accurately. More details on coordinate alignment can be found in ref [2].

Enhanced vision

Enhanced vision is utilized during fine coordinate alignment to locate the defects in the optical vision of ADR AFM. The technique is developed based on well- known differential frame averaging of the optical frames collected from the sample surface at two accurately separated locations. The sample can be moved accurately since ADR AFM uses a separated Z and XY scanners configuration. This architecture was initially developed to eliminate the crosstalk between the XY and Z scanners (which has been a common artifact in tube scanner based AFM systems)[2]. In this setup, sample is moved by XY scanner while tip is following the sample topography by Z scanner. In enhanced vision, the optical frames of the sample are collected at two precisely separated locations, and then the final frame is generated from the difference between the collected frames. The resulting frame possesses an enhanced contrast of surface details which are not easily observable in the standard vision of ADR AFM. A comparison between the frames collected by standard vision versus enhanced vision is depicted in FIGURE 2.

Screen Shot 2016-05-09 at 3.24.37 PM

Non-contact mode imaging

Non-contact mode is the standard imaging mode in ADR AFM. It is essential to maintain tip sharpness during the defect review process from the first to the last defect that is located and imaged. In addition to keeping tip costs low, well-maintained tip sharpness ensures consistent image quality and accuracy between the images of all defects during the process. It therefore enables the automated system to uninterruptedly locate and image the defects with a high throughput. In order to perform non-contact mode imaging, the AFM cantilever is oscillated at its resonance frequency. The oscillating cantilever is brought close enough to the sample that the oscillation amplitude reduces to a pre-defined set point due to the van der Waals tip sample interaction. ADR AFM maintains the oscillation amplitude to avoid tip contacting the sample. As the tip  scans the sample surface, the oscillation amplitude is maintained by moving the cantilever up and down with the Z scanner to maintain its tip sample interaction in attractive regime. More details on non-contact mode imaging can be found in reference[4]. Although ADR AFM’s functionality is based on non-contact mode imaging, it is capable of performing in other dynamic or contact imaging modes if needed.

Automatic defect search and imaging

The significant improvements in throughput of defect review are obtained by ADR AFM due to its fully automated process. Once defect coordinates from LLS inspection tool are entered into ADR AFM, coordinate alignment is performed, the defect is located and imaging starts for the list of selected defects. The process of locating and imaging the defects is fully automated. The automation includes locating the defect, tip-sample engagement, non-contact mode parameter optimization, survey scan, optimizing the scan size, final scan, processing, and defect classification. Defects can be classified into two groups of bumps and pits. Defects are typically located within ±10 μm of their LLS coordinates.

Sample preparation

Bare 300mm diameter CZ silicon wafers were treated with a gaseous acid in a reducing atmosphere at a temperature and for a sufficient duration to grow the crystal imperfections [3]. The size and shape of the decorated defects depends on the nature of the original defect as shown in FIGURE 3. Once decorated, the defect size is capable of being detected as LLS event. The LLS inspection tool locates and sizes the LLS events, providing the coordinates to be used by the SEM and AFM.

Screen Shot 2016-05-09 at 3.24.46 PM

Results

A wafer containing surface decorated defects was inspected by a LLS tool and 34 defects were selected to be reviewed by ADR AFM. The coordinates of the defects were entered to ADR AFM, coordinate alignment performed, and the defects were located and imaged by ADR AFM. The first 21 defects had been imaged by SEM before being studied by ADR AFM. However, SEM images only provide aerial two-dimensional view of defects without sufficient infor- mation on the defects depth and out of plane dimensions. The remaining 13 defects were not found by SEM despite the signal collected by the LLS tool. The summarized results of decorated defect study with ADR AFM and comparison with SEM results aredemonstrated in FIGURE 4. ADR AFM was able to find all the 34 defects including those that had not been found by SEM.

Screen Shot 2016-05-09 at 3.24.52 PM

The defects selected to be reviewed by ADR AFM belong to eight types according to their LLS signal. The tentative classification by the LLS tool is based on the defect’s light scattering which is dependent on morphology, depth, and presenece of a central defect. As the decorative etching process proceeds, crystal imperfections are exposed and etch at a different rate than the perfect crystal surface. Defects exposed at the initial stages of the etch are deeper and more developed than defects exposed late in the etching proccess. Defects with an inverted pyramid shape are generally deeper and posses higher LLS signal. They are classified as “Facet”. Defects with curved shape formed during the late stages of etching are shallower. These defects are classified as “Shallow”. Some defects are exposed at an intermediate point in the decorative etch and have some degree of faceted walls with curved bottom. This category is classfied as “Both”. Defects which have only started to be decorated have a very weak LLS signal and are classified as “Too shallow”. The defects are also categorized whether or not they have the center defect, hence, a total of eight defect types were identified. The defect classification is tabulated in FIGURE 5.

Screen Shot 2016-05-09 at 3.25.02 PM

As we go from left to right side of the table in figure 5, the LLS signal become weaker. This was attributed to the depth of defects and the sharpness of the defect’s edges. AFM images confirmed the depth difference between different classes of defects. Since the AFM images contain Z heights, we were able to use a banded color scale to depict the surface topography of the defects more accurately in 2D view.

Discussion

FIGURE 6 depicts a comparison between the data collected with SEM vs. AFM for the same defect. Primary SEM image provides an aerial 2D view of the defect. However, the shallow depth of the defect reaches the limitations of SEM, hence, poor contrast in the image. As indicated in Fig. 5, shallower defects were not found by SEM. A secondary electron image helps identify the center defect. Identification of center defect by secondary electron is possible only if the defect was found in primary SEM image.

Screen Shot 2016-05-09 at 3.25.07 PM

On the other hand, AFM image not only provides an aerial view of the defect, it also contains the height/depth values for each pixel. Therefore, more information can be obtained about the true topology of the defect by using a 3D repre- sentation of the AFM image or using a contoured color scale. Contoured color scales can also help understanding the topology of the defect in aerial view as shown in figure 5. As indicated before, AFM has the highest vertical resolution among all imaging techniques [1], hence, better contrast of AFM images in aerial view.

All of the 34 defects were found by ADR AFM including the 13 defects that were not found by SEM. FIGURE 7 depicts the AFM images a defect that was not found by SEM. The defect depth is below 4 nm and contains a center defect. This example indicates once again the limitation of SEM resolution in out of plane direction.

Screen Shot 2016-05-09 at 3.25.15 PM

It was indicated above that ADR AFM is a non-destructive imaging technique. It utilizes non-contact mode imaging for survey scan and final imaging scan. However, SEM beam can still modify the sample surface. FIGURE 8 indicates the sample contamination as a result of electron beam “burning” the surface during SEM imaging. These SEM burn-mark sizes are related to the SEM magnification. Figure 8 shows that several SEM magnifications were used in analyzing this defect.

Screen Shot 2016-05-09 at 3.25.30 PM

Summary

We have demonstrated the power of the ADR AFM to provide quality 3D information for defect review on bare silicon wafers. Crystal defects on surface of a 300 mm wafer are highlighted using a decorative etching technique. The surface defects are located by LLS inspection. Select defects of various classes are studies by SEM and ADR AFM. While shallow defects are not found by SEM, ADR AFM successfully found all the defects and provided high resolution three-dimensional topographical information of the defects. With the automated ADR AFM this type of analysis is simple and yet powerful.

References

1. G. T. Smith, Industrial Metrology: Surfaces and Roundness.: Springer, 2002.
2. Ardavan Zandiatashbar et al., “High-throughput automatic defect review for 300mm blank wafers with atomic force microscope,” in Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 2015, p. 94241X.
3. J. Libert and L. Fei, Method to Delineate Crystal Related Defects.: PCT Publication, WO2013055368(A1).
4. Ardavan Zandiatashbar, “Sub-angstrom roughness repeat- ability with tip-to-tip correlation,” NanoScientific, no. Winter, pp. 14-16, 2014.

The authors are with Park Systems Inc. (Santa Clara, CA and Suwon, Korea) and SunEdision Semiconductor in St Peters, MO. The lead author is Ardavan Zandiatashbara: [email protected]; phone 1 408 986-1110.

The Semiconductor Industry Association (SIA) this week announced worldwide sales of semiconductors reached $26.1 billion for the month of March 2016, a slight increase of 0.3 percent compared to the previous month’s total of $26.0 billion. Sales from the first quarter of 2016 were $78.3 billion, down 5.5 percent compared to the previous quarter and 5.8 lower than the first quarter of 2015. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales increased in March for the first time in five months, but soft demand, market cyclicality, and macroeconomic conditions continue to impede more robust growth,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Q1 sales lagged behind last quarter across nearly all regional markets, with the Americas showing the sharpest decline.”

Regionally, month-to-month sales increased in Japan (4.8 percent), Asia Pacific/All Other (2.3 percent), and Europe (0.1 percent), but fell in China (-1.1 percent) and the Americas (-2.8 percent). Compared to the same month last year, sales in March increased in Japan (1.8 percent) and China (1.3 percent), but decreased in Asia Pacific/All Other (-6.4 percent), Europe (-9.8 percent), and the Americas (-15.8 percent).

“Eighty-three percent of U.S. semiconductor industry sales are into markets outside the U.S., so access to overseas markets is imperative to the long-term strength of our industry,” Neuffer said. “The Trans-Pacific Partnership (TPP) is a landmark trade agreement that would tear down myriad barriers to trade with countries in the Asia-Pacific. The TPP is good for the semiconductor industry, the tech sector, the American economy, and the global economy. Congress should approve it.”

March 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.03

4.89

-2.8%

Europe

2.66

2.67

0.1%

Japan

2.47

2.59

4.8%

China

8.02

7.93

-1.1%

Asia Pacific/All Other

7.83

8.01

2.3%

Total

26.02

26.09

0.3%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.81

4.89

-15.8%

Europe

2.96

2.67

-9.8%

Japan

2.55

2.59

1.8%

China

7.83

7.93

1.3%

Asia Pacific/All Other

8.57

8.01

-6.4%

Total

27.70

26.09

-5.8%

Three-Month-Moving Average Sales

Market

Oct/Nov/Dec

Jan/Feb/Mar

% Change

Americas

5.75

4.89

-15.0%

Europe

2.77

2.67

-3.6%

Japan

2.57

2.59

0.8%

China

8.45

7.93

-6.1%

Asia Pacific/All Other

8.08

8.01

-0.8%

Total

27.62

26.09

-5.5%

Year-to-year percent change in world semiconductor revenues over the past 20 years.

Year-to-year percent change in world semiconductor revenues over the past 20 years.

By Lara Chamness, Industry Research and Statistics, SEMI

North America has a long and rich history of semiconductor manufacturing and innovation. As home to device manufacturers such as Intel, Texas Instruments, Micron, GLOBALFOUNDRIES, NXP (Freescale), Fairchild, Avago, Qorvo, Microchip, ON Semiconductor, significant operations of Samsung, and leading fabless companies such as Qualcomm, Broadcom, NVIDIA, AMD, Apple, Marvell, and Xilinx, North America continues to play an important role in advanced semiconductor manufacturing and in device and system design. SEMI’s Fab Forecast shows that North America accounts for 14 percent of Worldwide Installed Fab capacity (excluding discretes).

Source: SEMI (www.semi.org)

In terms of revenues, IC Insights recently announced, that companies headquartered in the United States continue to capture the bulk of IDM and Fabless IC Sales.

  • U.S. companies account for 51 percent of IDM Companies IC Sales in 2015
  • U.S. companies account for 62 percent of Fabless Companies IC Sales in 2015

Due to the presence of leading device manufacturers, North America represents a significant portion of the new equipment market, annual spending on average over the past five years has been in excess of $7 billion. Spending for new equipment is expected to be approach $6 billion this year.

Source: SEMI/SEAJ; Forecast, SEMI (www.semi.org)

With such a large installed fab base, North America also claims a significant portion of the wafer fab materials market.  Comparing global fab capacity to global wafer fab market share, North America represents 18 percent of the Wafer Fab Materials market compared to 14 percent of global fab capacity. This is due to the advanced device manufacturing that occurs in the region, which requires more process steps and advanced materials which fetch higher average selling prices.

Regional Wafer Fab Materials Markets

Source: SEMI (www.semi.org)

The equipment market is expected to increase about 10 percent in North America this year due to sizable investments by GLOBALFOUNDRIES, Intel and Samsung, while the Wafer Fab Materials Market is expected to remain flat this year relative to last year. As companies like Apple, Intel, Qualcomm continue to innovate, North America will remain an essential force in both device and systems design and in semiconductor manufacturing.

Plan to attend the SEMI/Gartner Market Symposium at SEMICON West 2016 on Monday, July 11, for an update on the semiconductor market outlook.