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Finding a short term solution to the neon gas shortage problem will be challenging.

BY HITOMI FUKUDA, Gigaphoton, Inc., Oyama, Japan

When many people think of neon, they think of brightly lighted signs used in restaurants and other retail environments. The element neon (Ne) gives a distinct reddish-orange glow when used in either low-voltage neon glow lamps or in high-voltage discharge tubes or neon advertising signs. The red emission line from neon is also responsible for the well known red light of helium–neon lasers. Neon is commercially extracted by the fractional distillation of liquid air. It is considerably more expensive than helium, since air is its only source.

What those outside the chip industry likely don’t know is that neon has been employed for semiconductor manufacturing for more than a decade, since deep ultraviolet (DUV) lithography came into widespread use starting with 248nm exposure systems. Why is neon important in lithography? Excimer lasers use gases like krypton fluoride (KrF) and argon fluoride (ArF) to generate light, and those gases are regularly changed out during use. However, a charge of excimer laser gas is actually about 98 percent neon, making this carrier gas essential to the laser’s operation. Three main steps are involved in producing gas suitable for excimer laser use: (1) bulk neon production, (2) purification, and (3) final mix.

Today, the semiconductor industry is experiencing severe neon shortages, leading to price increases that are impacting end-users’ bottom line. As a result, fab owners are rushing to secure enough neon to keep their facilities in operation, including buying the critical gas on the cash market and then having it purified and mixed to allow them to put it into use as quickly as possible.

Neon is a byproduct of steel production, but because it is a rare component of the waste gases, it must be recovered at very large steel plants. The former Soviet Union manufactured all of its oxygen plants for steel mills with neon, krypton and xenon capabilities and formerly worked on high-powered lasers as weapons, giving rise to significant neon capacity. Ukraine and Russia still operate the old-style massive manufacturing plants that have long since disappeared from Western countries, and have thus historically enabled the gas to be in over-supply.

From 1990 to 2012, many of these eastern European plants simply sent the crude neon into the atmosphere as no one would buy it. This over-supply began to tighten in 2014, as many old oxygen plants in Eastern Europe were either replaced by newer units without neon capability or shutdown altogether, especially with the contraction of the steel industry.

Why the shortage?

The neon crisis was triggered in part by conflict in the Ukraine, resulting in slowed production and escalating costs on the part of gas suppliers. Because neon is used for the majority of lithography light sources, the shortage caused many chip factories to face potential slowdown or even shutdown. In addition to gas prices increasing as much as 10 times over previous rates, chipmakers faced the prospect of a 15-percent or greater reduction in available supply of neon gas.

In China, old oxygen plants are being privatized or de-activated, or are being replaced by newer plants that lack the additional rare gas recovery investment. Even though there is a strong market for rare gases, the new plants are being put in without the rare gas capability due to a minimal ROI impact. Thus, while China has increased its market share in neon gas, the country’s purification facilities are few and far between, so the country currently lacks production capacity for high-grade purification of neon gas. Regional specialty gas suppliers have also reported diminished supplies, all of which has had severe implications for the future of lithography and global chip manufacturing.

Between 2012 and 2014, the net effect of the neon supply shortage was around 125 million liters of lost annual production. In 2015, neon production, at 400 million liters, was falling short of demand by roughly 75 million liters.

A deeper look at the problem

Semiconductor-related lithography accounts for about 70 percent of worldwide neon demand. As mentioned earlier, an excimer laser uses a multi-gas mixture. The term “excimer” refers to the rare gas / halide molecule. Each fill is dedicated to the generation of a single wavelength. Four wavelengths can be generated from fluorine laser gas mixtures: 157 nm (F2), 193 nm (ArF), 248 nm (KrF) and 351 nm (XeF).

According to some reports, the price of neon gas skyrocketed in 2014, from roughly $1,000 for a 6,000-liter bottle of the gas, to approximately $6,000 for the same quantity as of late 2015. This is evident as seen in FIGURE 1, where the different colors represent the various global chipmakers. Neon gas, minerals, and the industry workhorse—silicon — are among the critical materials vital to semiconductor industry operations. The industry has had to deal with shortages in helium and rare earths in recent years, but was able to find at least temporary solutions.

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Neon gas, on the other hand, appears to be a shortage for which finding a solution in the short term will be far more challenging. This problem is expected to continue for several years until a) sufficient new capacity comes on line, b) recycling can be implemented, or c) reprogramming of lasers can be accomplished, in order to allow for more efficient usage. In all likelihood, it will be a combination of all three of these factors that will alleviate the industry’s neon supply challenges, although getting prices back down to a more affordable level is likely to take longer.

Neon conservation

In the meantime, the industry is looking at ways to conserve neon gas to help stretch its usage until such as time as the larger issues begin to be addressed in a more long-term fashion. Important developments in neon conservation include recent excimer laser gas usage optimization efforts that have been put in place by lithographic tool and laser equipment vendors to help end-customers reduce consumption. Optimization can be achieved via software updates for current systems and may result in up to 40 percent more efficient neon usage. In addition, recovery and recycling of neon may be relatively straight-forward with few technical challenges, so several suppliers are proposing recycling and recovery plans.

With that said, the potential impact of these conservation efforts should be carefully considered, as some have the potential to put on hold, or even cancel, capital investment plans to produce more neon. This could mean the neon shortage would become exacerbated or prolonged beyond its current, already critical level.

To combat this crisis, Gigaphoton developed its unique Neon Gas Rescue Program, which expands on its previously announced program offering its eTGM technology for all new and existing GT series ArF immersion lasers.

The new program provides a more comprehensive package that includes the following:

1. A program for rapid qualification of new gas suppliers requested by customers. Previously, testing and qualification of a new gas supplier required anywhere from six to 12 months, but the new program will enable customers to begin using new gas suppliers much more quickly – cutting the qualification time down to as little as one month.

2. A limited, free-of-charge offer of the company’s eTGM technology will also be extended to the G41K series KrF lasers and GT40A series ArF lasers. This extended offer will commence in November 2015. By introducing eTGM, customers can reduce the laser’s neon usage by 25 percent on KrF and ArF lasers, and up to 50 percent on ArF immersion lasers.

3. The accelerated introduction of Gigaphoton’s newest gas recycling technology, hTGM, which can be applied to all types of lasers. hTGM is expected to begin roll-out later this year. By implementing the hTGM technology, customers will be able to recycle up to 50 percent of their gas consumption.

Conclusion

While the semiconductor industry is facing a unique challenge with the current neon gas supply shortage, it has history on its side in terms of innovative solutions. The lithography sector, in particular, has repeatedly found ways to extend and revitalize technology applications.

HITOMI FUKUDA is from the marketing team at Gigaphoton, 400 Yokokurashinden, Oyama-shi, Tochigi-ken 323-8558, Japan; email: [email protected]; www.gigaphoton.com.

Optimized settings for DI water pressure at CMP and careful analysis of interconnect layout are used to improve quality on a complex analog design.

BY STEPHEN SWAN, JOSEPH WILLIAMS, ANN CONCANNON, JIM O’HANNES and ERIC EVANGELOU, Texas Instruments, Dallas, TX

Triboelectricity is defined as a charge of (static) electricity generated by friction. The concept was first applied in the 1940s for electrostatic painting and is now widely used in photocopy machines. This phenomenon becomes a concern in wafer manufacturing processes since water is a polar molecule and deionized water (~18MOhm) is a good insulator [1, 2].

Our investigation into circuit damage was initiated by a finding of high leakage from a single transistor within a complex analog design. Electrical and physical analysis of a failing site revealed a halo image on a TEM micrograph, suggesting that the area of highest electric field under the poly gate had been damaged (FIGURE 1).

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Wafer signature – fab root cause

After insuring there was no quality risk (with HTOL and ELFR reliability testing), focus was placed on identi- fying the physical root cause, understanding why the failures were only occurring on a single transistor, and developing a design rule to reduce the risk on future products. Examination of wafer yield maps revealed fallout of less than 500 parts per million (ppm) in a distinctive geometric pattern with failing die at unique radius from the wafer center. Discussions with fab process experts within TI revealed that the geometric pattern aligned with positions of DI water jets on a single wafer oxide chemical mechanical planarization (CMP) tool and that the problem correlated to use of high DI water pressure (60psi) during wafer transfer operation.

Subsequent experiments proved that transistor damage was occurring when DI water was used to elevate the (inverted) wafer from the load chuck to the polish head with jets of water causing static discharge in distinct locations (FIGURES 2, 3). Interim corrective action was taken to match the DI water pressure to the recommended setting of 20psi, with verification provided by both passive data and experimental results [3].

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Since static electricity in triboelectric charging is caused by friction, we can apply the Bernoulli principle to estimate the relative change in static charge when dropping water pressure from 60psi to 20psi (Equation 1). This principle states that the sum of energy (kinetic and potential) in a fluid under steady flow must be equal at all points along the stream. In the case of water being ejected from a fixed nozzle, this would require that a drop in pressure (potential energy) results in a drop in velocity (kinetic energy) thereby reducing friction and static charge.

Equation 1: Bernoulli principle

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Where:
v is the fluid flow (m/s)
g is the value of acceleration due to gravity (9.81m/s2) z is the orifice size
p is the pressure (pascals)
ρ is the density of water (1000 kg/m3)

Solving for relative difference, we find that velocity is a function of pressure, such that reducing pressure from 60psi to 20psi will decrease the velocity by about 40 percent. Thus, we can predict a corresponding drop in static charge due to friction by the same amount. The relative difference in charge was validated by using a surface photovoltage (SPV) tool, which is a method of monitoring the potential of a semiconductor surface [4], FIGURE 4.

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Tool ‘fingerprint’ analysis

Now that a physical explanation for how excess static charge was being applied to the face of product wafers had been defined, the next step was to understand why the resulting damage to the product circuit was always observed in a specific transistor (as opposed to being randomly distributed throughout the circuit). Through yield map signature analysis of the diagonal clusters of product die with a revised test screen, it was noted that while the clusters of failing die appeared at distinct radius dimensions from wafer center, their orientations were not fixed and, at first pass, seemingly random. However, upon closer inspection of the load chucks (FIGURES 2, 3), it was found that the water jets (appearing as a ‘slit’ style nozzle) had fixed orientations that were different from tool to tool.

This information led to an effort of correlating the nozzle position on each CMP tool to the orientation of diagonal clusters in the stacked yield wafer maps. This comparison made it possible to map yield loss sites from individual wafers to specific tools, and to identify that the damage was taking place at a specific layer for the product (second dielectric CMP, after metal-1).

Capacitive coupling

With the knowledge that the source of the physical damage was coming from triboelectric charging at one oxide CMP step , a working theory was created to show how the electric charge could find a path to ground from the front side (DI water jet) to the backside (grounded wafer chuck) of the wafer (FIGURE 5).

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Design considerations

In a design of more than 180 thousand transistors, it was significant that all failures mapped to a single NMOS transistor. This device was one of six identical structures, a two finger minimum sized 5V NMOS and the device was isolated from any external connections so charge coupling from an external pin was eliminated as a potential cause. Also, a review of metal-to-gate antenna design rules confirmed that there were no violations within the failing array and metal to gate ratios were well within the specification, with 10X margin. Since it was unlikely that a traditional antenna was the cause of the gate damage, additional aspects of the layout needed investigation [5].

Two areas of concern at the metal-1 layer under second dielectric were minimum metal spacing and adjacent metal routes for parallel lines. Investigation of the layout and design rules at this layer showed that minimum spacing of parallel lines was smaller than that of other metal layers, which would make the capacitance coupling between metal lines at this layer more significant.

Further analysis of the adjacent metal showed that this one transistor had a considerable amount of floating metal (prior to subsequent metal routing) adjacent to its gate metal compared to the five adjacent transistors. A model of capacitance between the floating metal and gate metal of the six structures showed that the LED5 transistor had a ratio more than 10:1 compared with ratios less than 1:1 for each of the other five transistors.

Our conclusion from these combined efforts was that failure of the single transistor in question was due to the unique layout of tight metal spacing and a high ratio of floating metal-to-gate metal, when under the influence of triboelectric charging from the fab CMP process.

An updated graphic (FIGURE 6) is used to show that charge is induced on the wafer (oxide) surface and coupled to the floating metal and finally, to the gate metal. The floating metal increases the effective gate metal capacitance such that it is now large enough to accumulate adequate charge to damage its gate oxide.

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To prevent this effect from impacting future designs, an electronic design automation (EDA) approach was used to define conditions which would flag combinations of metal:gate antenna ratios and proximity of gate to floating metal.

Summary

Root cause of high leakage from a single transistor within a complex analog design was proven to be due to an interaction between triboelectric charging in the wafer CMP process and the unique layout of this structure. Process modifications were performed to reduce DI water pressure during the wafer handling sequence at CMP, a test screen was developed to yield off any future failures and ELFR / HTOL reliability verification was performed to insure no quality risk on finished goods. EDA design checks have been developed to flag structures with high ratios of spacing for floating metal to gate metal for sites with significant metal antenna ratios.

Acknowledgments

Our thanks to several members of TI who were instrumental in identifying root cause and solutions. These include Dan Clavet, Scott Kolda, Aaron Dries, and Chris Qualey from MaineFab, Jonathan Shu and Michelle Hartsell of SVA Quality, Bill McIntyre of SVA-MDP, Dinh Nguyen of SVA- MLP, Nam Nguyen and Chris S Pereira of ATI, and Mikko Loikkanen of SVA-MLP Design.

References

1. Dela Cruz, W.A.; Marcelo, M.L.D.; Borlongan, M.A.B., “Preventing arcing damage on radio frequency device wafer by

controlling ESD resistivity level of water for saw and wash,” 29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD, vol., no., pp.3B.5-1, 3B.5-4, 16-21 Sept. 2007.

2. Re-Long Chiu (WaferTech) “Scrubber Clean Induced Device IDDQ Fail”, IEEE Proceedings, 2012.

3. S. Larivière (Altis Semiconductor), “Electro-static induced metal breakdown at interlayer dielectric post CMP brush clean process”. ASMC Proceedings, 2009.

4. Schroder, Dieter K. (2006). Semiconductor Material and Device Characterization. Wiley-IEEE Press. ISBN 0-471-73906-5.

5. Ackaert, J.; Greenwood, B., “Design solutions for preventing process induced ESD damage during manufacturing of inter- connects,” IC Design and Technology (ICICDT), 2010 IEEE Inter- national Conference on , vol., no., pp.98,101, 2-4 June 2010.

STEPHEN SWAN is Quality Manager at TI’s MaineFab in South Portland Maine; JOSEPH WILLIAMS and ERIC EVANGELOU are mem- bers of MaineFab Product Engineering; ANN CONCANNON (DMTS) is a member of TI Analog Labs in Santa Clara CA; JIM OHANNES is manager of the TI Design Center in South Portland ME.

An exploration of where trace metals come from, the impact they have on the industry and what can be done to reduce the risks.

KNUT BEEKMANN, Precision Polymer Engineering (PPE), part of the IDEX Sealing Solutions Group, Blackburn, England

Triboelectricity is defined as a charge of (static) electricity generated by friction. The concept was first applied in the 1940s for electrostatic painting and is now widely used in photocopy machines. This phenomenon becomes a concern in wafer manufacturing processes since water is a polar molecule and deionized water (~18MOhm) is a good insulator [1, 2].

When working at the nanoscale of microchip production, even low levels of contamination have the capacity to alter the electrical characteristics of the device and affect the reliability of the end product. Operational hygiene has always been an issue due to the sensitivity of semiconductors to contaminants, but the threat of trace metal contamination specifically is significant. This is mainly true for front end processing but, due to the high mobility of many of these contaminants, it remains a threat at all stages of the manufacturing process flow.

Trace metal constituents of elastomer seals can be released as byproducts during erosion of the seal in aggressive plasma or chemical environments that are part of routine process tool operation. Contamination of semiconductor devices by trace metals adversely affects device performance and as linewidths decrease, the allowable levels of metal contamination reduce. This article explores where trace metals come from, the impact they have on the industry and what can be done to reduce the risks.

Background

Semiconductor microchips, which provide inexpensive, fast computing power for electronic devices, are made from millions or even billions of transistors. The transistor is fundamentally an electronic switch that contains no moving parts but uses an applied low voltage to the gate which in turn allows electrons to move from the source to the drain.

The overall chip making process involves many repeating steps to form the transistor at the front end, and subse- quent formation of the back end interconnect including multiple metal and dielectric levels and several etch steps in between. In the process of building these layers, many transistors are created and interconnected. When completed, a single wafer will contain hundreds of identical chips that must pass rigorous testing. The chip is then mounted onto a metal or plastic package that undergoes final testing, ready to be assembled into final products [1,2].

During routine operation, many components within the process tools and ancillary equipment will be subject to wear and abrasion, particularly those components within the process module that are directly exposed to harsh physical and chemical environments. The most critical locations are those where components are exposed to such environments and in proximity to the substrate being processed.

Equipment consumable items that can sometimes be overlooked are elastomer seals or O-rings. These materials have a certain lifetime proportional to the mechanical and chemical properties of the operating environment and the physical constraints of the groove and location. While an elastomer in a critical location may not actually determine the maintenance cycle of the process tool, byproducts and elastomer constituents will be released into the process environment during active operation. Therefore, whatever constitutes the elastomer can contaminate the wafer and this applies equally to the trace metals.

Trace metal contaminants fall broadly into two categories. Alkali metals which include elements such as sodium (Na), potassium (K) and lithium (Li) and heavy metals which include elements such as copper (Cu), iron (Fe), zinc (Zn), titanium (Ti) and chromium (Cr). The effects on the device of such contaminants vary depending on the type of the element. Sodium for example, can readily lose its outer electron to form an ion with charge +1. It can then readily diffuse through the oxide under the influence of an electric field even at room temperature, however; it cannot penetrate the silicon crystal lattice which means that a charge can accumulate at the silicon/silicon dioxide interface. This in turn leads to unpre- dictable voltage threshold shifts and correspondingly random digital outputs from logic circuits.

Additional failure mechanisms include current leakage through the dielectric and reduced dielectric breakdown voltage, degradation of time dependent dielectric breakdown (TDDB), or complete breakdown of the gate [3]. Gettering layers are also no guarantee of eliminating the issue. Phopho- silicate glass (PSG) and borophophosilicate glass (BPSG) layers are often used to getter sodium ions, however, the presence of moisture either through integral process steps or atmospheric absorption can facil- itate the release of trapped mobile ions in the getter [4]. Rather than accumulate at the semiconductor interface, heavy metals tend to diffuse through the semiconductor, where they effectively create energy states in the bandgap of the semiconductor causing changes in carrier lifetime or the diffusion length [5].

Consumer demands for faster, more powerful and portable technology with greater functionality is a key factor driving the semiconductor manufacturing industry.

Although the part of Moore’s law that refers to shrinking technology remains largely intact, the pressure on cost reduction is rising throughout the whole value chain [6]. Reduced device dimensions and gate thickness leads to devices that become more sensitive to a number of factors including trace metal contamination.

It is clear that such contamination leads to unstable device performance, yield loss, device degradation with increased risk of reliability failures, potentially costing the fab in lost time, loss of revenue and wafer production capacity.

Purity in elastomers

When choosing elastomer materials or seals for critical applications, device manufacturers must ensure that they select appropriate materials with ultra-low levels of trace metals, in order to avoid contamination and device degradation. Manufacturers must also decide on the material in accordance with the location in the tool and the chemistry involved. Critical locations where the elastomer is in contact with the chemistry or process media, where degradation takes place, and where the byproducts of this degradation can be transported to the wafer, require the highest quality seal material in order to avoid contaminating the device. The sealing product must precisely fit the characteristics of the operating equipment.

There is often a large choice of products for any one particular application and ‘semiconductor compatibility’ is often taken for granted especially in critical applications. However, not all elastomer materials are equal when it comes to the level of undesirable contaminants. For many device applications, it is no longer adequate to measure contamination at the parts per million (PPM) level. When analyzing trace metal levels in elastomer materials, vapor phase decomposition (VPD) combined with inductively coupled plasma mass spectrometry (ICPMS) yields data down to parts per billion [7]. A number of different elastomer materials have been analyzed by an independent test laboratory in order to quantitatively determine the amount of trace metal within each sample. The materials analyzed include the leading elastomer brands and the results are graphically represented in FIGURE 1. It should be particularly noted that In order to accommodate all the samples tested, a log scale was used.

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The results show that the elastomers that achieved the lowest trace metal content of all materials tested were entirely organic perfluoroelastomers, or FFKMs. The cleanest fluoroelastomer or FKM material was found to be Nanofluor Y75N, again a fully organic highly fluori-nated elastomer. FIGURES 2, 3 and 4 below illustrate the individual levels for several of the key contaminants that should be avoided for three of the cleanest materials tested.

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Conclusion

It is clear that the seal lifetime is not the only factor that should be considered when making elastomer choices for specific applications. Elastomer or seal wear in key tool locations during normal operation exposes the wafer to the degradation byproducts of the elastomer material, and therefore also the impurities contained within the elastomer, such as trace metals. FFKM elastomers are particularly suited to the most critical applications, and the harsh environments presented by higher temper- atures, aggressive wet chemical and plasma processes. The more aggressive the environment and the more sensitive the device, the greater is the need to consider the contaminating degradation byproducts of the system components.

Contamination ultimately results in loss of yield, increased cost, or loss of reputation. The use of high purity components becomes a preventative measure, guarding against costly transistor damage or increased risk of poor reliability. Elastomer materials that contain only ultra-low levels of metallic contaminants are ideal for manufacturers of devices at advanced technology nodes and all fabs wishing to minimize the risk of random changes to electrical characteristics and reliability failures.

For further information about how to integrate high performance elastomer seals into your production equipment, and to understand the benefits of customized sealing solutions please contact the author at [email protected].

The industrial semiconductor market will post an 8 percent compound annual growth rate (CAGR), as revenue rises from $43.5 billion in 2014 to $59.5 billion in 2019. Increased capital spending and continued economic growth, especially in the United States, will spur demand and industrial semiconductor sales growth, according to IHS Inc. (NYSE: IHS), a global source of critical information and insight. Commercial aircraft, LED lighting, digital video surveillance, climate control, traction and medical devices are driving most of the global demand for industrial semiconductors.

The greatest semiconductor growth will come from LEDs, which is expected to reach $14.5 billion in 2019, stemming from the global LED lighting boom. Discrete power transistors, thyristors, rectifiers and power diodes are expected to hit $7.8 billion in revenue, due to the policy shift toward energy efficiency in the factory automation market.

According to the IHS Industrial Semiconductors Intelligence Service, analog application-specific integrated circuits (ICs) can expect strong growth through 2019, reaching $4.7 billion in industrial markets, especially in factory automation, power and energy, and lighting. Growth will primarily come from various power management product portfolio offerings and device integration from Texas Instruments (TI), Analog Devices (ADI), NXP and other leading semiconductor firms. Microcontrollers (MCUs) are also expected to experience robust growth in the long term, growing from $4.4 billion to $6.3 billion, thanks to advances in power efficiency and integration features.

Total industrial original equipment manufacturing (OEM) factory revenue is forecast to grow at a CAGR of 5 percent, reaching $670 billion in 2019. Industrial OEM factory revenues specifically grew 6 percent in 2015 driven by increased sales in building and home-control, and military and civil aerospace sectors. High-growth categories include LED lighting, climate control, digital video surveillance products and commercial aircraft.

With its comparatively strong global economy, the United States accounted for 30 percent of all semiconductors used in industrial applications in 2015. China was the second largest industrial chip buyer, purchasing about 16 percent of all industrial semiconductors last year.

“Robust economic growth and increased capital spending in the United States is good news for industrial semiconductor suppliers, because they have the world’s largest industrial equipment makers, including General Electric, United Technologies and Boeing,” said Robbie Galoso, associate director, industrial semiconductors, IHS Technology. “Strong industrial equipment demand will further boost sales of optical semiconductors, analog chips and discretes, which are the three largest industrial semiconductor product segments.”

By Douglas G. Sutherland and David W. Price

Author’s Note: This is the last in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications. Within this article we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

In the eighth installment1 in this series, “The Tyranny of Numbers,” we discussed the trend of increasing process steps—the number of steps is expected to double between the 20nm and 10nm nodes—and the impact that those additional steps will have on final yield. In addition to impacting yield, the increased complexity of the process flow will also increase production costs and cycle time. As these trends unfold, managing costs and cycle time will become increasingly important to fab operations.

The tenth fundamental truth of process control for the semiconductor IC industry is:

Adding Process Control Reduces Production Costs and Cycle Time

Instrumental to having an efficient, low-cost fab is the ability to collect meaningful information about the process in a timely fashion. Process control tools (metrology and inspection) are the eyes and ears of the fab in that they provide insight into what’s working and what’s not: they are an investment in “process information.” In a 2007 paper2 the National Institute of Standards and Technology (NIST) estimated that the average return on investment for metrology alone was 300 percent.

Previous articles in this series have illustrated how process control can reduce costs by reducing the scrap and raw material costs associated with lost yield and reliability3 failures. Similarly, improving yield reduces the environmental footprint of fab operations per good die out.4 In this article, we will examine two other elements of cost reduction and factory efficiency enabled by process control:

  1. Process equipment re-use from node-to-node
  2. Improved net cycle time

Equipment Re-Use

The single biggest component of cost in a modern fab is capital depreciation. It can vary from company to company, but typically wafer fab capital equipment is depreciated at 20 percent per year over the course of five years. If you can extend the life of a piece of equipment beyond the point where it is fully depreciated you are essentially getting that tool for free. If you can find a way to re-use an entire group of process tools (scanners, etchers, etc.) the savings could easily be measured in tens or even hundreds of millions of dollars.

Ultimately, a process tool must meet the technical specifications that are demanded by the manufacturing process in which it is used. However, in cases where the tool’s capability is marginal, its lifetime can be extended by closer monitoring—using existing metrology or inspection tools to keep the tool operating within the required process specifications. Performing more frequent process tool qualifications can help improve matching and ensure that a tool does not drift out of spec. For stable feed-back and feed-forward schemes, having more in-line inspections provides better averaging and allows for better control of the actual process. In these situations, process control is helping to extend the life of existing process tools—adding process control in this context can actually save money.

The Process Capability Index (Cpk) is a metric that measures how well the natural variation of a process fits within the spec limits. For a centered process with a symmetric distribution the Cpk is given by equation 1,

Cpk = (USL – LSL) / 6σ                             Eq. 1

where USL and LSL are the upper and lower spec limits respectively and s is the standard deviation of the process. If the Cpk value is greater than one, the process is considered capable. Cpk values less than one indicate that the process is not capable.

Consider an etch process step where the Cpk of the CD measurement is exactly equal to one (i.e., the step is marginally capable in that the upper and lower spec limits are both three standard deviations from the mean). The marginal capability could be the fault of the previous photo step, the etch step or both. Either way it is an expensive proposition to upgrade either tool set to improve the Cpk—the capability —of the process.

Often the capability of the process can be improved by implementing a data feed-forward scheme—using additional metrology to fully characterize the process at one step (e.g., photo) and then feeding that information forward to adjust parameters at etch to effectively customize the process conditions for each lot or wafer. Figure 1 below shows an example Statistical Process Control (SPC) chart of the after-etch CD with and without feed-forward.

Figure 1. Left: SPC Chart of etch CD without feed forward (Cpk=1.0). Right: SPC Chart of etch CD with feed forward (Cpk=1.3)

Figure 1. Left: SPC Chart of etch CD without feed forward (Cpk=1.0). Right: SPC Chart of etch CD with feed forward (Cpk=1.3)

Feed-back and feed-forward schemes can be used to extend the useful lifetime of process tools by effectively increasing the process window in which they operate. CD measurements that are slightly off target at photo can be brought back on target by using that information to adjust the etch bias at the etch process step. 

Cycle Time

Cycle time is another very important production metric. We will give a more detailed account of cycle time in an upcoming paper but would like to touch briefly on the counter-intuitive relationship between cycle time and process control.

Any source of variability that prevents lots from moving through the fab in lock-step fashion will increase the cycle time. Adding inspection steps will add cycle time to those lots that get inspected but due to sampling (not every lot gets inspected) it will have a much smaller impact on the average. When an excursion does occur, comparatively few process tools will have to be put down (because the inspection points are closer together) and the module owner will be able to isolate the problem much sooner. The total disruption to the fab (the variability) will be reduced and the cycle time of all lots will be improved. This counter-intuitive concept has been demonstrated by several fabs that have both added inspection steps and reduced cycle time simultaneously.

To summarize, adding process control steps contribute to fab efficiency on several levels (figure 2): increasing baseline yield, extending the useful life of existing process tools, limiting the duration of excursions, and reducing cycle time.

Figure 2. The cascading benefits of process control.

Figure 2. The cascading benefits of process control.

As we conclude this series on the 10 fundamental truths of process control1,3,5-11, we thank you for reading. We hope that these articles have provided deeper insight into the value of process control and the base knowledge for successful implementation of process control in IC fabrication. We look forward to exploring additional aspects of process control in future Process Watch articles throughout the coming months.

References:

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Chemical precursors (inorganic and organic) used to form high dielectric constant (High-K) materials, metals and metal nitrides needed in advanced ICs are forecasted to reach $400M USD in global sales by 2020, as highlighted in TECHCET’s 2016 Critical Materials Report. Estimated to have totaled over $258M in 2015, this market consists of ~51% high-k metal precursors used for gate dielectrics and capacitors, and ~49% other metal precursors used for electrode and interconnect processes.

The largest usage for High K ALD and CVD (Atomic Layer Deposition and Chemical Vapor Deposition) precursors will continue to be capacitor formation for volatile memory devices through 2020. However, it is expected that revenues for High-K gate oxides processes may surpass memory capacitors by 2021. Compared to CVD, the ALD process relies on unique properties of precursors to self-limit reactions at the atomic level, so ALD precursors are generally chemically engineered complex molecules that command relatively higher average selling prices.

Atomic Layer Etching (ALE) is a new technology similar to ALD, in that alternating sequential surface-limited steps remove precise layers. When engineering atom-scale device features, chip fabricators will continue to rely on such high precision processes employing new and existing materials to enable high quality surfaces. Besides the physical plasma assisted path to ALE employing Cl2 and Ar ions, the chemical path to ALE uses metal organic compounds and hydro fluoric acid, and recent research is focused on using tin(II) acetylacetonate and other beta-diketonates.

Understanding the complex dynamics of materials interactions are critical to the successful use of novel processes and materials in IC HVM. Challenges and opportunities relating to the affordable, controllable, and safe implementation of new materials will be presented in detail at the Critical Materials Conference 2016—open to the public May 5-6, in Hillsboro, Oregon—in conjunction with the private Critical Materials Council (CMC) meetings. For more info on TECHCET’s Report or to Register for the CMC Conference, please go to www.cmcfabs.org/seminars/ or contact [email protected]

TECHCET’s work is focused on process materials supply-chains and materials technology trends for Semiconductor, Display, Solar/PV, and LED manufacturing industries. The company has been responsible for producing the Critical Material Reports for SEMATECH and the industry since 2000. This work continues to benefit the Critical Materials Council, now organized as CMC Fabs. For more info please go to: www.cmcfabs.org or www.techcet.com

Front-end fab equipment spending (including new, used, and in-house) is projected to increase 3.7 percent in 2016 (to US$ 37.2 billion) and another 13 percent in 2017 (to $42.1 billion) according to most recent edition of the SEMI World Fab Forecast.  Fab equipment spending for 2015 ended almost flat ($35.9 billion), with a slight decrease of -0.4 percent year-over-year.

The SEMI World Fab Forecast report presents details of fab-related spending through the industry and extends the outlook through the end of 2017.  Fab equipment spending is expected to pick up slowly in the first half of 2016, and accelerate into the second half when momentum starts to build for 2017, with a return to double-digit growth rates (see Figure 1).

Figure 1

Figure 1

The biggest contributors to the growth are foundries, 3D NAND fabs, and companies beginning to equip and prepare for the 10nm ramp-up in 2017. Dedicated foundries continue to represent the largest spending segment. Spending for 2015 dropped slightly from $10.7 billion to $9.8 billion (-8 percent YoY), but is expected to increase by 5 percent in 2016 and almost 10 percent in 2017.

DRAM spending ranks second place after foundries. After a strong 2015, DRAM spending is expected to slow in 2016 (-23 percent) and increase again in 2017 by 10 percent.

In terms of spending growth rates, the big momentum comes from 3D NAND (including 3D XPoint). Spending doubled from about $1.8 billion in 2014 to $3.6 billion in 2015, 101 percent growth. In 2016, it will again rise to more than $5.6 billion (50 percent growth).

The increase in equipment spending is also supported by six companies, which are among the top 10 spenders globally. The six have announced plans to increase their respective capital expenditures in 2016, while the assumption for the largest spender, Samsung, is that capital expenditure will be less than in 2015.

Equipment spending growth for 2017 is also buoyed by new 24 facilities (excluding R&D) which began construction in 2015 or will begin construction this year. These projects are located around the world, including eight planned in China alone.

The industry has recently set records for mergers and acquisitions, and more are expected in 2016.  The combined flat growth for semiconductor equipment spending in 2015 and slow growth in 2016 confirm a more mature industry.  New technologies — new nodes and newer memory devices — will drive the increase in spending currently forecasted for 2017.

Learn more about SEMI fab databases at: www.semi.org/en/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats

The emerging market for silicon carbide (SiC) and gallium nitride (GaN) power semiconductors is forecast to pass the $1 billion mark in five years, energized by demand from hybrid and electric vehicles, power supplies and photovoltaic (PV) inverters. Worldwide revenue from sales of SiC and GaN power semiconductors is projected to rise to $3.7 billion in 2025, up from just $210 million in 2015, according to IHS Inc. (NYSE: IHS), a global source of critical information and insight. Market revenue is also expected to rise with double digit growth annually for the next decade.

SiC Schottky diodes have been on the market for more than 10 years, with SiC metal-oxide semiconductor field-effect transistors (MOSFET), junction-gate field-effect transistors (JFET) and bipolar junction transistors (BJT) appearing in recent years, according to the latest information from the latest IHS SiC & GaN Power Semiconductors Report. SiC MOSFETs are proving very popular among manufacturers, with several companies are already offering them, and more are expected to in the coming year. The introduction of 900 volt (V) SiC MOSFETs, priced to compete with silicon SuperJunction MOSFETs, as well as increased competition among suppliers, forced average prices to fall in 2015.

“Declining prices will spur faster adoption of the technology,” said Richard Eden, senior market analyst for power semiconductor discretes and modules at IHS Technology. “In contrast, GaN power transistors and GaN modules have only just recently appeared in the market. GaN is a wide bandgap material offering similar performance benefits to SiC, but with greater cost-reduction potential. This price and performance advantage is possible, because GaN power devices can be grown on silicon substrates that are larger and less expensive than SiC. Although GaN transistors are now entering the market, the development of GaN Schottky diodes has virtually stopped.”

By 2020, GaN-on-silicon (Si) devices are expected to achieve price parity with — and the same superior performance as — silicon MOSFETs and insulated-gate bipolar transistors (IGBTs). When this benchmark is reached, the GaN power market is expected to surpass $600 million in 2025. In contrast, the more established SiC power market — mainly consisting of SiC power modules — will hit $3 billion in the same time period.

By 2025, SiC MOSFETs are forecast to generate revenue exceeding $300 million, almost catching Schottky diodes to become the second best-selling SiC discrete power device type. Meanwhile, SiC JFETs and SiC BJTs are each forecast to generate much less revenue than SiC MOSFETs, despite achieving good reliability, price and performance. “While end users now strongly prefer normally-off SiC MOSFETs, so SiC JFETs and BJTs look likely to remain specialized, niche products,” Eden said; “however, the largest revenues are expected to come from hybrid and full SiC power modules.”

Hybrid SiC power modules, combining Si IGBTs and SIC diodes, are estimated to have generated approximately $38 million in sales in 2015 and full SiC power modules are only two or three years behind in the ramp-up cycle. Each module type is forecast to achieve over $1 billion in revenue by 2025.

The IHS SiC & GaN Power Semiconductors Report is based on more than 50 semiconductor supply chain and potential end-user interviews. It provides detailed global analysis of this fast-moving market and explains growth drivers and likely adoption rates in major application sectors.

IC Insights recently released its new Global Wafer Capacity 2016-2020 report that provides in-depth detail, analyses, and forecasts for IC industry capacity by wafer size, by process geometry, by region, and by product type through 2020.  Figure 1 breaks down the world’s installed monthly wafer production capacity by geographic region (or country) as of December 2015.  Each regional number is the total installed monthly capacity of fabs located in that region regardless of the headquarters location for the companies that own the fabs.  For example, the wafer capacity that South Korea-based Samsung has installed in the U.S. is counted in the North America capacity total, not in the South Korea capacity total.  The ROW region consists primarily of Singapore, Israel, and Malaysia, but also includes countries/regions such as Russia, Belarus, Australia, and South America.

Figure 1

Figure 1

Some highlights of regional IC capacity by wafer size are shown below.

As of Dec-2015, Taiwan led all regions/countries in wafer capacity with nearly 22% of worldwide IC capacity installed in the country.  Taiwan surpassed South Korea in 2015 to become the largest capacity holder after having passed Japan in 2011.  China became a larger wafer capacity holder than Europe for the first time in 2010.

For wafers 150mm in diameter and smaller, Japan was the top region in terms of the amount of capacity.  The fabs running small size wafers tend to be older and typically process low-complexity, commodity type products or specialized devices.

The capacity leaders for 200mm wafers were Taiwan and Japan.  There have been many 200mm fabs closed over the past several years, but not in Taiwan and that resulted in the country becoming the largest source of 200mm capacity beginning in 2012.  With Taiwan being home to most of the IC industry’s foundry capacity, the country’s share of 200mm capacity will likely rise further in the coming years.

For 300mm wafers, South Korea was at the forefront, followed by Taiwan.  Taiwan lost its position as the leading supplier of 300mm wafer capacity in 2013.  That was in large part because ProMOS closed its large 300mm fabs, but it was also due to Samsung and SK Hynix continuing to expand their fabs in South Korea to support their high-volume DRAM and flash businesses.

According to IC Insights’ new 2016 edition of The McClean Report, total worldwide semiconductor industry capital spending is forecast to show low single-digit growth in 2016 after registering a 1% decline in 2015.  As discussed below, last year’s drop in semiconductor industry capital spending was a significant departure from historical patterns that go back more than 30 years.

Figure 1 shows the annual worldwide semiconductor industry capital spending changes from 1983-2015.  Over the past 33 years, there have been six periods when semiconductor industry capital spending declined by double-digits rates for one or two years (1985-1986, 1992, 1997-1998, 2001-2002, 2008-2009, and 2012-2013).  It is interesting to note that in every case except the 2012-2013 spending downturn, within two years after the period of decline in capital spending, a surge in spending of at least 45% occurred.  The second year increases in spending after the cutbacks were typically stronger than the first year after a downturn with the lone exception to this being the 2010 spending rebound after the 2008-2009 downturn.  This was because most semiconductor producers tend to act very conservatively coming out of a market slowdown and wait until they have logged about 4-6 quarters of good operating results before significantly increasing their capital spending again.

As shown in Figure 1, the streak of strong capital spending growth within two years after a spending cutback timeperiod ended in 2015, with capital spending registering a 1% decline.  IC Insights believes that this is yet another indication of a maturing semiconductor industry.

Figure 1

Figure 1

More detailed information on semiconductor industry capital spending, including 2016 capital spending forecasts by company, can be found in IC Insights’ flagship market research report, The McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry. The new 478-page McClean Report provides IC market and technology trend forecasts from 2016 through 2020.