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Viewpoints: 2016 outlook


January 11, 2016

Each year, Solid State Technology turns to industry leaders to hear viewpoints on the technological and economic outlook for the upcoming year. Read through these expert opinions on what to expect in 2016.

New technologies will fuel pockets of growth in 2016

Plisinski_headshotBy Mike Plisinski, Chief Executive Officer, Rudolph Technologies, Inc.

While the 2016 outlook for the semiconductor industry as a whole appears increasingly uncertain, there are areas where significant growth remains likely. In particular, advanced packaging, driven by growing consumer demand in applications ranging from smartphones and tablets to the Internet of Things (IoT), shows great promise for continued innovation.

First, we see outsourced assembly and test (OSAT) manufacturers driving the development of new packaging technology. For example, we’ve seen major gains in the adoption of fan-out packaging and copper pillar technology, evidenced by ongoing capacity expansion, and the addition of new players—the most obvious perhaps being the large ongoing investment by a leading foundry in Asia where our inspection equipment has received a prominent role. We see more and more manufacturers choosing to add yield management and/or advanced process control (APC) software, to obtain a competitive advantage in not only cost, but also reliability. This is achieved by transforming ultra-large data sets into useful information used for predictive analytics (reducing costs) and analysis across the supply chain (improving reliability).

The growth in advanced packaging is also driving the adoption of sophisticated lithography techniques for these new technologies. Our JetStep advanced packaging stepper is now in high-volume manufacturing use at several top OSATs. The system allows our customers the flexibility to handle all of the current advanced processes within a single tool, which provides a compelling cost of ownership value. We also see emerging processes, such the adoption of rectangular panel substrates, in some packaging applications, certainly in fan-out, but also embedded and other packaging technologies. Rectangular panels promise significant gains in economy-of-scale and processing efficiency.

Lastly, expansion in radio frequency (RF) device capability continues to grow, with the increasing number of devices that communicate wirelessly and the increasing number of frequencies with which they communicate. Measuring the electrode and piezo layers of SAW/BAW filters will only grow as more and more filters are required in mobile devices. Beyond mobile, the expansion in RF is also driven by WiFi, Bluetooth and IoT requirements for connectivity, so we expect it to accelerate even as the smartphone growth curve flattens.

Worldwide semiconductor revenue totaled $333.7 billion in 2015, a 1.9 percent decrease from 2014 revenue of $340.3 billion, according to preliminary results by Gartner, Inc. The top 25 semiconductor vendors’ combined revenue increased 0.2 percent, which was more than the overall industry’s growth. The top 25 vendors accounted for 73.2 percent of total market revenue, up from 71.7 percent in 2014.

“Weakened demand for key electronic equipment, the continuing impact of the strong dollar in some regions and elevated inventory are to blame for the decline in the market in 2015,” said Sergis Mushell, research director at Gartner. “In contrast to 2014, which saw revenue growth in all key device categories, 2015 saw mixed performance with optoelectronics, nonoptical sensors, analog and ASIC all reporting revenue growth while the rest of the market saw declines. Strongest growth was from the ASIC segment with growth of 2.4 percent due to demand from Apple, followed by analog and nonoptical sensors with 1.9 percent and 1.6 percent growth, respectively. Memory, the most volatile segment of the semiconductor industry, saw revenue decline by 0.6 percent, with DRAM experiencing negative growth and NAND flash experiencing growth.”

Intel recorded a 1.2 percent revenue decline, due to falls in PC shipments (see Table 1). However, it retained the No. 1 market share position for the 24th year in a row with 15.5 percent market share. Samsung’s memory business helped drive growth of 11.8 percent in 2015, and the company maintained the No. 2 spot with 11.6 percent market share.

Table 1. Top 10 Semiconductor Vendors by Revenue, Worldwide, 2015 (Millions of Dollars)

Rank 2014

Rank 2015

Vendor

2014 Revenue 

2015 Estimated Revenue 

2014-2015 Growth (%)

2015 Market Share (%)

1

1

Intel

52,331

51,709

-1.2

15.5

2

2

Samsung Electronics

34,742

38,855

11.8

11.6

5

3

SK Hynix

15,997

16,494

3.1

4.9

3

4

Qualcomm

19,291

15,936

-17.4

4.8

4

5

Micron Technology

16,278

14,448

-11.2

4.3

6

6

Texas Instruments

11,538

11,533

0.0

3.5

7

7

Toshiba

10,665

9,622

-9.8

2.9

8

8

Broadcom

8,428

8,419

-0.1

2.5

9

9

STMicroelectronics

7,376

6,890

-6.6

2.1

12

10

Infineon Technologies

5,693

6,630

16.5

2.0

Others

157,992

153,182

-3.0

41.2

Total

340,331

333,718

-1.9

100

Source: Gartner (January 2016)

“The rise of the U.S. dollar against a number of different currencies significantly impacted the total semiconductor market in 2015,” said Mr. Mushell. “End equipment demand was weakened in regions where the local currency depreciated against the dollar. For example in the eurozone, the sales prices of mobile phones or PCs increased in local currency, as many of the components are priced in U.S. dollars. This resulted in buyers either delaying purchases or buying cheaper substitute products, resulting in lower semiconductor sales. Additionally, Gartner’s semiconductor revenue statistics are based on U.S. dollars; thus, sharp depreciation of the Japanese yen shrinks the revenue and the market share of the Japanese semiconductor vendors when measured in U.S. dollars.”

The NAND market continued to deteriorate throughout the year. As a result, revenue grew only 4.1 percent in 2015, fueled by elevated supply bit growth that resulted in an aggressive pricing environment. The tumultuous NAND pricing environment rippled through most of the NAND solutions, particularly solid-state drives (SSDs), which continue to encroach on hard-disk drives (HDDs). The ensuing price war in SSDs further pressured the profitability of the NAND flash makers amid the biggest technology transition in flash history — 3D NAND. While 3D NAND commercialization was modest, it was limited to only one vendor — Samsung. Modest revenue gains have not stopped investment in NAND flash and 3D technology, with all vendors continuing to spend aggressively in the technology and most with new fabs.

After 32.0 percent revenue growth in 2014, the DRAM market hit a downturn in 2015. An oversupply in the commodity portion of the market caused by weak PC demand led to severe declines in average selling prices (ASPs), and revenue contracted by 2.4 percent compared with 2014. The oversupply and the extent of ASP declines could have been significantly worse if Micron Technologies’ bit growth had performed in line with its South Korean rivals. Fortunately for the market, the company saw negative bit growth due to its transition to 20 nm, sparing the industry from an even more severe downturn.

Additional information is provided in the Gartner report “Market Share Analysis: Semiconductors, Worldwide, Preliminary 2015 Estimates.”

IC Insights has released its Global Wafer Capacity 2016-2020 report that provides in-depth detail and analysis of IC industry capacity by wafer size, by process geometry, by region, and by product type. The new report provides a ranking of the industry’s 25 largest IC manufacturers in terms of installed capacity as of December 2015.  The top 10 capacity leaders are shown in Figure 1.  Among the world’s top 10 capacity leaders in 2015 were four companies headquartered in North America, two companies based in South Korea and in Taiwan, and one company each from Europe and Japan. The list includes the world’s four largest memory suppliers, three largest foundries, the largest microprocessor supplier, and Texas Instruments and ST—the two biggest suppliers of analog ICs.

Figure 1

Figure 1

Collectively, the top 10 leaders had installed capacity of 11,737K wafers/month at the end of the year, which equates to 72% of global capacity and up slightly from 10,885K wafers/month or 71% in 2014.

  • As of December 2015, Samsung had the most installed wafer capacity with 2.5 million 200mm-equivalent wafers per month, which represented 15.5% of the world’s total capacity with most of it used for the fabrication of DRAM and flash memory devices.
  • Second in line was the largest pure-play foundry in the world TSMC with about 1.9 million wafers per month capacity, or 11.6% of total worldwide capacity.
  • Micron substantially increased its available capacity in recent years primarily through acquiring existing capacity from others. With the addition of the Elpida and Rexchip fabs as well as the extra Inotera capacity, Micron first became the third-largest wafer capacity holder in the world in 2013. Micron had the sixth-largest amount of wafer capacity in 2012, and in the beginning of that year the company acquired Intel’s stake in two IM Flash Technologies fabs, giving Micron access to all the capacity from those fabs.
  • The fourth-largest capacity holder at the end of 2015 was Toshiba with about 1.3 million in monthly wafer capacity (8.2% of total worldwide capacity), including a substantial amount of flash memory capacity for joint-investor/partner SanDisk.
  • Rounding out the top 5 companies was another memory IC supplier SK Hynix with 1.3 million wafers/month (8.1% of total worldwide capacity).
  • Intel’s capacity declined slightly in 2015 because of the company’s Fab 68 in China being taken off-line while it is converted from the production of logic chipsets to next-generation flash memory (3D NAND and XPoint).

Given the skyrocketing cost of new wafer fabs and manufacturing equipment and as more IC companies transition to a fab-lite or fabless business model, IC Insights expects that an even greater percentage of fab capacity will be in the hands of fewer suppliers through the end of the decade.

By Denny McGuirk, SEMI president and CEO

“In like a lion, out like a lamb” is just half the story for 2015.  While initial expectations forecasted a double-digit growth year, the world economy faded and dragged our industry down to nearly flat 2015/2014 results.

However, 2015 will be remembered for a wild ride that fundamentally changed the industry.  In 2015 a wave of M&A activity swept across the industry supply chain — unlike any single year before — with scores of transactions and notable multi-billion dollar companies being absorbed.  In 2016, we all will be working within a newly reconfigured supply chain.

Increasingly, in this business landscape, collaboration is required simultaneously across the extended supply chain — customers’ customers’ customers are now routinely part of the discussion in even unit process development.  Facilitating interaction and collaboration across the extended supply chain is part of what SEMI does and I’ll be updating you in next week’s letter on how, but first, let’s review what’s happened and what’s happening.

2015 Down 1%: “In Like a Lion, Out Like a Lamb”

2015 had an optimistic start with a strong outlook and good pace in Q1 and 1H.  In January 2015 forecasters projected semiconductor equipment and materials growing in a range of 7 percent to nearly 14 percent vs. 2014.  Global GDP, as late as May 2015, was pegged at 3.5 percent for 2015 after coming in at only 3.4 percent in 2014.  In August, estimates dropped to 3.3 percent, in November estimates dropped further to 3.1 percent for the year.

As our industry has matured, semiconductor equipment and materials growth rates are ever more tightly correlated to shifts in global GDP.  With global GDP unexpectedly dropping, the second half saw declining book-to-bill activity and the year will likely end flat or slightly negative for 2015.  Though nearly flat, the numbers are still impressive with a healthy $37.3 billion annual revenue for semiconductor manufacturing equipment and $43.6 billion for semiconductor materials.

An important change is since the 2009 financial crisis, electronics, chips, and semiconductor equipment and materials markets have been much more stable year-to-year than in the years prior to 2009.  Also, the movement of the three segments is much more synchronized compared to the earlier years of boom and bust. For SEMI’s members this means cycles are becoming more muted — enabling members to shift business models accordingly to better maintain prosperity.

Fab-Equipmt-600w Capital-Equip-600w

 

2015’s $125+ Billion M&A:  Inflection Point for Silicon Valley Icons and Global Titans

2015 is a year that will be viewed as an inflection point in our industry.  The unprecedented M&A volume (more than $125 billion for semiconductor related companies) and the size of individual deals through the electronics supply chain will forever  change the industry.

historic-proportions

While there have been waves of consolidation for semiconductor Integrated Device Manufacturers (IDMs) in the 1980s and 1990s, and semiconductor equipment and materials in the 1990s and 2000s, the fabless semiconductor companies are the latest wave undergoing consolidation.  Although, in 2015, not just fabless, but all segments saw major deals — even iconic chemical brands DuPont and Dow Chemical announced their intention to merge.

Large and familiar brands like Broadcom (Avago), SanDisk (Western Digital), Altera (Intel), Freescale (NXP), and KLA-Tencor (Lam Research) have been merged and will continue forward as part of their acquirers.  China is on the move with its ambitions to quickly grow its indigenous semiconductor supply chain with recent acquisitions of ISSI, OmniVision, NXP RF power unit, and notably Mattson in the semiconductor equipment segment.

In an age when new fab costs are pushing double-digit billions of dollars and leading-edge device tapeouts are surpassing $300 million per part, consolidation is a strategy to increase scale, leverage R&D, and compete better.  For SEMI’s members, the winner-take-all stakes increase and raise expectations for technology, product performance, application development, speed, and support.  This, in turn, means that SEMI members have an increased need for a newly drawn pre-competitive collaboration model along the extended electronics supply chain and for Special Interest Groups (SIGs) to drive collective action in focused sub-segments and for specific issues.

Collaboration-is-critical-6

Source: SEMI (www.semi.org), 2015

2016 Up ~1%: Stay Close to your Customer and your Customer’s Customer and …

Current projections for semiconductor equipment and materials suggest that 2016 will not be a high growth year.  The span of forecasts ranges from almost -10 percent to +5 percent.  At SEMI’s Industry Strategy Symposium (ISS), 10-13 January, we will be taking a deep-dive into the 2016 forecast and on the business drivers and will have a much better picture of the consensus outlook.

However, it is already quite clear that following this enormous wave of consolidation, the industry will look different and will offer new and different opportunities.  Listening to SEMI’s members, I’ve heard that during this period of upheaval it’s absolutely critical to stay close to one’s customers – but more than that – to have access and ongoing direct dialogue with the customer’s customer … and customers’ customers’ customers.

In light of the cost of research and development, the magnitude of risks, and the speed of new consumer electronics adoption, SEMI members find that they need to intimately know emerging requirements two to three steps away in the supply chain, and may require rapid and innovative development from their own sub-suppliers to meet product delivery in time.  In parallel, we see system integrators (electronics providers) staffing up with semiconductor processing engineers and equipment expertise, both for differentiation of their own products and for potential strategic vertical manufacturing.

2016 will mark an acceleration of collaboration and interdependence across the extended supply chain.  Next week, I’ll provide an update letter on SEMI’s related activities with an overview of what SEMI is doing to meet the realities of a reshaped industry.  SEMI’s role is evolving, and more important now than ever, in helping the industry achieve together, what it cannot accomplish alone.

SEMI-Infographic--Achieving

Learn more about SEMI membership and upcoming events.

Mark Adams, President of Micron Technology

Micron Technology, Inc. today announced that President Mark Adams will resign for personal health reasons. He will remain with the company until February 1, 2016, to support the transition.

Adams joined Micron in June 2006 and has served as President since February 2012.

“Mark has been a stellar leader and contributor to Micron’s growth and success during his time with the company,” said Micron CEO Mark Durcan. “We thank him for his dedication and service and wish him the very best with his recovery and into the future.”

Micron Technology, Inc., is a global leader in advanced semiconductor systems. Micron’s portfolio of high-performance memory technologies—including DRAM, NAND and NOR Flash—is the basis for solid state drives, modules, multichip packages and other system solutions.

In 2015, Chinese state-owned, chip-design company Tsinghua Unigroup Ltd. tried unsuccessfully to buy Micron for $23 billion.

2016 bounce to modest gains


December 14, 2015

By Christian G. Dieseldorff, Industry Research & Statistics Group, SEMI

SEMI just published the latest quarterly update of its World Fab Forecast report.  While the year started with a positive outlook, the initial optimism has largely deflated, and the year will end largely flat. Fab equipment spending growth (new and used) for 2015 is expected to be 0.5 percent (US$ 35.8 billion). For 2016, spending is forecast to grow by 2.6 percent ($36.7 billion), with a possible continued upward trend.

Past trends prove again the close correlation of spending to global GDP and revenue.  The IMF predicted worldwide GDP to grow by 3.5 percent back in May, and has revised it down to only 3.1 percent.  Likewise, as of May, the year’s average revenue growth for the semiconductor industry was predicted to be in the mid- to high-single digits (according to ten leading market research firms).  Now these firms have revised their 2015 predictions to an average of just 1.3 percent.

Fab equipment spending (new, used and in-house) follows the same rollercoaster as revenue, and is now expected to grow by only 0.5 percent by the end of 2015, possibly 1 percent, according to SEMI.

Fab-Equipment-Spending

In 2015, 80 to 90 percent of fab equipment spending went to 300mm fabs, while only 10 percent was for 200mm or smaller.  SEMI’s recently published “Global 200mm Fab Outlook” provides more detail about past and future 200mm activities.

Cherish the Memory

Examining fab equipment spending by product type, Memory accounts for the largest share in 2015 and 2016. In 2015, DRAM spending was second in place but in 2016 3D Flash will, by far, outspend DRAM.

Most DRAM spending in 2015 went towards 21/20nm ramp.  In 2016, DRAM companies are expected to start risk production of 1xnm (for example, Samsung in 1H 2016; Hynix in 2H 2016; and Micron in 2016).

While 2015’s spending was dominated by DRAM, SEMI reports that 2016 will be dominated by Flash, mainly 3D-related architectures.  Capacity for 3D-NAND will continue to surge.  SEMI’s report tracks 10 major 3D producing facilities, with a capacity expansion of 47 percent in 2015 and 86 percent in 2016.

Foundry Segment Holds Steady

The Foundry segment is next in terms of the largest share of fab equipment spending in 2015 and 2016.  In general, the foundry segment shows steadier, more predictable spending patterns than other device product segments. The largest foundry player, TSMC, has a strong impact on the foundry industry.  In the second half of 2015, TSMC cut 2015 capex from $10.5 billion to $8 billion, due to a flagging market.  SEMI expects a stronger fourth quarter in 2015 for equipment spending for foundry as TSMC fulfills its capital expenditure for the year and we expect an increased capex in 2016.

TSMC recently announced revenue expectation for 2016 to be in double digits and expects to increase capex for 2016 as it ramps 16nm and adds initial 10nm capacity.

It’s Only Logical (and MPU)

Coming in third place in fab equipment spending, MPU had lower spending in 2015.  Intel revised its planned capex down four times, from $10 billion to $8.7 billion then to $7.7 billion, and finally to $7.3 billion, and it decided to delay the launch of 10nm products (Cannonlake) to 2H17.  Intel still announced lofty plans for 2016 capex, around $10 billion.  Especially in 2H16, spending will pick up for anticipated 10nm activities.

Meanwhile for Logic spending has been very strong in 2015, with 90 percent growth, driven by SONY’s CMOS image sensors.  This exuberant growth, however, is expected to slow down in 1H16.

Consequence of Consolidations: the End of Wild Times?

Between 2010 and 2014, change rates for equipment spending fluctuated wildly, from +16 percent in 2011 to -16 percent in 2012, -8 percent in 2013 to 15 percent in 2014. These drastic changes have been replaced by dampened spending growth rate for 2015 and into 2016.  Multiple reasons may apply: a more mature and lower growth industry, increased caution regarding capacity ramp, or perhaps the recent frenzy of consolidations further concentrating capex spending.  SEMI’s next quarterly publication, in February 2016, will give further insight into early indicators of 2017.  Will sedate, positive spending growth continue?

The SEMI World Fab Forecast Report in Excel format, tracks spending and capacities for 1,167 facilities across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities. It uses a bottoms-up approach methodology, providing high-level summaries and graphs and in-depth analyses of capital expenditures, capacities, technology and products by fab.  Learn more about the SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats

Worldwide semiconductor fab equipment capital expenditure growth (new and used) for 2015 is expected to be 0.5 percent (total capex of US$35.8 billion), increasing another 2.6 percent (to a total of $36.7 billion) in 2016, according to the latest update of the quarterly SEMI World Fab Forecast report.

SEMI reports that in 2015, Korea outspent all other countries ($9.0 billion) on front-end semiconductor fab equipment, and is expected to drop to second place in 2016 as Taiwan takes over with the largest capex spending at $8.3 billion. In 2015, Americas ranked third in overall regional capex spending with about $5.6 billion and is forecast to increase only slightly to (5.1 percent) in 2016.

fab equipment spending 2016

In 2015, 80 to 90 percent of fab equipment spending went to 300mm fabs, while only 10 percent was for 200mm or smaller.  SEMI’’s recently published “Global 200mm Fab Outlook” provides more detail about past and future 200mm activities.

Examining fab equipment spending by product type, Memory accounts for the largest share in 2015 and 2016.  While 2015’s spending was dominated by DRAM, the SEMI World Fab Forecast reports that 2016 will be dominated by Flash, mainly 3D-related architectures.  Capacity for 3D-NAND will continue to surge. SEMI’’s report tracks 10 major 3D producing facilities, with a capacity expansion of 47 percent in 2015 and 86 percent in 2016.

The Foundry segment is next in terms of the largest share of fab equipment spending in 2015 and 2016.  In general, the foundry segment shows steadier, more predictable spending patterns than other device product segments. Coming in third place in fab equipment spending, MPU had lower spending in 2015.  Logic spending was very strong in 2015, with 90 percent growth, driven by SONY’s CMOS image sensors.

Throughout 2015, SEMI anticipates that there will be 1,167 facilities worldwide investing in semiconductor equipment in 2016, including 56 future facilities across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities. For further details, please reference to the latest edition of SEMI’s World Fab Forecast report.

Beyond economic limits due to litho limitations, the inherent need for a physical barrier puts an electrical limit on the ability to scale.

BY ED KORCZYNSKI, Senior Technical Editor

On-chip interconnects for ICs have evolved to meet different exacting needs, and the most advanced chips require multiple levels of copper (Cu) metal lines and via connections between transistors. When scaling Cu lines to the finest dimensions possible to interconnect local transistors in advanced manufacturing nodes, there are economic limits due to lithography technology. Also, the inherent need for a physical barrier to surround Cu and prevent poisonous out-diffusion imposes an electrical limit on the ability to scale. Best practices today include an explicit hierarchy of dimensions and a stacking-order for on-chip interconnects: local between nearby transistors, global between functional blocks, as well as input/output (I/O) and power/ ground connections. With advanced logic chips having >12 levels of on-chip copper metallization, only the bottom-most are at the tightest pitch. Table1 (courtesy of imec) shows the hierarchy of interconnect signals for a 14nm-node finFET logic chip, and the tightest pitch is 42nm as used for the vertical gate contacts as well as for the metal-1 (M1) and metal-2 (M2) levels. The last published International Technology Roadmap for Semiconductors (ITRS) chapter for Interconnects that included detailed tables of on-chip metal specifications was published in 2012. In the ITRS 2012 Interconnect chapter Table 2 on microprocessor (MPU) requirements, the “Intermediate Wires” specification for Metal 2 (M2) is the same as for Metal 1 (M1) level and shows 32nm half-pitch is manufacturable, which is used with MPU physical gate lengths of 22nm.

interconnects table

FIGURE 1 shows the fraction of the intermediate wire volume that is Cu depending on the thickness of the barrier for succeeding generations of high-performance (HP) MPUs. Note that in the SEM cross-section on the right that the 10nm of Cu is only 50% of the line thickness, and that such a line would be extremely susceptible to current-crowding and premature circuit failure due to electro-migration (EM).

interconnects 1

In minimally-scaled Cu wiring, resistivity increases arise due to electron scattering from the sidewalls and grain boundaries. Tricky process integration involving electro-chemical deposition (ECD) of the Cu along with careful thermal annealing is already being used to grow large columnar grains across the trench—resembling bamboo when cut in cross-section—to minimize the volume of grain-boundaries. Forming columnar lines of single Cu grains after ECD requires control of barrier atomic-layer deposition (ALD) parameters, along with chemical-mechanical planarization (CMP) and rapid-thermal annealing (RTA) processes.

When engineering materials, first-order parameters to be controlled include composition and uniformity, while second-order parameters include internal structure such as crystal orientation or average crystal grain-size in multi-crystalline structures. In general, it is more difficult and far more expensive to control second-order parameters in manufacturing, and when engineering at the atomic scale it is yet more difficult to control third- order parameters such as grain boundary orientation.

Since the industry must control third-order parameters to continue using Cu metal, there has been ongoing R&D of non-metallic materials that could be integrated into ICs as on-chip conductors. Superconductors have been found that can exhibit zero resistance to electric current flow, but only when they are frozen to extremely low temper- atures such that phonon vibrations within their lattices settle out. Recently, a team of six Japanese research groups tested nearly 1000 materials over a four year period and found no superconductors with critical temperatures (Tc) above the 298°K of room temperature.

The rapid increase in resistivity when Cu lines are scaled to minimal dimensions motivates the search for “ballistic” conductors which are immune from electron scattering effects. While R&D into graphene and Carbon Nano-Tubes (CNT) as on-chip conductors continues, there are inherent issues with integrating any such technologies into high-volume manufacturing (HVM) to achieve superior performance compared to legacy Cu. The ITRS 2012 Interconnects chapter summarizes the issues:

Ballistic transport in one dimensional systems, such as silicides, carbon nano tubes, nanowires, graphene nanoribbons or topological insulators offers potential solutions. While ballistic transport has many advantages in narrow dimensions, most of these options incur fundamental, quantized resistances associated with any conversions of transport media, such as from Cu to CNTs. In addition to the quantum resistance, the technological problems of utilizing an additional conduction medium with its interface, substrate and integration issues, pose substantial barriers to the imple- mentation of ballistic transport media.

Imec recently published preliminary “7nm-node” finFET specifications for logic ICs having 14nm gate lengths, with expectation that delays in the implementation of EUV lithography call for use of multiple-patterning using 193-immersion (193i). M1 layer patterning at 18nm half-pitch can be done with self-aligned double- patterning (SADP) technology, while Litho-Etch-Litho- Etch (LELE) patterning with two masks allows for 24nm half-pitch patterning of more arbitrary 2D shapes for easier routing. Going to tighter half-pitches will require Litho-Etch-Litho-Etch-Litho-Etch (LELELE) with three masks, or self-aligned quadruple patterning (SAQP) schemes, which is why the number of metal levels for logic continues to increase with each successive node.

In memory chips with regular bit arrays for storage and orthogonal bit:word architectures, leading 3D architectures use similar metal interconnect half-pitches. FIGURE 2 shows a new 3D stacked NAND Flashmemoryarchitecturethatwill be shown at the 2015 IEEE International Electron Device Meeting (IEDM) in presentation 3.2, “A Novel Double-Density, Single-Gate Vertical Channel (SGVC) 3D NAND Flash That Is Tolerant to Deep Vertical Etching CD Variation and Possesses Robust Read-disturb Immunity,” by Hang-Ting Lue et al. of Macronix.

interconnects 2

The Metal Level 2 Bit Line (ML2 BL) half-pitch of ~25nm in parallel lines in this 3D NAND structure can be formed with SADP litho. Since SADP has been used in HVM of 2D NAND cells, presumably the complex SADP integrated process flow has already been established. Imec has shown ability to reach 18nm half-pitch with SADP 193i, so this new 3D NAND structure might be able to be shrunk by a “half-node” without having to re-engineer the ML2 BL fab process flow.

Even if the lithographic cost of scaling metal lines to <18nm half-pitch could be managed, the Cu barrier provides a functional limit as shown in Fig. 1. Assuming that Cu multi-level interconnects will be current-limited and will require ~3nm barriers—to prevent out-diffusion from the line as well as EM-induced diffusion within the line—the industry is already considering atomic limits. The barrier would be ~1/3 of 18nm, ~1/2 of 12nm, and ~2/3 of 9nm wide Cu lines.

It is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating.

BY KEITH BEST, Rudolph Technologies, Wilmington, MA, and PHILLIP HOLMES, TEL NEXX, Billerica, MA

Recent years have seen rapid development in the area of advanced packaging. In general, advanced packaging processes are concerned with the interconnection of multiple chips in a single package to provide increased functionality and performance in a smaller volume. System Scaling Technology — the combination of front-end, middle-end and back-end to advance microelectronic systems—utilizes many different advanced packaging approaches, one of which is known as 2.5D packaging. The term “2.5D packaging” has not always been used consistently in literature. The definition used for the purpose of this paper can be summarized as follows: a 2.5D package utilizes an interposer between multiple silicon die and a system-in-package (SiP) substrate, where this interposer has through vias connecting the metallization layers on its front and back surfaces (FIGURE 1).

FIGURE 1. A 2.5D IC/SiP using an interposer and through vias.

FIGURE 1. A 2.5D IC/SiP using an interposer and through vias.

 

The development of these new packaging schemes is being driven primarily by the rapid growth in mobile handheld devices such as smartphones. Often, the manufacturing processes used are adaptations of well-established front-end processes. A number of different approaches are in development or already in production, including wafer-level chip scale packaging, copper pillar bumps on through silicon vias (TSVs), fan-out wafer level processing, and many more. Of particular interest is the replacement of solder bumps by fine pitch copper pillar bumps, which has been the subject of many new system- in-package designs. Here we investigate the lithography and plating of copper pillars, with focus on heights in excess of 100μm and diameters of 25μm, in anticipation of future SiP requirements.

The increase in the number of I/O channels required by multi-chip system designs has exceeded the density and pitch capabilities that traditional solder bump processes can deliver, so that an alternative connection scheme is required. For interposers, the key enabling technology has been the development of fine pitch copper pillar bumps to provide the high-density interconnection between the interposer and the die. Copper pillar bumps provide a number of advantages over the solder bumps they are supplanting. They can deliver finer pitches, 40μm and less have been demonstrated. They also provide superior electromigration performance in applications where high current-carrying capacity is required. However, lithography and electroplating for fine pitch copper pillar bumps can be particularly challenging. The pillars are electroplated into openings in a thick layer of photoresist which exceeds the capability of most front-end tools. Typically, today’s copper pillars range from 30-50μm in height, with height to width aspect ratios from 1:1 to around 2:1 Here we describe the lithography, resist, and electroplating systems and processes required to create 5:1 aspect ratio copper pillars with heights in excess of 100μm.

Photoresist

A negative tone photoresist (JSR THB-151N) was chosen for this work. Its acrylate groups cross-link on exposure and are developed in industry standard 2.38% TMAH developer. The photoresist was spun to a thickness of 120μm on 300mm silicon wafers with an under bump metallization (UBM) prepared seed layer. To reach the 120μm photoresist film thickness, two coatings of photoresist were required, soft baked at 130C, 300secs and 130C, 360secs respectively. After coating, the photo- resist film was allowed to rehydrate for one hour prior to exposure on a wafer stepper (Rudolph Technologies’ JetStep System).

Lithography

We used a customized test reticle that included a wide range of sizes and pitches to expose the wafer. When processing a thick photoresist, well-controlled sidewall angles are a critical requirement, especially when electroplating tall copper pillars. Most front-end tools have high numerical aperture (NA) lenses with low depth of focus (DOF) that prevent adequate exposure of thick films with sufficient image contrast to meet the sidewall angle and resolution requirements. Mask aligners also struggle with high aspect ratio imaging, not because of their NA, but because they are unable to provide the necessary focus offset required to expose the film at high resolution, ultimately limiting their aspect ratio and sidewall angle control. Although photoresist sidewall angles are primarily a function of the photoresist material and its processing (pre-bake, post-bake, developing, etc.), the exposure system plays an important role. Accurate focus control across the wafer or substrate is required to achieve consistent and accurate CD control with straight and perpendicular sidewalls.

The lithography stepper employed in this study refocuses for each exposure to ensure optimal focal plane height on advanced packaging substrates that are frequently warped by film stress and thermal cycling. The system’s 0.1 NA provides a large depth of focus to maintain image integrity and CD control through thick films. The stepper lens is achromatized and the installed “filter wheel” provides a choice of illumination wavelengths to expose the photoresist layers: “broadband” ghi (350-450nm), gh (390 to 450nm) or i-line (365nm). This study, with a photoresist thickness of 120μm, required high energy illumination of >1000 mJ/cm<sup>2</sup>, so broadband illumi- nation (g,h,i wavelengths) was employed to maintain high throughput.

The coated wafers were exposed using a focus exposure matrix wafer layout which provided a large number of programmed focus and exposure conditions at a fixed stepping distance to enable quick and efficient character- ization of the lithography process window for any pillar CD. After exposure, the wafers were developed for a total time of 180 secs, using 6 puddles in 2.38% TMAH. A number of wafers were processed in this way to provide images of the resist structures prior to the electroplating process. The SEM micrograph in FIGURE 2 shows a cross section of the photoresist via mold structures, the CD limit appears to be 25μm with this process, since the via is not open to the seed metal beyond this resolution.

lithography 2

It is interesting to note how the sidewall angle of the photoresist changes with decreasing CD suggesting that the plating will generate a “pedestal” type of copper pillar base at larger CDs, becoming progressively more vertical at smaller CDs. However, upon closer inspection of the smallest CDs, a slight “footing” can be observed at the base of the via (FIGURE 3), and this could result in slight undercut of the final copper pillar. The footing effect was most likely the result of our unoptimized develop process.

lithography 3

Electroplating

After the lithography processing, the wafers were sent to TEL NEXX for electroplating. The plating process employed the TEL NEXX Stratus P300 System, a fully automated electrochemical deposition system for advanced wafer-level packaging applications. The system deposits thick metal layers for wafer bumping, redistribution layers, TSVs, integrated passives, and MEMS.

In this study, we used a methanesulfonic acid copper chemistry with organic additives. The bath composition, operating temperature and current waveform were optimized for high speed copper plating into very thick resist features with flat bump profiles. After plating the photoresist was stripped using an immersion bath with EKC162 solution at 60 degrees. To preserve the profile of the photoresist mold the seed layer was not etched. The final copper pillar structures exhibit the inverse photo- resist mold profile (FIGURE 4).

lithography 4

The electroplating process successfully deposited copper in the photoresist via “molds” that were open to the copper seed material, producing good quality copper pillars with a final minimum copper pillar CD of 20μm, indicating a process bias of 5μm. This bias enabled the final copper pillar to reach a 6:1 aspect ratio as shown in FIGURE 5.

lithography 5

The final copper pillars exhibit excellent sidewall angle, 90 degrees for the smaller CDs. The profiles correlate well with the profiles observed in the photoresist SEM cross sections. The change in profile at the base of the photoresist for the smaller CDs did result in a slight undercut of the final copper pillar. The removal of this photoresist foot could be achieved by either increasing the de-scum time or modifying the develop recipe. The larger copper pillars tended to flare out slightly at the base (FIGURE 6) compensating for any undercut. This will benefit the structure during the removal of the copper seed layer.

lithography 6

The rheology of the copper pillar surface is very important for bonding reliability and the uniform plating of Sn solder, which was not performed during this particular study since it was not the primary objective. FIGURE 7 shows the flat top surface of a copper pillar which is free of voids and defects.

lithography 7

For advanced packaging applications, precise copper pillar height control is essential, and lithography CD control plays an important part in the plating process since CD variation directly affects plated height. The electroplating rate is proportional to current per unit area, i.e. the open area at the bottom of the photoresist openings at the beginning of the process, and the area of the evolving metal surface during deposition. Variation in CD or sidewall angle across the wafer will result in a corresponding change in copper pillar height. For example, in the case of copper pillar features a 5% change in CD can cause a 10% change in plated height.

Conclusion

The results of this study prove that it is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating. As advanced packaging requirements continue to evolve, the ability to create smaller copper pillar CDs at finer pitches in thick films will provide increased I/O density opportunities for SiP designers. Furthermore, it is clear that achieving high yield and reliability in the final package requires precise CD control throughout the entire photoresist profile to ensure consistent copper pillar height.

KEITH BEST is director applications engineering at Rudolph Technologies, Wilmington, MA. PHILLIP HOLMES is director of technology at TEL NEXX, Billerica, MA

IC Insights will release its new 2016 McClean Report late next month.  The 2016 McClean Report will include a ranking of the top-50 semiconductor suppliers’ for 2015 as well as the top-50 fabless semiconductor suppliers.  The forecasted “post-merger” top-10 2015 IDM and fabless semiconductor suppliers are covered in this research bulletin.

Unlike the relatively close annual market growth relationship between fabless semiconductor suppliers and foundries, fabless semiconductor company sales growth versus IDM (integrated device manufacturers) semiconductor supplier growth has typically been very different (Figure 1).  In 2010, for the first and only time on record thus far, IDM semiconductor sales growth (35%) outpaced fabless semiconductor company sales growth (29%).  Since very few fabless semiconductor suppliers participate in the memory market, the fabless suppliers did not receive much of a boost from the surging DRAM and NAND flash memory markets in 2010, which grew 75% and 44%, respectively.

As shown in Figure 2, only three of the top-10 IDM semiconductor suppliers are forecast to register growth in 2015 and, in total, the top-10 IDMs are expected to display flat growth this year.  Although flat growth by the top-10 IDMs would typically be considered poor performance, it is still forecast to be a much better result than is expected from the top-10 fabless semiconductor suppliers (Figure 3).  In order to make direct comparisons for year-over-year growth, IC Insights combined the merged, or soon to be merged, companies’ 2014 and 2015 semiconductor sales regardless of when the merger occurred.

As shown, the top-10 fabless semiconductor suppliers are forecast to register a 5% decline in sales this year, five points worse than the top-10 IDMs.  It should be noted that essentially all of the decline expected for the top-10 fabless suppliers in 2015 could be attributed to the forecasted decline in Qualcomm/CSR’s sales this year.  Much of the sharp decline in Qualcomm/CSR’s sales this year is being driven by Samsung’s increasing use of its internally developed Exynos application processor in its smartphones instead of the application processors it had previously sourced from Qualcomm.

Fig 1

Fig 1

Fig 2

Fig 2

Fig 3

Fig 3

Application processor sales to fabless/system house Apple from pure-play foundry TSMC are included in the fabless company sales ranking under the “Apple/TSMC” moniker.  Application processor sales supplied to Apple from IDM-foundry Samsung are included as part of Samsung’s logic IC sales.

As mentioned in the title of this Research Bulletin, 2015 could end up being only the second year ever, after 2010, in which the IDM semiconductor suppliers outpace the fabless semiconductor suppliers with regard to year-over-year growth.  Whether this actually takes place will be revealed from IC Insights’ extended compilation of the IDM and fabless semiconductor company rankings for the 2016 McClean Report.