Tag Archives: letter-wafer-top

We are in a historic era for consolidation among semiconductor manufacturers. Included in the announced mergers and acquisitions this year alone are:

Semiconductor Market Consolidation. (Slide from: Dr. Rutger Wijburg, Sr. Vice President and General Manager, GLOBALFOUNDRIES; keynote at Semicon Europa

Semiconductor Market Consolidation. (Slide from: Dr. Rutger Wijburg, Sr. Vice President and General Manager, GLOBALFOUNDRIES; keynote at Semicon Europa)

According to a recent article in the Wall Street Journal by Don Clark, the reasons for this market consolidation are relatively new to the industry: slowing growth and rising costs.

In the past, chip makers used acquisitions to obtain new technology. But, Clark writes that a different reason is becoming more prominent: “Many recent deals resemble consolidation waves in older industries, motivated mainly by trimming costs in areas like manufacturing, sales and engineering.”

For example, Avago projects that it can gain $750 million in annual savings starting in 2017 after it integrates Broadcom, according to Clark.

The article cites figures from Dealogic stating that the industry has seen $100.6 Billion in mergers and acquisitions in 2015 so far, compared to $37.7 Billion for all of 2014.

And that total is poised to go higher.

“Bloomberg reported last week that four chip companies — Analog Devices Inc., Maxim Integrated Products Inc., SanDisk Corp. and Fairchild Semiconductor International Inc. — were in talks concerning different deal options… ‘It’s buy or be sold,’ summed up Alex Lidow, chief executive of Efficient Power Conversion Corp., a startup he co-founded in 2007 after 30 years leading chip maker International Rectifier Corp,” Clark writes.

IEEE S3S 2015 could be the turning point for monolithic 3D. From October 4-7 we will have the option to get a short course, invited and selected presentations from a broad range of the industry representatives. They include major vendors such as Qualcomm, Global Foundries, and Applied Materials; leading research organization like CEA Leti, Taiwan National Applied Research Labs, German IMS Chips, and NASA; leading Universities like Berkeley and Stanford; and start-ups like SiGen and MonolithIC 3D.

In its tutorial session, Qualcomm will explain why it is investing in and promoting 3D VLSI (3DV) as an alternative scaling technology, as is illustrated by the following two slides:

GameChang2-0_Fig1GameChange2-0_Fig2

Yet many people still have doubts, as reflected by the title of the panel we were invited to participate in — “Monolithic 3D: Will it Happen and if so…” — at the IEEE 3D-Test Workshop on October 9, 2015.

The doubts likely relate to the technology challenge that is illustrated in the following slide:

GameChange2-0_Fig3

The question, in short, is how we can add more transistors monolithically interconnected to the underlying transistors without exceeding the thermal budget for the underlying transistors and interconnect.

The current paths to monolithic 3D involve major changes to the front line process flow and require the development of a new logic transistors. The big concern is that leading edge vendors are too busy with dimensional scaling and if anything else could be done it seems that FD-SOI would be it, while trailing edge fabs are, in most cases, avoiding any major transistor process development. The recent failure of Suvolta could be an indication of this reality.

Hence the importance of Game-Changing 2.0, a major technology innovation to be unveiled on Wednesday by MonolithIC 3D in a paper titled: “Modified ELTRAN (R) – A Game Changer for Monolithic 3D”. The paper will present a novel use of the ELTRAN process developed by Canon about 20 years ago, primarily for SOI applications. Using ELTRAN (Epi. Layer Transfer) techniques, a substrate could be prepared enabling any fab to simply integrate a monolithic 3D device without the need to change its current front-line fab process. This flow is further simplified and could be integrated with the monolithic 3D flow introduced last year that leverages the emerging precision bonders, such as EVG’s Gemini (R) XT FB. This flow provides a natural path for product innovation and an unparalleled competitive edge to its adopters. In addition, this game-changing breakthrough offers a very cost-competitive flow. The following chart illustrates the original use of ELTRAN process for the fabrication of SOI wafers:

GameChange2-0_Fig4

In the “Invited Talks on M3DI” at the conference we will have an opportunity to learn from the inventor of the ELTRAN process, Dr. Takao Yonehara, currently with Applied Materials, in his “Epitaxial Layer Transfer Technology and Application” talk. Prior to Applied Materials, Dr. Yonehara worked with Solexel, a Silicon Valley startup, to deploy the ELTRAN process for low cost solar cell fabrication. Yonehara’s talk will be followed by Prof. Joachin Burghartz of Institute for Microelectronics in Stuttgart, discussing “Ultra-thin Chips for Flexible Electronics and 3D ICs” that uses a variation of such flow in small scale production.

The semiconductor industry is bifurcating these days into a segment that follows aggressive scaling for few super-value applications supported by very few vendors, while the bulk of the industry is enhancing old fabs targeting mainstream applications and the emerging IoT opportunities. Further enhancing these older fabs with monolithic 3D offers a most effective return on investment. Game-Changing 2.0 means that without a need for major process R&D efforts or new equipment, the path for 3D scaling is now open with enormous advantages for IoT. Accordingly, my answer to the original question above is summarized by the title of our invited talk at the IEEE 3D-Test Workshop: “Monolithic 3D is Already Here — the 3D NAND — and Now it would be Easy to Adapt it for Logic.”

In addition the other division, SOI and SubVt provide good complementing technology updates for the power-performance objectives that are so important for these emerging markets.

So, come to the S3S and enjoy unique key technologies update with the great wine and country pleasures of Sonoma Valley.

ASML Holding NV (ASML) today announced the first shipment of its new TWINSCAN (TM) NXT:1980Di immersion lithography system to support increasingly demanding multiple-patterning performance requirements. Demonstrating 1.2 nanometer (nm) dedicated chuck overlay and better than 10 nm focus uniformity, the NXT:1980Di features new grid calibrations and hardware that enables chipmakers to achieve tighter process windows for next-generation process nodes. The NXT:1980Di also improves throughput by 10% to 275 wafers per hour.

ASML_Twinscan_NXT_1980Di_Left_Open_print_37731“Whether our customers face increased process complexity due to multiple patterning or plan to add Extreme Ultraviolet lithography, an improved level of immersion patterning is required in all leading-edge semiconductor manufacturing environments,” Bert Koek, Senior Vice President of DUV Product Marketing at ASML said. “The NXT:1980Di is a major leap forward in overlay, focus control and productivity, providing a cost-effective solution for chipmakers to further extend immersion lithography, and ultimately Moore’s Law.”

In future nodes, chipmakers are expected to use both immersion lithography and next-generation Extreme Ultraviolet (EUV) lithography, creating additional overlay requirements beyond the standard node-to-node improvements. The NXT:1980Di is specifically designed to accommodate the mix-and-match use with EUV, achieving about 2 nm matched-machine overlay.

The NXT:1980Di is currently available to customers. All TWINSCAN NXT:1970Ci systems can be upgraded in the field to the performance level of an NXT:1980Di. ASML also provides an upgrade path for previous TWINSCAN NXT models to further extend chipmakers’ capital investment. Additionally, as part of a rich portfolio of upgrade options, ASML offers add-on capabilities with the NXT:1980Di to address unique application needs, like a contrast enhancing alignment sensor to further improve overlay.

London, UK and San Jose, California – Dialog Semiconductor and Atmel Corporation announced today that Dialog has agreed to acquire Atmel in a cash and stock transaction for total consideration of approximately $4.6 billion. The acquisition creates a global leader in both Power Management (defined as power management solutions for mobile platforms including smartphones, tablets, portable PCs and wearable-type devices) and Embedded Processing solutions. The transaction results in a company that supports Mobile Power, IoT and Automotive customers. The combined company will address a market opportunity of approximately $20 billion by 2019.

Dialog will complement its position in Power Management ICs with a portfolio of proprietary and ARM (R) based Microcontrollers in addition to high performance ICs for Connectivity, Touch and Security. Dialog will also leverage Atmel’s established sales channels to diversify its customer base. Through realized synergies, the combination could deliver an improved operating model and enable new revenue growth opportunities.

“The rationale for the transaction we are proposing today is clear – and the potential this combination holds is exciting. By bringing together our technologies, world-class talent and broad distribution channels we will create a new, powerful force in the semiconductor space. Our new, enlarged company will be a diversified, high-growth market leader in Mobile Power, IoT and Automotive. We firmly believe that by combining Power Management, Microcontrollers, Connectivity and Security technologies, we will create a strong platform for innovation and growth in the large and attractive market segments we serve. This is an important and proud milestone in the evolution of our Dialog story,” said Jalal Bagherli, Dialog Chief Executive Officer.

“This transaction combines two successful companies and will create significant value for Atmel and Dialog shareholders, customers and employees. Adding Dialog’s world-class capabilities in Power Management with Atmel’s keen focus on Microcontrollers, Connectivity and Security will enable Dialog to more effectively target high-growth applications within the Mobile, IoT and Automotive markets,” said Steven Laub, Atmel President and Chief Executive Officer.

The transaction is expected to close in the first quarter of the 2016 calendar year. In 2017, the first full year following closing, the transaction is expected to be accretive to Dialog’s underlying earnings. Dialog anticipates achieving projected annual cost savings of $150 million within two years. The purchase price implies a total equity value for Atmel of approximately $4.6 billion and a total enterprise value of approximately $4.4 billion after deduction of Atmel’s net cash. Dialog expects to continue to have a strong cash flow generation profile and have the ability to substantially pay down the transaction debt approximately three years after closing.

The transaction has been unanimously approved by the boards of directors of both companies and is subject to regulatory approvals in various jurisdictions and customary closing conditions, as well as the approval of Dialog and Atmel shareholders. Jalal Bagherli will continue to be the Chief Executive Officer and Executive Board Director of Dialog. Two members of Atmel’s existing Board will join Dialog’s Board following closing. The transaction is not subject to a financing condition.

Process Watch: Risky business


September 18, 2015

By Douglas G. Sutherland and David W. Price

Authors’ Note: This is the ninth in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications. Within this paper we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

Previous installments have discussed many aspects of process control from general concepts to specific issues related to risk management (see below for links to previous Process Watch articles). In this article we will focus on strategies for managing risk associated with the most difficult steps in the process.

The ninth fundamental truth of process control for the semiconductor IC industry is:

High-Stakes Problems Require a Layered Process Control Strategy

In the IC manufacturing process there are a bewildering number of things that can go wrong and there is a tremendous amount of money at risk. As the margins of error steadily decrease with each new design node, the number of parameters that can wreak havoc on the process continues to rise. The increasing complexity of multiple patterning, pitch splitting and other advanced patterning techniques does nothing to mitigate this problem.

This increased process complexity drives the need for new process control strategies. For example, higher order overlay corrections that were largely unheard of above 45nm are now considered mandatory at 2Xnm and below. Similarly, wafer topography, something that historically was only measured during the manufacture of bare wafers, is now becoming a requirement in IC fabs to accommodate the shallower depth of focus in today’s scanners. For the same reasons, wafer backside and edge inspection are also becoming common practices. The difficulty of some process steps necessitates that they have more than just a single line of defense.

Figure 1 below shows the severity of a potential problem increasing in the horizontal direction and the probability of that problem actually occurring increasing in the vertical direction. In this figure the term “risk” can be thought of as the product of these two attributes – the amount of material impacted (severity) multiplied by the probability of it happening. The severity could increase for a number of reasons: the next inspection point could be many steps downstream from the current step, the process tools at the current step may have very high throughput so that by the time the problem is identified many lots have been exposed to it, or both.

Figure 1. Risk exposure chart with higher severity to the right and higher probability to the top. The problems that require a layered approach to risk management are those in the upper right hand corner where the probability of having a problem is high and the amount of material exposed to that problem is large.

Figure 1. Risk exposure chart with higher severity to the right and higher probability to the top. The problems that require a layered approach to risk management are those in the upper right hand corner where the probability of having a problem is high and the amount of material exposed to that problem is large.

Clearly the safest place to operate is in the lower left corner where both probability and severity are low. However, for process steps that are inherently closer to the upper right hand corner of the chart—high probability and high severity—it often makes sense to have a layered approach to process control in which there is a well thought out back-up plan if the problem is not immediately identified with the first inspection step. Sometimes there are aspects of the problem that are easier to detect later in the process than immediately after the problem step.

Consider the case of forming the first metal layer that wires together the individual transistors. This can be particularly difficult for a number of reasons. The CDs and pitches are aggressive—often at design rules similar to the gate layer. Also, the opportunity for built-in redundancy (multiple vias) is low because there is only one point of contact for each of the transistor connections (source, drain and gate), so every connection has to work.

In such a case it makes sense to have multiple layers of protection, each of which has unique capabilities. For instance, you might perform macro inspection after the photo step to discover any gross defects in the lithography process. There should also be inspection steps after oxide etch, barrier deposition and copper CMP. Having multiple inspection steps ensures the quality of the process throughout the formation of this layer and also helps ensure that you catch problems that originate at one step but may not become apparent until later in the process.

Simply waiting to do a final inspection at copper CMP is usually not sufficient. Doing so will pick up problems in the CMP process but may not allow for distinguishing these from issues that may have originated at an earlier step. Only by inspecting the same wafer at multiple steps are you able to subtract out previous-layer defects and isolate the problem.

Having multiple inspection points has several benefits. It helps identify problems early in the process flow, which significantly reduces the amount of material exposed. A device with 50,000 wafer starts per month has about 1,600 wafer starts per day. Identifying a problem one day sooner can save millions of dollars (depending on the yield loss and wafer cost). Multiple inspection points also help diagnose where the problem occurred and expedite the recovery procedure. Over time, they provide more information about the process allowing for continuous improvement plans that can help reduce not only the severity but also the frequency of problems.

Previous Process Watches:

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

By Zvi Or-Bach, Contributor

The upcoming IEEE S3S Conference 2015 in Sonoma, CA, on October 5-8, will focus on key technologies for the IoT era. It is now accepted that the needs for the emerging IoT market are different from those that drive the high-volume PC and smart-phone market. The Gartner slide below illustrates this industry bifurcation where traditional mass products follow the ever more expensive scaling curve, while IoT devices, with their focus on cost, power, flexibility and accessibility, will seek a place near its minimum.

S3S_Gartner

The current high-volume market is focused on a few foundries and SoC vendors driving a handful of designs at extremely high development cost each, processed at the most advanced nodes, with minimal processing options. In contrast, the emerging IoT market is looking for older nodes with lower development costs and a broad range of process options, and has many more players both at the foundry side and the design side.

The key enabling technologies for the IoT market are extremely low power as enabled by SOI and sub-threshold design, integrated with multiple sensor and communication technologies that are both enabled by 3D integration. All of these combine in forming the IEEE S3S unified conference.

This year’s conference includes many exciting papers and invited talks. It starts with three plenary talks:

  • Gary Patton – CTO of Global Foundries: New Game Changing Product Applications Enabled by SOI
  • Geoffrey Yeap – VP at Qualcomm.: The Past and Future of Extreme Low Power (xLP) SoC Transistor, embedded memory and backend technology
  • Tsu-Jae King Liu – Chair of EE Division, Berkeley University: Sustaining the Silicon Revolution: From 3-D Transistors to 3-D Integration

The following forecast from BI Intelligence suggest that the semiconductor technologies that are a good fit for the future market of IoT should be of prime interest for the semiconductors professional.

S3S_BI

Jim Walker, Research VP at Gartner, argued at the “Foundry vs. SATS: The Battle for 3D Wafer Level Supremacy” market symposium that 3D ICs are the key enabler of performance and small form factor of products required for IoT.

The upcoming IEEE S3S conference provides an important opportunity to catch up and learn about these technologies.

Let me share with you some nuggets from the monolithic 3D integration part of the conference:

Prof. Joachin Burghartz of the Institute for Microelectronics Stuttgart will deliver an invited talk on “Ultra‐thin Chips for Flexible Electronics and 3D ICs” which will present a process technology to fabricate flexible devices 6-20 microns thin. This process flow is currently in manufacturing in their Stuttgart fab, as depicted below:

S3S_Fig3

Another interesting discussion will be presented by NASA scientist Dr. Jin-Woo Han who will describe “Vacuum as New Element of Transistor”. These transistors are made of “nothing” and could be constructed within the metal stack, forming monolithic 3D integration with silicon-based fabric underneath.

In his invited talk “Emerging 3DVLSI: Opportunities and Challenges” Dr. Yang Du will share  Qualcomm’s views on monolithic 3D IC, which they term 3DVLSI and illustrate below, which seems very fitting for IoT applications.

S3S_Fig2

Globalfoundries will present joint work with Georgia Tech on “Power, Performance, and Cost Comparisons of Monolithic 3D ICs and TSV-based 3D ICs”. This work again shows that monolithic 3D can provide a compelling alternative to dimensional scaling as illustrated by the following chart.

S3S_Fig4

Monolithic 3D will present “Modified ELTRAN (R) – A Game Changer for Monolithic 3D” that shows a practical flow for existing fabs to process monolithic 3D devices using their exiting transistor process and equipment. This flow leverages the work done by Canon about 20 years back called ELTRAN, for Epitaxial Layer Transfer. The following slide illustrates the original ELTRAN flow.

S3S_Final

By deploying the elements of this proven process, a multilayer device could be built first by processing a multilayer transistors fabric at the front end of line, and then process the metal stacks from both top and bottom sides.

The conference includes many more interesting invited talks and papers covering the full spectrum of IoT enabling technologies. In addition, the conference offers short courses on SOI application and monolithic 3D integration, and a fundamental class on low voltage logic.

New technologies are an important part of the future of semiconductor industry, and a conference like the S3S would be a golden opportunity to step away for a moment from the silicon valley, and learn about non-silicon and silicon options that promise to shape the future.

Soitec (Euronext), which generates and manufactures semiconductor materials for the electronics and energy industries, and Shanghai Simgui Technology Co., Ltd. (Simgui), a Chinese silicon-based semiconductor materials company, jointly announced today that the first 200-mm silicon-on-insulator (SOI) wafers have been produced at Simgui’s manufacturing facility in Shanghai using Soitec’s proprietary Smart Cut (TM) technology, and will be shipped within the next weeks for customers’ qualification. This major milestone in the companies’ licensing and technology transfer agreement, signed in May 2014, demonstrates that the process has been successfully implemented at Simgui and that the technology transfer is proceeding as planned to produce Soitec’s SOI products in order to increase SOI wafer capacity to serve the growing RF and power markets.

“We are very pleased to have reached this major milestone with Simgui, which now has the capability to manufacture Soitec’s SOI products using our Smart Cut technology. This represents a key step in our commitment to increase capacity in response to the needs of our customers who serve the fast-growing RF and power markets, both in China and worldwide,” said Paul Boudre, CEO and chairman of the board of Soitec.

“China is a hot spot for the IC industry today. The fast growth of China’s mobile devices demands a large number of SOI wafers. Through the collaboration with Soitec, Simgui has successfully demonstrated a strong technical ability and expanded capacity to meet our customers’ needs. In addition to the planned high-volume manufacturing of SOI wafers, we will continue to promote the SOI ecosystem in China and build a globally influential Chinese silicon industry,” said Dr. Xi Wang, chairman of the board of directors of Simgui.

The two companies formed their international partnership last year to address both China’s growing demand and to increase worldwide production capacity for 200-mm SOI wafers used in fabricating semiconductors for RF and power applications. When completed, the partners’ first wafer production line in China will boost the industrial manufacturing capacity of SOI wafers to meet increasing worldwide usage and will also be a key element in establishing an SOI ecosystem in China.

Simgui is a high-technology company in Shanghai focused on supplying SOI wafers and providing foundry services for epitaxial (epi) wafers used in key sectors of the semiconductor industry. Soitec designs and manufactures high-performance semiconductor materials.

Marking an industry first for emerging electronics devices, Semiconductor Research Corporation (SRC) today announced a significant expansion of its benchmarking research — a unique program that evaluates the relative capabilities of new and emerging computing devices.

SRC, the world’s leading university-research consortium for semiconductor technologies, is managing the initiative through its Nanoelectronics Research Initiative (SRC-NRI) and STARnet Research programs. The research will be led by the Georgia Institute of Technology’s Azad Naeemi, associate professor, Georgia Tech School of Electrical and Computer Engineering.

“Benchmarking guides university research funded through SRC — enabling concise communication of research outcomes, focusing researchers’ attention on key technical challenges and sparking invention,” said Tom Theis, executive director of SRC-NRI. “Professor Naeemi’s research is expected to take benchmarking of emerging devices to a new level of sophistication.”

Evaluating the performance of devices in representative “benchmark” circuits is a well-established engineering practice in the semiconductor industry. However, this new program is the first to develop a comparable methodology for evaluating the relative capabilities of emerging devices.

These emerging devices include, for example, transistor-like “steep slope” devices that can operate at very low voltage and, therefore, very low power, and non-volatile magnetic devices that combine the functions of logic and memory. The new devices operate by a variety of principles fundamentally different from those governing the operation of established silicon field-effect transistor technology.

In recent years, benchmarking of these devices has steadily increased in rigor. The Georgia Tech team — selected by a group of SRC member companies supporting the initiative including IBM, Intel Corporation, Micron Technology and Texas Instruments — will build on this foundation.

“This research will also enable selection of the most promising emerging devices for technology transfer to SRC member companies and for continued development in future SRC research programs,” said Gilroy Vandentop, executive director of STARnet Research.

Besides maintaining and improving the established benchmarking methodology, the Georgia Tech team is tasked with developing and evaluating benchmark circuits to better understand the potential of new devices for memory arrays, to explore and quantify the value of non-volatility and to measure the impact of various ways of implementing device-to-device connections. Perhaps most challenging, Prof. Naeemi will lead the development of a rigorous benchmarking methodology for non-Boolean (analog) computational circuits being explored for future applications such as artificial neural networks.

“Our team is chartered with maintaining and improving the established benchmarking methodology for emerging devices, evaluating the potential performance of the various SRC-NRI and STARnet devices in the established benchmark circuits,” said Naeemi. “We will incorporate additional device concepts as they emerge through ongoing research, and we will develop additional benchmark circuits to better understand the capabilities of these devices.”

The SRC benchmark program is a two-and-a-half year effort that funds research from July 1, 2015 through the close of 2017.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors were $27.9 billion for the month of July 2015, a decrease of 0.9 percent from July 2014 when sales were $28.1 billion. Global sales from July 2015 were 0.4 percent lower than the June 2015 total of $28.0 billion. Regionally, sales in the Americas were roughly flat in July compared to last year, while sales in China increased by nearly 6 percent. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales have slowed somewhat this summer in part due to softening demand, normal market cyclicality, and currency devaluation in some regional markets,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Despite these headwinds, year-to-date global sales through July are higher than at the same time last year, which was a record year for semiconductor revenues.”

Regionally, year-to-year sales increased in China (5.6 percent), Asia Pacific/All Other (1.0 percent), and the Americas (0.8 percent), but decreased in Europe (-12.5 percent) and Japan (-13.3 percent), in part due to currency devaluation. On a month-to-month basis, sales increased in Japan (2.7 percent), China (0.6 percent), and Europe (0.4 percent), but fell slightly in the Americas (-0.3 percent) and Asia Pacific/All Other (-2.5 percent).

“One key facilitator of continued strength in the U.S. semiconductor industry is research, the lifeblood of innovation,” Neuffer said. “SIA and Semiconductor Research Corporation this week released a report highlighting the urgent need for research investments to advance the burgeoning Internet of Things and develop other cutting-edge, semiconductor-driven innovations. Implementing the recommendations in the report will help the United States harness new technologies and remain the world’s top innovator.”

July 2015

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.53

5.52

-0.3%

Europe

2.83

2.84

0.4%

Japan

2.57

2.64

2.7%

China

8.13

8.18

0.6%

Asia Pacific/All Other

8.94

8.71

-2.5%

Total

27.99

27.88

-0.4%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.47

5.52

0.8%

Europe

3.24

2.84

-12.5%

Japan

3.04

2.64

-13.3%

China

7.75

8.18

5.6%

Asia Pacific/All Other

8.63

8.71

1.0%

Total

28.13

27.88

-0.9%

Three-Month-Moving Average Sales

Market

Feb/Mar/Apr

May/Jun/Jul

% Change

Americas

5.61

5.52

-1.7%

Europe

2.89

2.84

-1.8%

Japan

2.54

2.64

3.8%

China

7.77

8.18

5.2%

Asia Pacific/All Other

8.74

8.71

-0.3%

Total

27.56

27.88

1.2%

Related news: 

Tech, academic leaders call for robust research investments to bolster U.S. tech leadership, advance IoT

bill holt

William M. Holt, executive vice president and general manager of the Technology and Manufacturing Group (TMG) at Intel.

The Semiconductor Industry Association (SIA) today announced William M. Holt, executive vice president and general manager of the Technology and Manufacturing Group (TMG) at Intel, has been named the 2015 recipient of SIA’s highest honor, the Robert N. Noyce Award. SIA presents the Noyce Award annually in recognition of a leader who has made outstanding contributions to the U.S. semiconductor industry in technology or public policy. Holt will accept the award at SIA’s Annual Award Dinner on Thursday, Dec. 3.

“For the last four decades, Bill Holt has been a tireless advocate, innovator, and leader for the semiconductor industry, helping advance new technologies that drive our industry and power our economy,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Throughout his distinguished career, Bill’s expertise, skill, and unwavering determination have helped keep the semiconductor industry at the forefront of innovation. On behalf of the SIA board of directors, it is an honor to announce Bill’s selection as the 2015 Robert N. Noyce Award recipient in recognition of his tremendous accomplishments.”

Holt began his Intel career in DRAM development in 1974. Today, he is responsible for technology development and the company’s worldwide manufacturing operations, including component fabrication, assembly and test, customer fulfillment, and supply chain management. Additionally, Holt oversees research and development in the areas of wafer process, package assembly and test, and design and technology computer-aided tools. Holt earned a bachelor’s degree in electrical engineering from the University of Illinoisand a master’s in electrical engineering from the University of Santa Clara.

“It is a tremendous honor to join the ranks of Noyce Award winners, individuals who have built the semiconductor industry and made it a paragon of America’s economic and technological strength,” said Holt. “Throughout my career, I have focused on doing my part to advance the forward march of innovation, one step at a time. As I gratefully accept this award, I look forward to continuing to help our industry take the next step forward.”

The Noyce Award is named in honor of semiconductor industry pioneer Robert N. Noyce, co-founder of Fairchild Semiconductor and Intel. In addition to the presentation of the Noyce Award, this year’s SIA Award Dinner will feature former Defense Secretary Leon Panetta as keynote speaker.