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A new range of dissipative materials based on fluoroelastomer and perfluoroelastomer polymers is designed for wafer processing and wafer handling applications. 

By KNUT BEEKMANN, Precision Polymer Engineering, Blackburn, Lancashire, U.K. 

All industries are now focusing on creating increasingly innovative products at a greatly reduced cost, providing customers with new cost efficient solutions. As new technologies are being produced, there is a need for an improved supply chain, providing new materials, improving wafer throughputs and lowering defects – all resulting in reduced costs for manufacturers.

When dealing specifically with the electronics industry, there is a particular focus for all major manufacturers on electrostatic charge reduction and elimination of electrostatic discharge (ESD). Electro- static discharge is something we all experience on a regular basis – when walking across a carpeted floor and then touching a door handle, for example, or during a lightning storm. Although in everyday situations it is unlikely that any real lasting damage will be sustained, it is possible for electronic devices to be damaged by ESD events that are imperceptible to the human body. Even relatively low electrostatic voltages can have a huge impact on sensitive electrical devices, impacting yield, quality and reliability. It is suspected that ESD events occur hundreds of times a day. Although these are often not seen, they can have a significant impact on electrical equipment, resulting in a huge cost to manufacturers. In fact, it has been estimated that the cost of static associated damage ranges up to 33% for the electronic industry and between an average of 16 to 22% for component manufacturers [1] – a number which all would like to see dramatically reduced.

The principle of ESD

The initial creation of electrostatic charge requires energy to be transferred to a material which can occur when two materials repeatedly come into contact and separate. This is referred to as triboelectric charging. During this process a chemical bond is formed between the two surfaces as they come into contact, allowing charges to move from one material to the other to equalize their electrochemical potential. This creates a net charge imbalance between the objects. When separated, some of the bonded atoms keep extra electrons, while others give them away, though the imbalance will be partially destroyed by tunnelling or electrical breakdown (usually corona discharge). In addition, some materials may exchange ions of differing mobility, or exchange charged fragments of larger molecules.

When objects at different electrostatic potentials are brought together, the result is a rapid transfer of charge between the objects – the spark or ‘shock’ we commonly recognise as static electricity.

The triboelectric effect is not very predictable, and only broad generalizations can be made. However, materials such as glass or silica, plastics and elastomers, all of which are a fundamental requirement of semiconductor device manufacturing, either as a handling material or as part of the device, can each be a source of electrostatic charge. Once a material has become charged, the electrostatic field can also induce a charge distribution in nearby ungrounded conducting materials.

The level and sign of charge will mostly depend on the types of material, as summarized in TABLE 1.

TABLE 1. Example materials in the triboelectric series.

TABLE 1. Example materials in the triboelectric series.

The impact of electrostatic charging

ESD has been an issue across multiple industries for as long as manufacturing has been taking place. Military forts in the 1400s were using static control procedures and devices trying to prevent inadvertent electrostatic discharge ignition of gunpowder stores. By the 1860s, paper mills throughout the U.S. employed basic grounding, flame ionization techniques, and steam drums to dissipate static electricity from the paper web as it travelled through the drying process [2].

As electronic device technology has progressed, we have seen reduced voltage tolerances and lower capacity for heat dissipation. The age of electronics brought with it new problems allied to electro- static discharge. Today, ESD impacts productivity and product reliability in virtually every aspect of the global electronics environment and emphasis on minimizing electrostatic charging and ESD has become hugely important [2].

When flowing through an integrated circuit, electrostatically induced charge can generate sufficient heat to break down the gate structure, cause spiking in contacts, junction breakdown and burn the interconnects. ESD events can also create a weakness that can lead to reliability issues or premature failure [3]. Damage from ESD on semiconductor devices can be immediate and catastrophic and can be blamed for millions of dollars of product failures a year.

ESD events may also interfere with the control electronics of the process tool. ESD creates electro- magnetic energy transmitted in the form of waves in the radio frequency range, leading to electromagnetic interference (EMI) [4]. Finally, electrostatic charging of materials can also lead to attraction and subsequent adhesion of particles from the ambient or from within the process tools. Electrostatic attraction will not distin- guish between material types and create potential yield reducing damage, as both insulating and ungrounded conducting matter can be equally influenced.

The failures can all have a dramatic impact on manufacturers, especially when we consider the
cost of repairing equipment that has been exposed to ESD – especially if such failures happen once the component has been installed into a system. While a simple piece of electronic technology may cost only $10 to replace and retest on its own, when it fails in the field it could mean a cost of hundreds or thousands of dollars. Recent approximations propose that the cost of repairing an ESD-damaged product increases tenfold at every level between individual component to system [1].

Semiconductor manufacturing

Modern semiconductor production plants have become significantly more automated, especially as wafer sizes have increased to 300mm. Wafers can undergo more than 1000 process steps and multiple robotic wafer handling cycles per process step, providing opportunities for static charges to accumulate and discharge. To a large extent, therefore, static build up is inevitable. In order to counteract this risk, system manufacturers have a responsibility to monitor the environment and use appropriate materials and equipment, as well as ensuring grounding and controlled leakage paths in order to control ESD.

Plastics and elastomers are commonly used to contact or support substrates through production lines. They serve their main purpose in several ways; substrates do not slide as they move and they should potentially be able to withstand raised temperatures without creating adhesion issues. However, these contact materials are primarily insulators. Whenever a substrate is in contact with a handling device and subsequently separates, triboelectric charging will take place. This increases the likelihood of a subsequent ESD event or induced charging of materials.

Rather than using insulators to contact the substrates, these materials should be electrostatically dissipative and have a low resistance path to ground. To ensure this, electrostatically dissipative materials need to have a volume or surface resistance between that of insulating and conducting materials at between 1×104 and 1×1011 ohms [2].

In addition to the properties previously mentioned, materials need to be compatible with semiconductor devices and not contribute to already sensitive levels of contamination. Elasto-meric materials such as ethylene-propylene polymers (EPD/EPDM) can be obtained in dissipative variants; however these invariably contain metallic elements. Dissipative elastomer materials for semiconductor processing or handling should have controlled constituents and avoid common metallic filler.

Dissipative elastomers

Particular properties of fluoroelastomers and perfluoroelastomers, such as chemical resistance, higher temperature compatibility and low levels of contaminants, make them particularly suitable for semiconductor applications. Finding materials with additional electrostatic dissipative properties, however, often proves a challenge.

FIGURE 1. EDX spectra of electrostatically dissipative perfluoroelastomer.

FIGURE 1. EDX spectra of electrostatically dissipative perfluoroelastomer.

FIGURE 2. EDX spectra of electrostatically dissipative fluoroelastomer.

FIGURE 2. EDX spectra of electrostatically dissipative fluoroelastomer.

To meet this need, a completely new range of dissipative materials based on fluoroelastomer and perfluoroelastomer polymers has been specifically designed for wafer processing and wafer handling applications. FIGURES 1 and 2 show an energy dispersive X-ray spectroscopy (EDX) analysis carried out on both polymer types and demonstrates a complete absence of metallic based filler and an entirely organic composition. This is summarized in TABLE 2. Despite avoiding the use of metallic based additives, volume resistance values can be obtained that are well within the dissipative range (FIGURES 3 and 4).

TABLE 2. EDX compositional analysis in weight.

TABLE 2. EDX compositional analysis in weight.

FIGURE 3. Perfluoroelastomer volume resistance.

FIGURE 3. Perfluoroelastomer volume resistance.

FIGURE 4. Fluoroelastomer volume resistance.

FIGURE 4. Fluoroelastomer volume resistance.

Conclusion

Technological progress within the semiconductor industry brings with it greater yield sensitivity, along with a common desire to reduce costs. These two factors are also related to defects and hence, how well those defects are controlled throughout an increasingly automated manufacturing process. An important part of reducing defects, both during and after production, includes management of electro-static charging in order to avoid damage from ESD events. Greater use of dissipative materials is an obvious way of minimising charge build-up and reducing ESD events.

However, it is also essential to ensure these materials are compatible with the process environment and the devices themselves. With the correct material and precautions in place, it is possible to avoid damage from static charge, particle contamination through electrostatic attraction and process tool interference through EMI.

References

1. “Guidelines for Static Control Management,” Steven Halperin Eurostat 1990.
2. “Fundamentals of Electrostatic Discharge,” ESD Association
3. “Understanding ESD and EOS Failures in Semiconductor Devices,” S. Agarwal, Cypress Semiconductor, Electronic Design Feb 2014
4. “Preventing Electrostatic Problems in Semiconductor Manufacturing,” A.J. Steinman Compliance Engineering, 2004 Annual reference guide
5. “ESD Protection While Handling LEDs,” C. Lee, D. Ying, C. Wittmann, A. Stich, Osram Application note, December 2013.

KNUT BEEKMANN is the Marketing Manager for Semiconductors, Precision Polymer Engineering, Blackburn, Lancashire, U.K.

The most expensive defect


December 18, 2014

Defects that aren’t detected inline cost fabs the most. 

By DAVID W. PRICE and DOUGLAS G. SUTHERLAND, KLA-Tencor, Milpitas, CA

Defect inspection tools can be expensive. But regardless of the cost of the inspection tool needed to find a defect, the fab is almost always better off financially if it can find and fix that defect inline versus at the end of line (e.g., electrical test and failure analysis). Here, we are referring to the term defect in a general sense—the same concepts also apply to metrology measurements.

The third fundamental truth of process control for the semiconductor IC industry is:

The most expensive defect is the one that wasn’t detected inline.

FIGURE 1A (top) shows an imaginary SPC chart for a factory experiencing a baseline shift in defectivity (an excursion) beginning at Lot #300. FIGURE 1B (bottom) shows the same scenario except the fab has an effective inline monitor at the point of the excursion. In this case, the excursion is quickly identified and the offending process tool is taken offline for process tuning or maintenance. The excursion is contained and relatively few lots are impacted by the resulting yield loss.

Defects 1a

FIGURE 1. It is always better to find and fix problems inline versus at the end of line. 1a. Problem identification and correction does not occur until bad wafers reach end-of-line test. 1b. Problem identification and correction occurs immediately.

FIGURE 1. It is always better to find and fix problems inline versus at the end of line. 1a. Problem identification and correction does not occur until bad wafers reach end-of-line test. 1b. Problem identification and correction occurs immediately.

The difference between these two scenarios is that in the top chart, the fab is unable to detect the excursion inline so the baseline shift continues unabated until the first affected lots hit end of line test. For a foundry process with a 60-day cycle time, this delay could easily exceed 20 days.

In our experience working with IC manufacturers, the majority of financial impact does not come from large excursions that cause significant yield loss to every affected wafer—those problems are usually identified and rectified very early on. Rather, the largest losses usually come from small excursions that are difficult to detect. They cause relatively low levels of yield loss but persist for prolonged periods of time. It is not uncommon to see thousands or even tens of thousands of wafers exposed to these low level excursions.

The culprit is nearly always a process control capability issue that can be traced back to one or more possible problems. The following list is not meant to be exhaustive, but is instead, representative of the most common causes:

Defects 2

FIGURE 2. Cost vs. mean time to detection (MTTD) of finding a defect inline. The curves are drawn for 4 different wafer costs in a fab with 100k WSPM. It is assumed that the excursion takes place at a single step in the process and happens once per year to each of the process tools at that step. The yield loss is assumed to be 20% during the excursion.

  • Insufficient number of inspection points to allow effective isolation of the defect source.
  • Failing to use a sensitive enough inspection tool or recipe (pixel size is too large, wrong wavelength,
  • etc.)
  • Inspection area of wafer is too low.
  • Review sample size is too small.

Often, the original inspection strategy was carefully designed, but as time passed, changes were made to reduce costs. As new sources of noise are introduced in the SPC chart, the fab becomes less sensitive to small excursions.

FIGURE 2 shows the economic impact to the fab for the two scenarios shown by the SPC chart in FIGURE 1. Imagine an excursion which results in a net 25 percent yield loss (e.g., one out of four wafers must be scrapped). Finding that excursion at end-of-line (+30 days) versus inline (greater than one day) would amount to a staggering $21 million loss per occurrence for an average size run rate of 25k wafer starts per month. Given that this value only repre- sents the cost of re-manufacturing the scrapped wafers it could actually be a conservative estimate. The true cost could easily be double that amount for a fab that is running at the limit of their capacity since it would directly impact revenue.

Even if the situation requires the use of a relatively expensive inspection tool to find, monitor and resolve the problem, it is nearly always in the factory’s best interest to do so. One of the implications of this truth is that if an important defect type can only be detected by a certain inspection tool, then that inspection tool is almost always the most cost-effective solution for that layer. Rather than modifying process control strategies to save costs, it is nearly always in the factory’s best interest to maintain capable, inline process control strategies that prevent the financial impact of ‘the most expensive defect.’

Author’s Note: This is the third in a series of 10 installments that explore fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights their implications.

Read more Process Watch:

Process Watch: Fab managers don’t like surprises

Process Watch: The 10 fundamental truths of process control for the semiconductor IC industry

Process Watch: Exploring the dark side

“The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

 

Cross section sample preparation is demonstrated using a workflow that combines High Accuracy Cleaving I(HAC) and Broad Ion Beam (BIB) milling.

By TESHIMA, LatticeGear, Beaverton, OR and JAMIL J. CLARKE, Hitachi High Technologies America, Inc., Clarksburg, MD 

In order to develop and manufacture new materials and processes, the cross section is essential (FIGURE 1). Cross sections allow one to visualize, measure, and characterize the chemistry of the film stack or device structures. This allows engineers to verify the integrity of devices and to make critical decisions about the process. To be able to provide this data, manufacturers and equipment suppliers invest close to a billion dollars annually [1] to purchase equipment for off-line use and out- of-fab support labs.

FIGURE 1. Cross section of a fully processed microprocessor prepared by high accuracy cleaving and flat milling

FIGURE 1. Cross section of a fully processed microprocessor prepared by high accuracy cleaving and flat milling

Because such labs are not considered a “make wafer” function, lab managers are under constant pressure to reduce costs, both per sample and for lab operations. This paper demonstrates cross section sample preparation using a workflow that combines High Accuracy Cleaving (HAC) and Broad Ion Beam (BIB) milling. Coupling these techniques, which are relatively low in cost when compared to Focused Ion Beam (FIB) or automated polishing or cleaving [2], reduces sample preparation time, complexity, and cost without sacrificing cross-section quality. The LatticeAxTM HAC and the Hitachi IM4000 BIB milling tools were used to demonstrate this process and are also described.

Preparing cross sections for SEM analysis

Characterization of semiconductor structures and material properties commonly begins with sample preparation. Semiconductor samples are inspected either as a cross section or “top down.” Cross-section samples are needed to inspect layers of subsurface features. As shown in FIGURE 2, if a cross-section view is required and the original sample is a wafer or a die, cleaving is typically the first step in the sample preparation procedure.

FIGURE 2. Wafers and wafer pieces enter a cross- section workflow that starts with cleaving and then follows a single- or multi-tool sample preparation process.

FIGURE 2. Wafers and wafer pieces enter a cross- section workflow that starts with cleaving and then follows a single- or multi-tool sample preparation process.

In many cases, the sample can proceed directly to the Scanning Electron Microscope (SEM) as shown in the Single-Tool workflow. For fully processed devices and those with large metal structures, improving surface quality with another method enhances the results (see Multi-Tool workflow).

Advanced techniques used in the multi-tool workflow, such as FIB and automated polishing, have benefits in terms of submicron—or in the case of FIB, nanometer—targeting accuracy, but the tradeoff is high cost, long cycle time, and the need for skilled operators.

Methods

The following sections describe the techniques used to perform multi-tool, cross-section sample prepa- ration workflow using HAC and BIB milling.

High Accuracy Cleaving An accurate and high quality cleave is critical to preparing a cross section for SEM imaging regardless of whether it follows the single- or multi-tool workflow. Manual cleaving, in which you scribe a line and then break the sample along the fracture over a raised edge or pin, has inherent problems with accuracy and repeatability. In addition, because the user handles the sample with fingers that are often gloved, great skill is required to achieve good results. FIGURE 3a shows traditional scribing hand tools used in manual cleaving. Cleaving results using these tools are obviously dependent on the hand-eye coordination of the operator.

FIGURE 3a. Hand tools commonly used for cleaving semiconductor materials

FIGURE 3a. Hand tools commonly used for cleaving semiconductor materials

Figure 3b

Figure 3b

The LatticeAx process overcomes these disadvantages by controlling the indent location and depth, as well as the cleaving operation, with fine-positioning knobs on the LatticeAx high magnification digital microscope. This new machine-assisted Indent and Cleave[3] approach bridges both manual scribing and fully automated cleaving or polishing, and increases success rates while keeping costs down.

The accurate, repeatable indent and slow, controlled cleaving that results from this hybrid tool (FIGURE 3b) speeds preparation time and produces high accuracy, quality results—regardless of user experience—and with greater flexibility of sample size and dimensions.

Broad Ion Beam Milling The BIB milling system is a specimen preparation device (FIGURE 3c) for SEM and surface analysis (EDX[4], EBSP[5], etc.). The device uses a defocused beam of argon ions that sputter material from the target specimen at a rate up to 2-500μm/hour, depending on the mode used. The BIB milling system uses a simple, repeatable process to remove surface layers of a specimen and for final finish of specimens in cross section. It is advantageous compared to mechanical polishing methods, which require well-trained operators to polish the specimen to a flat and mirror-like surface and hit a specific target. In addition, complex material composites that contain materials varying in hardness pose challenges when mechanically prepared using polishing wheels and compounds. This mechanical approach can lead to cracks, stress, relief (pull-out effects), and smearing. These adverse effects are minimized when using the low voltage (0-6kV) argon beam to remove material.

FIGURE 3c. Hitachi IM4000Plus broad ion beam milling system

FIGURE 3c. Hitachi IM4000Plus broad ion beam milling system

Flat Milling Mode Using the BIB’s “Flat Milling” mode yields a high quality cross section in a short amount of time. It requires the initial high accuracy cleave to be through or within a few 100nms of the area of interest and the face of the cross section to be at 90 degrees to the sample surface. With a high quality cleave, the BIB’s Flat Milling mode quickly polishes the cross-section face. Material is removed at a rate of 2μm/hr. Using the flat milling holder, the milling process can uniformly sputter an area approximately ~5mm across around the center of rotation of the specimen (FIGURE 3d). Typical operating parameters for the Hitachi IM4000Plus are 3kV accelerating voltage and a tilt of 70 degrees, with sample stage oscillation set to ±90 degrees and 10rpm. The best quality surface is achieved with a minimum mill time, thus the importance of cleaving through, or very close to, the region of interest. Otherwise, variations in the milling rates of different materials produce artifacts, often called “curtaining.”

Figure 3d

Figure 3d

Cross-section Mode When more than a few microns of material need to be removed, the BIB system is operated in “Cross-section” mode. This is commonly used when exposing a sub-surface target structure. Mechanical grinding causes mechanical artifacts and deformation from stress, making it difficult to obtain a smooth surface for SEM analysis. When using the cross-section milling holder, the BIB IM4000Plus shields part of the argon ion beam with the mask arranged on the specimen, and produces a cross section along the trailing edge of the mask into the sample. For Cross-section mode, targeting accuracy is approximately +/- 15μm.

Backside Milling Backside (as opposed to topside) milling mode can be used in both flat milling and cross-section modes. Backside milling is effective and necessary to alleviate curtaining effects[6] that can occur when traditional top-down ion milling induces striations. These striations are caused by the milling differential from neigh- boring materials that are atomically denser than the surrounding area. FIGURE 4 shows the direction of the ion beam during backside milling and the trench milled by the ion beam.

FIGURE 4. Copper bump after backside milling shows both the milling direction and the trench created by the ion beam

FIGURE 4. Copper bump after backside milling shows both the milling direction and the trench created by the ion beam

Case Study 1. Quick 5-minute HAC and Flat Milling for Cross Section Final Polish

In this example, a cross section was prepared of an Intel microprocessor removed from its package. The size of the sample available after deprocessing was 8 x 8mm. To prepare the cross section, the sample was cleaved parallel to 15μm contacts visible on the sample surface. The Hitachi IM4000 was then used to prepare the final surface using flat milling mode. Approximately 100nm of material was removed in 10 minutes to achieve the polished surface of the final cross section.

The cross-section process included:

1. Indenting the 15μm area of interest (AOI) with the LatticeAx (FIGURE 5a) (3 min)
2. Cleaving through the AOI using the small sample cleaving accessory[7] (2 min) (FIG 5b-c)
3. Mounting the sample for the IM4000Plus and backside milling using flat milling mode (15 min)

FIGURE 5a. Case Study 1 –HAC and flat milling processes for cross section final polish

FIGURE 5a. Case Study 1 –HAC and flat milling processes for cross section final polish

FIGURE 5b. View of sample after cleaving with the small sample cleaver

FIGURE 5b. View of sample after cleaving with the small sample cleaver

 

FIGURE 5c. Optical view of the cross section after cleaving

FIGURE 5c. Optical view of the cross section after cleaving

Results

This demonstrates a rapid (15-minute) method to obtain a damage-free cross section from a fully processed microprocessor over a very large area (5mm in diameter). A comparison of the results before and after milling shows the clear improvement in surface quality and SEM imaging results (FIGURE 5d and e). Using other methods such as mechanical polishing or FIB can take several hours to achieve a comparable size produced by the large flat-milled region. The best results were obtained when removing a minimum of material (nms), demonstrating the importance of an accurate, high quality cleave prior to BIB milling. FIGURE 5f shows a high-magnification view of the resulting cross section after flat milling that is high quality and without curtaining.

FIGURE 5d. SEM image of the microprocessor after cleaving

FIGURE 5d. SEM image of the microprocessor after cleaving

FIGURE 5e. SEM image of the microprocessor after 10 minutes of BIB milling using flat milling mode

FIGURE 5e. SEM image of the microprocessor after 10 minutes of BIB milling using flat milling mode

 

FIGURE 5f. SEM image showing planar cross section after flat milling

FIGURE 5f. SEM image showing planar cross section after flat milling

Case Study 2. Using HAC and BIB Milling in Cross-section Mode to Prepare Cross Sections of Solder Bumps

Cross sections are required to inspect solder bump reliability for interconnect problems during development and production, or for electromigration failure after aging. Creating these cross sections in a targeted location is critical for effective fault isolation and SEM analysis. With the advent of large Through Silicon-Via (TSV) and solder bump structures—often 100μm in depth or width—high throughput methods are necessary to make cross sections efficiently and effectively.[8]

In this case study, the solder bumps were prepared for SEM in a two-step process. In step 1, the LatticeAx cleaver was used to cleanly cross-section close to, and parallel to, a specific row of copper bumps. The copper bumps had a diameter of 85μm and were cleaved 30 μm from the center of a bump. Time to cleave was 5 minutes and yielded the results shown in FIGURE 6a and FIGURE 6b.

FIGURE 6a. SEM image of the microprocessor after cleaving

FIGURE 6a. SEM image of the microprocessor after cleaving

FIGURE 6b. SEM image of the microprocessor after cleaving

FIGURE 6b. SEM image of the microprocessor after cleaving

In step 2, a broad argon ion beam instrument, the Hitachi IM4000, was used to prepare the final imaging surface within the copper bump. The backside milling method was used; no further preparation was performed.

Results

FIGURES 6c and 6d, taken after ion milling, plainly show the improved surface quality and copper grain structures, as well as fine details at the interface between the bump and adjacent structures. By cleaving close to the center of the copper bumps, the milling time on the BIB was reduced to less than 2 hours versus tens of hours for large cross-section areas (multiple bumps).

This two-step sample preparation process described has been implemented in production by a large semiconductor manufacturer. The technique described reduces turn-around time and repeatedly results in artifact-free cross sections of copper solder bumps.

FIGURE 6c. SEM image of the microprocessor after cleaving

FIGURE 6c. SEM image of the microprocessor after cleaving

FIGURE 6d. SEM image of the microprocessor after cleaving

FIGURE 6d. SEM image of the microprocessor after cleaving

Conclusion

For “off-line” laboratories, using HAC and BIB together for creating high quality cross sections is a compelling, low-cost alternative to investments in FIBs or automated polishing or cleaving equipment. High accuracy cleaving reduces sample preparation time, complexity, and cost without sacrificing cross- section quality. Combining this with a broad argon ion beam instrument for quick removal of minimal amounts of material or for milling of large flat areas, HAC presents effective, accurate results critical to product or failure analysis, while keeping both equipment and per-sample costs low.

Whether for final polish or in sample preparation of solder bumps, the results from the machine-assisted high accuracy Indent and Cleave approach combined with broad ion beam milling rival those of fully automated cleaving or polishing systems

References

1. Per industry sources
2. Approximate costs: FIB/SEM at $1-2 million; Automated HAC at $300,000; HAC+BIB milling tool at $160,000.
3. Cleaving Breakthrough: A New Method Removes Old Limitations, E. Moyal, E. Brandstädt, EDFAAO (2014) 3:26-31
4. Energy-dispersive X-ray spectroscopy
5. Electron backscatter pattern
6. CAVolkert and AM Minor, MRS Bull 32(5) (2007) 389–99.
7. The small sample cleaving accessory is used to clamp samples as small as 4mm wide for indenting with the LatticeAx and cleaving using a separate cleaving base. 8. Sample Preparation of Semiconductor Materials with a New Site-specific Cleaving Technology, Microscopy Today, September 2013, Teshima et al., 56-59.

J. TESHIMA is with LatticeGear, LLC., 1500 NW Bethany Blvd., Suite 200, Beaverton, OR 97006, USA. JAMIL J. CLARKE is with Hitachi High Technologies America, Inc., Nanotechnology Systems Division, 22610 Gateway Center, Dr. Clarksburg, MD 20871, USA

LSA technology plays an enabling role to overcoming manufacturing challenges for sub-20nm logic devices. 

By YUN WANG, Ph.D., Ultratech, San Jose, CA

Sub-20nm system-on-chip and FinFET devices have specific manufacturing challenges that can be resolved with laser spike annealing (LSA) technology. Over the last decade, new process technologies and materials have emerged, such as strained silicon, high-k/metal gate (HKMG) and advanced silicide. Meanwhile transistor structures have evolved significantly, from bulk planar and PDSOI to 3D FinFET. With dimensions approaching atomic scales, the need for low thermal budget processes offered by millisecond annealing (MSA) becomes more important to precisely control the impurity profiles and engineer interfaces. This article will explain how LSA technology plays an enabling role to overcoming manufacturing challenges for sub-20nm logic devices.

LSA and MSA

The European semiconductor equipment market is expected to grow along with the world market. Global capital spending on semiconductor equipment is projected to grow 21.1 percent in 2014 and 21.0 percent in 2015. According to the August edition of the SEMI World Fab Forecast, semiconductor equipment spending will increase from $29 billion in 2013 to $42 billion in 2015.

In this article the terms LSA and MSA are used interchangeably. MSA can be implemented either by a scanning laser or a bank of flash lamps (FIGURE 1). In both cases, a reduced volume of substrate is heated to high temperature by a powerful light source, which results in fast temperature ramping compared to conventional RTP. Surface cooling in the millisecond time scale is dominated by conductive heat dissipation through the lower temperature substrate, which is several orders of magnitude faster than radiation heat loss or convection cooling through surfaces. The wafer backside is typically heated by a hot chuck or lamps to reduce the front surface peak temperature jump, and in some cases, to reduce the flash lamp power requirement or facilitate laser light absorption. Flash usually requires higher backside heating temperature than the laser option.

FIGURE 1. Simulated temperature distribution in silicon substrate by millisecond nonmelt scanning laser (left) and flash lamp heating (right).

FIGURE 1. Simulated temperature distribution in silicon substrate by millisecond nonmelt scanning laser (left) and flash lamp heating (right).

There are important differences between flash and laser approaches. The flash system provides global heating where the top surface of the entire wafer is heated at the same time. Hence heat dissipation occurs only in one dimension (1D – vertical direction). In addition, the backside needs to be floated to relieve the stress caused by global wafer bending due to the vertical thermal gradient. The laser system, on the other hand, provides localized heating around the scanning beam. The heat dissipation is between two-dimensional (2D) and three-dimensional (3D) (2D for an infinitely long line beam, and 3D for a point source). Since the thermal stress is localized, the backside can be chucked to facilitate heat sinking.

The difference in heat dissipation has a significant impact on the cooling rate, in particular, when long annealing or high intermediate (preheat) temperature is used. FIGURE 2 compares the temperature (T) profiles between laser and flash systems for the same peak surface temperature (Tpk) and dwell time (tdwell— defined as the full-width-half-maximum duration when a fixed point on the wafer sees the laser beam or flash pulse). The latter shows much slower ramp down. This is because once the flash energy is dissipated through the wafer thickness, the cooling is limited by the same radiation loss mechanism as in RTP. For applications relying on non-equilibrium dopant activation, the extra thermal budget due to the slow ramp down could be a concern for deactivation.

FIGURE 2. Comparison of simulated temperature profiles between long dwell laser and flash annealing. Tpk = 1200°C, dwell time = 10ms, preheat T = 800°C for flash. Inset shows details magnified around peak temperature.

FIGURE 2. Comparison of simulated temperature profiles between long dwell laser and flash annealing. Tpk = 1200°C, dwell time = 10ms, preheat T = 800°C for flash. Inset shows details magnified around peak temperature.

LSA technology uses a long wavelength p-polarized CO2 laser with Brewster angle incidence. Previous studies have shown that such configuration has benefits of reduced pattern density effect compared to short wavelength with near normal incidence. A second beam can be added to form a dual beam system that allows more flexibility to adjust the temperature profiles, and expands the process capability to low T and long dwell time.

FIGURE 3 shows different LSA annealing temperature-time (T-t) regimes that can be used to meet various application needs. Standard LSA used in front-end applications has Tpk ranging from 1050~1350°C and tdwell from 0.2~2ms. Short dwell time is beneficial for reducing wafer warpage and litho misalignment, especially for devices with high strain. Long dwell time (2~40ms) adds more thermal budget for defect curing. It can also be used to improve activation and fine tune the junction depth. The low T regime enables applications that require lower substrate and peak annealing temperatures, such as annealing of advanced silicide or new channel/gate stack materials that have poor thermal stability.

FIGURE 3. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

FIGURE 3. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

High-k/metal gate (HKMG)

The impact of MSA on HKMG is thinner equivalent oxide thickness (EOT) due to reduced interfacial layer growth from a lower thermal budget. Lower leakage and better surface morphology are also observed in hafnium-based, high-k films when annealed by a laser.

Incorporating nitrogen into a high-k dielectric film can improve thermal stability, reliability, and EOT scaling. Post nitridation anneal with MSA provides opportunities to stabilize the film with a more precisely controlled nitrogen profile, which is important since excessive nitrogen diffusion can increase interface trap and leakage. Oxygen has a strong impact on the characteristics of HKMG and it is important to control the ambient environment during the gate annealing. Full ambient control capability has been developed for LSA to accommodate this need. FIGURE 4 shows the schematics of our patented micro-chamber approach that allows ambient control to be implemented in a scanning system using non-contact gas bearing. Different process gas can be introduced to accommodate various annealing and material engineering needs.

FIGURE 4. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

FIGURE 4. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

Advanced silicide

Conventional NiSi processing involves two RTA steps. The 1st RTA (200~300°C) forms Ni-rich silicide, and the 2nd RTA (400~500°C) after selective etch of un-reacted Ni forms the desired low resistance NiSi phase. By replacing the 2nd RTA with a high temperature MSA (700~900°C), it can reduce leakage as well as improve performance. The improvement in leakage distribution results from the statistical reduction of Ni pipe defects due to the low thermal budget of MSA.

High temperature promotes phase mixing of Si-rich Ni silicide at the silicide/Si interface and lowers Schottky barrier height (SBH). In conventional RTA, this requires T > 750°C; such high T would lead to morphology degradation, excess diffusion, and higher resistivity. With MSA, because of the short duration, agglomeration does not occur until ~900°C.

To maximize the performance gain, anneal at high T close to the agglomeration threshold is desired. In such a case, minimizing within-die pattern effects and implementing within-wafer and wafer to-wafer temperature control becomes very important.

FinFETs

As FinFETs shrink, interface contact resistance, Rc, becomes more critical (FIGURE 5). A promising path to lower Rc is interface engineering by dopant segregation using pre or post silicide implantation.

FIGURE 5. Parasitic resistance components for different nodes of FinFET, calculated using an analytical model. of 10-8 -cm2 is used.

FIGURE 5. Parasitic resistance components for different nodes of FinFET, calculated using an analytical model. of 10-8 -cm2 is used.

FIGURE 6. SIMS profiles of Ga-doped (left) p+/n and As-doped (right) n+/p Ge junctions annealed by LSA. For Ga, no diffusion is observed. For As, concentration enhanced diffusion is observed but can be reduced with short dwell time.

FIGURE 6. SIMS profiles of Ga-doped (left) p+/n and As-doped (right) n+/p Ge junctions annealed by LSA. For Ga, no diffusion is observed. For As, concentration enhanced diffusion is observed but can be reduced with short dwell time.

 

Thermal annealing is necessary to repair implant damage and activate dopants in pre silicide implantation scheme, and to drive-in dopants in post silicide case. Using MSA instead of RTA results in more precise dopant profile control, higher dopant concentration at the interface and less potential silicide defectivity, due to the lower thermal budget.

Recently, Ti re-emerged as an option for contact metal because of better thermal stability and potential lower SBH. LSA can be applied to form low Rc Ti/Si contact. In advanced FinFET flow where contacts are formed after source/drain activation and gate stack, low thermal budget process is beneficial to minimize dopant deactivation and unintentional gate work function shift.

In-situ doped selective epitaxial growth is increasingly used to form the raised source/drain for FinFET. There is, however, a limitation in the maximum activation level it can achieve. Activation can be improved using MSA in combination with additional implantation. Drastic FinFET performance improvement has been achieved with co-optimization of conformal doping, selective epitaxial growth, implantation and MSA. In addition to front-end and middle-of-line applications, there are also opportunities at the back-end. One example is low-k curing. For FinFET, low-k is important not only as an inter-Cu dielectric, but also as a transistor-level dielectric to minimize the parasitic capacitance arising from 3D topography. The modulus and hardness of the low-k films can be improved without adversely impacting the k value using MSA.

New channel materials

Below the 10nm technology node, new materials with enhanced transportation, such as SiGe/Ge and III-V compounds, may be needed to meet the performance requirements. These materials have low thermal stability and are lattice mis-matched with the Si substrate, as a result physical integrity during thermal annealing is a very big concern. Low thermal budget processing by MSA provides a way to alleviate this issue. For example, studies on SiGe/Si heterostructures have shown that MSA can enable a higher annealing temperature than RTA, without strain relaxation or structural degradation. This results in improved activation. With MSA, junctions with enhanced activation and reduced diffusion can be obtained.

Summary

We have reviewed various applications of millisecond annealing for advanced device fabrication. As new materials emerge and device dimensions approach the atomic scale, precise thermal budget control becomes critical. This opens new opportunities for short time scale annealing. In addition to the traditional dopant activation and impurity profile control, MSA can also be used for interface engineering and material property modifications (structural, electrical, chemical, and mechanical). In general, if a desired process has higher thermal activation energy than an undesired process, application of high temperature, short duration annealing is beneficial.

YUN WANG, Ph.D., is Senior Vice President and Chief Technologist of Laser Processing Ultratech, San Jose, CA.

By Douglas G. Sutherland and David W. Price

Author’s Note: This is the fourth in a series of 10 installments that explore fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights their implications. Within this article we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

Nobody likes surprises—especially the managers of $10 billion factories. In a dynamic field like advanced semiconductor IC fabrication, there will always be unknowns. However, it is critical to know what you know and know what you don’t know. Every measurement has error. The quality of the decision you make is highly dependent on the uncertainty in the data used to make that decision.

Process control spending is discretionary. Fabs will invest to the point that they believe the return on investment is favorable. It may make financial sense to sample less, skip certain measurements, or use a less capable inspection/metrology tool. However, the fab must always face facts and quantify the level of risk associated with these decisions. The stakes—missing an excursion resulting in costly yield loss—are too high to live in denial.

The fourth fundamental truth of process control for the semiconductor IC industry is: 

Always quantify your lots at risk when making changes to your process control strategy

Quantifying your lots at risk equates to understanding the uncertainty in your measurement. This is a basic concept that most factory engineers learned at some point during their education, however, it is also one of the most tedious of tasks. As a result, this portion of the analysis is skipped more often than we care to admit.

Within process control there are really only two types of risk: Alpha risk and Beta risk. Alpha risk is a false alarm; it is when your inspection tells you that the wafer measured is out of control when really there is nothing wrong with the larger process. Beta risk is the opposite of this; it is when your inspection tells you that the wafer you measured was in control but really there is a serious problem. Figure 1 summarizes the difference.

KLAT_FIGURES-1

Figure 1. Definition of Alpha risk and Beta Risk

Alpha and Beta risk arise as a result of the inability to consistently make an inspection that accurately represents the process at that point in time. The best way to reduce both types of risk is to make the process itself less variable. There are few, if any, activities in semiconductor manufacturing that are more value-added than driving variability out of the process. It is much easier to spot real changes in the process when the native lot-to-lot variation is low. However, this cannot always be easily achieved and the Alpha risk (the number of false alarms) can sometimes only be reduced by moving the control limits further from the target (raising the upper control limit and / or lowering the lower control limit). Increasing the spread between the control limits will reduce the Alpha risk but it comes at the expense of increasing the Beta risk—it makes the inspection process less sensitive to real excursions.

Just as changing the native variability in the process usually warrants reassessing where to place the control limits, any time the characteristics of the measurement itself are changed (changing the sensitivity of the recipe, changing the area of the wafer that is inspected, changing the size of the review sample, etc.) the position of the control limits also needs to be re-evaluated.

As an example, consider a defect inspection step where 100 percent of the wafer area is inspected. For a particular defect of interest (DOI) the inspection finds between 40 and 60 DOI on each wafer under normal conditions and the upper control limit (UCL) is placed at 61. If the inspection strategy is changed such that further inspections will only sample 50 percent of the wafer area, the range of normal values will change from between 40 and 60 to between 12 and 42 for 50 percent area (or 24 and 84 when normalized back to the full wafer count). The increase in range is a result of the Binomial Probability Theory that quantifies the effect that sometimes there will be a disproportionate number of DOI in the area that was inspected and sometimes there will be a disproportionate number of DOI in the area that was not inspected.

With the stroke of a pen, the decision to reduce the wafer area to 50 percent has tripled the variability in this particular part of the process from a range of 20 to a range of 60 DOI per wafer. In doing so, they have undone months of hard work by a team of engineers who worked diligently to drive the variability out of the process in the first place. The fab manager must now choose to keep the UCL at 61 and suffer many more false alarms or raise the UCL to 85 where they will have approximately the same number of false alarms but be much less sensitive to real excursions.

The impact of changing the inspected wafer area depends on several factors including the average DOI, the native variation and the size of the excursion that one is trying to detect. Figure 2 shows how the percent error changes as a function of wafer area for three different DOI counts.

KLAT_FIGURES-2

Figure 2.  Percent Error versus Wafer Area for three different DOI counts.  At 100 percent area there is no error introduced into the measurement. As the area decreases, the error increases. The error is largest for low DOI counts and is bounded by -100% on the low side and unbounded on the high side.

We have chosen the example of wafer area to illustrate the point because it is such a common practice but the same principles apply to all aspects of process control. The measurement is part of the process― when you degrade the quality of the measurement you degrade the quality of the process.

There are many ways in which process control risk manifests itself in the fab. One simple approach is to get in the habit of asking the questions: “how many lots are at risk if I do this?” and, “what are the error bars on this analysis?”

For example, how many lots are at risk if the fab:

  • Skips an inspection step?
  • Uses a less sensitive inspector or pixel size?
  • Reduces the sampling rate?
  • Use a less precise metrology tool?
  • Measure fewer features per wafer?

Changing process control strategy to reduce costs may seem like a short term solution but it is seldom if ever sustainable for one very simple reason: fab managers don’t like surprises!

References:

1)     You Can’t Fix What You Can’t Find, Solid State Technology, July 2014

2)     Sampling Matters, Semiconductor Manufacturing and Design, September 2014

3)     The Most Expensive Defect, Solid State Technology, December 2014

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Process Watch blog series: 

Process Watch: The 10 fundamental truths of process control for the semiconductor IC industry

Process Watch: Exploring the dark side

“The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

The semiconductor equipment and materials industry is currently enjoying a double-digit annual growth rate and good prospects looking forward to 2015.  However, there are huge challenges around the corner with the move from planar to FinFET transistors, with 193nm immersion lithography being pushed well below 14nm, and with an explosion of new materials to integrate, among others.

The SEMI International Technology Partners Conference (ITPC 2014) convened on 9-12 November on the bright and crystalline Kohala Coast of the Big Island of Hawaii.  Like our industry, all looked calm and peaceful – yet just around the corner, the Kilauea Volcano was violently reshaping the landscape with rivers of molten lava in the town of Pahoa.

Living in the shadow of an active volcano and the sometimes spectacularly disruptive process of building an island – or the nano-electronics manufacturing industry in our case – was picked up in this year’s ITPC theme:  New Structures for Innovation.  Wholly new concepts for collaboration and partnerships to address the challenges and to enable innovation were discussed formally in the conference, as well as informally in the many networking opportunities.

The program included keynote presentations by driving IC manufacturers:  Intel, SMIC, SK Hynix, TSMC, and Micron to set the stage for the rest of the program by hitting the key issues:

  • Delivering density scaling benefits in an era of increased capital intensity and materials complexity (Intel and SMIC)
  • Trends in semiconductor development following changes in the mobile market (SK Hynix)
  • Limits of lithography beyond the 10nm node (TSMC)
  • Collaboration for innovation (Micron)

Each of these keynote presentations neatly distilled the related challenges and opportunities and provided richly provocative observations on what is needed to keep innovation as the fundamental enabler.

Beyond the exceptional insights and depth of these presentations, a few “fun facts” were captured below.

  • Intel’s pursuit of 450mmm has had a positive impact on 300mm productivity (Bob Bruck, Intel)
  • China’s overall two highest revenue imports are oil and ICs  (Tzu-Yin Chiu, SMIC)
  • To succeed in today’s IC manufacturing world there needs to be system-level and process-level partnership and collaboration across the extended supply chain  (Sungwook Park, SK Hynix)
  • Of the Fortune 500 companies from 30 years ago, only 15% remain today.  Large companies are often too slow to react to change (Mark Adams, Micron)
  • Facebook and Google are now among the top six server manufacturers in the world (Mark Adams, Micron)

The conference continued with an industry and market outlook segment with special attention to IoT, electric vehicles, and nanoelectronics “connecting lives to improving lives.”  This included some amazing video clips of Nissan’s autonomous driving electric vehicles in Japan traffic, and imec’s intense visualizations of next generation nano-bio applications.

Among the best appreciated sections, was the segment on new industry structure that featured speakers and panelists from Google (David Peterson), Robert Metcalfe (University of Texas), Dan Solomon (Solomon Consulting), and AlixPartners (Dan Fisher). David Peterson brought a perspective from outside of our industry which is useful to test ideas and refresh approaches. He asked the audience to start with the most difficult ideas: make the tough choices, ask the questions that no one else will, and nurture a vibrant, distinctive culture. On making the tough choice, he was specific – and it is indeed tough, “sub-optimize current performance to invest in future performance:  innovations, R&D, learning, leadership development, building an adaptable organization, experimenting with ideas and projects that may not succeed. This segment was capped by Shozo Saito (Toshiba) providing an overview on the connections of new market and industry structure by device platform development.

The final segment focused on technology with Frits van Hout of ASML presenting the EUVL transition from R&D to industrialization. Following this a panel, moderated by Dan Hutcheson of VLSI Research, focused on frontiers of technology with panelists Paul Boudre of Soitec, David Hemker of Lam Research, Michael Liehr of CNSE, and Omkaram Nalamasu of Applied Materials.

It was a fascinating conference that both discussed the need and models for new collaboration and partnerships – and brought our industry’s thought leaders together to have opportunities to find these connections during the conference.

A few more interesting “fun facts” “fun bits” from the conference:

  • China plans to spend $100B to build a China-local IC industry that will supply up to 40% of China’s IC consumption.
  • The era of planar technology is coming to an end – and this precipitates great changes.
  • There is virtually no viable small company R&D engine model remaining in ICs and semiconductor equipment.  The model for innovation in our industry has significantly changed in the last five years.
  • Collaborations and partnerships are more essential now than ever before for developing innovation.
  • To build trust in developing partnerships, potential partners should work together and take many small risks together quickly.
  • Among the top innovations in our industry is Moore’s law and inventing SEMI – this is one of the big successes in collaboration and co-opetition.
  • A twelve week cycle from tape-out to finished wafer is too long.  This must change to keep pace with product development innovation.
  • The semiconductor industry should quickly work to define standards/platforms for IOT to ensure the pace of growth and chip consumption
  • A favorite slide was from Google that reminded the audience that to win, we have to view any customer problem as our problem:

ITPC

To participate in other strategic events, consider the SEMI Industry Strategy Symposium U.S. 2015 in January or SEMI Industry Strategy Symposium Europe 2015 in February.

3D TSV begins


December 10, 2014

3D TSV integration has already been adopted in MEMS and CMOS Image Sensors for consumer applications (Source: 3DIC & 2.5D TSV Interconnect for Advanced Packaging Business Update report). Device makers such as Sony, Toshiba, Omnivision, Samsung, Bosch Sensortec, STMicroelectronics and mCube … have all brought devices to the market that integrate 3D TSV technology.

“TSV’s added- value is important: increased performance and functionality, more compact devices, more efficient utilization of the silicon space,” explained Yole Développement (Yole). Moreover, even if 3D TSV process steps are adding cost at the device manufacturing level, these technologies enable cost- saving in other parts of the supply chain.

tsv

“No more doubts about adoption of 3D TSV platform across a wider range of applications: all key players added 3D TSV into their roadmaps, engineering samples have already started to ship and preparation is on-going for entering volume manufacturing,” said Rozalia Beica, CTO & Business Director, Advanced Packaging and Semiconductor Manufacturing at Yole. This year, the industry witnessed several memory product announcements for high-end applications, with transfer to volume production planned in the near future.

“Driven by the demand to further increase in performance, 2015 will be the year for the implementation of 3D TSV technology in high volume production,” explains Rozalia.

The market research and strategy consulting company, Yole and its advanced packaging team, are closely studying and monitoring the industry’s activities in this field. The latest results can be found in Yole’s new 3DIC & 2.5D Business Update Report published this year.

Yole’s vision on further 3D TSV technology adoption will be presented during the European 3D TSV Summit 2015 in Grenoble. The company is partnering with SEMI to support the European TSV Summit, which will take place in Grenoble, France on January 19 to 21, 2015. The European 3D TSV Summit is organized by SEMI Europe. To meet Yole’s experts, discover the detailed program and register, click European 3D TSV Summit 2015.

Also, at the European 3D TSV Summit, Jean-Christophe Eloy, President & CEO, Yole will moderate the panel discussion, “From TSV Technology to Final Products – What is the Business for 3D Smart Systems?” taking place on Tuesday 20, at 5:20 PM. Jean-Christophe will highlight 3D TSV market trends and technology challenges, especially its integration for 3D smart systems application. He will welcome the following panelists: Ron Huemoeller, Senior VP Advanced Product / Platform Development, AMKOR – Martin Schrems, VP of R&D, ams AG – Bryan Black, Senior Fellow, AMD – Mustafa Badaroglu, Senior Program Manager, Qualcomm.

In parallel, Rozalia Beica will be part of the Market Briefing Symposium, on Monday 19. Her presentation is entitled: “From Development to Manufacturing: An Overview of Industry’s 3D Packaging Activities”.

“We are excited to have a group of highly qualified market experts, such as Yole Développement, joining us this year for the European 3D TSV Summit,” stated Anne-Marie Dutron, Director of SEMI Europe’s Grenoble office. “To highlight the adoption of 3D TSV technology in several market applications and to answer the demand from our members, we have given the business aspects of the 3D TSV industry more importance in this 2015 edition.”

The European 3D TSV Summit final program is now available.

The Semiconductor Industry Association (SIA) today announced that worldwide sales of semiconductors reached $29.7 billion for the month of October 2014, an increase of 9.6 percent from the October 2013 total of $27.1 billion and an uptick of 1.5 percent compared to last month’s total of $29.2 billion.

Sales in the Americas increased 12.2 percent year-over-year in October, leading all regions. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, a new WSTS industry forecast projects substantial growth for 2014 and moderate growth for 2015 and 2016.

“Year-over-year global semiconductor sales increased for the eighteenth straight month in October, and the industry is well-positioned for a strong close to 2014,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “Sales continue to be strong across the board, with nearly all regions and product categories exhibiting increases. We expect nearly double-digit growth in 2014, followed by moderate growth in 2015 and 2016.”

Regionally, sequential monthly sales increased in the Americas (5.8 percent) and remained roughly flat in Asia Pacific (up 0.7 percent), Europe (down 0.1 percent), and Japan (down 0.6 percent). Compared to October 2013, sales increased in the Americas (12.2 percent) as noted above, Asia Pacific (12.1 percent), and Europe(5.2 percent), but decreased in Japan (-3 percent).

Additionally, SIA today endorsed the WSTS Autumn 2014 global semiconductor sales forecast, which projects the industry’s worldwide sales will reach $333.2 billion in 2014, a 9 percent increase from the 2013 sales total. WSTS predicts year-over-year increases for 2014 in Asia Pacific (11.4 percent), Europe (8.7 percent), the Americas (6.9 percent), and Japan (1.3 percent).

Beyond 2014, the industry is expected to grow steadily and moderately across all regions, according to the WSTS forecast. WSTS predicts 3.4 percent growth globally for 2015 ($344.5 billion in total sales) and 3.1 percent growth for 2016 ($355.3 billion). WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

October 2014
Billions
Month-to-Month Sales
Market Last Month Current Month % Change
Americas 6.06 6.41 5.8%
Europe 3.21 3.21 -0.1%
Japan 3.03 3.01 -0.6%
Asia Pacific 16.93 17.05 0.7%
Total 29.23 29.69 1.5%
Year-to-Year Sales
Market Last Year Current Month % Change
Americas 5.71 6.41 12.2%
Europe 3.05 3.21 5.2%
Japan 3.11 3.01 -3.0%
Asia Pacific 15.22 17.05 12.1%
Total 27.09 29.69 9.6%
Three-Month-Moving Average Sales
Market May/Jun/Jul Aug/Sep/Oct % Change
Americas 5.47 6.41 17.2%
Europe 3.24 3.21 -1.1%
Japan 3.04 3.01 -0.9%
Asia Pacific 16.38 17.05 4.1%
Total 28.13 29.69 5.5%

WSTS Autumn 2014 Forecast

Autumn 2014 Amounts in US$M Year on Year Growth in %
2013 2014 2015 2016 2013 2014 2015 2016
Americas 61,496 65,763 69,274 71,432 13.1 6.9 5.3 3.1
Europe 34,883 37,923 38,491 39,732 5.2 8.7 1.5 3.2
Japan 34,795 35,239 35,133 35,452 15.2 1.3 -0.3 0.9
Asia Pacific 174,410 194,226 201,648 208,656 7.0 11.4 3.8 3.5
Total World – $M 305,584 333,151 344,547 355,272 4.8 9.0 3.4 3.1
Discrete Semiconductors 18,201 20,441 21,347 21,980 -4.9 12.3 4.4 3.0
Optoelectronics 27,571 29,498 30,958 31,983 5.3 7.0 4.9 3.3
Sensors 8,036 8,627 9,151 9,624 0.3 7.4 6.1 5.2
Integrated Circuits 251,776 274,586 283,090 291,685 5.7 9.1 3.1 3.0
Analog 40,117 44,217 47,429 49,175 2.1 10.2 7.3 3.7
Micro 58,688 62,211 63,144 64,240 -2.6 6.0 1.5 1.7
Logic 85,928 89,547 91,488 93,927 5.2 4.2 2.2 2.7
Memory 67,043 78,611 81,029 84,343 17.6 17.3 3.1 4.1
Total Products – $M 305,584 333,151 344,547 355,272 4.8 9.0 3.4 3.1

The semiconductor industry directly employs nearly a quarter of a million people in the United States. In 2013, U.S. semiconductor company sales totaled $155 billion, and semiconductors make the global trillion dollar electronics industry possible. Founded in 1977 by five microelectronics pioneers, SIA unites companies that account for 80 percent of America’s semiconductor production.

Cypress Semiconductor Corp. and Spansion, Inc. this week announced a definitive agreement to merge in an all-stock, tax-free transaction valued at approximately $4 billion. The post-merger company will generate more than $2 billion in revenue annually.

“This merger represents the combination of two smart, profitable, passionately entrepreneurial companies that are No. 1 in their respective memory markets and have successfully diversified into embedded processing,” said Rodgers, Cypress’s founding president and CEO. “Our combined company will be a leading provider of embedded MCUs and specialized memories. We will also have extraordinary opportunities for EPS accretion due to the synergy in virtually every area of our enterprises.”

Under the terms of the agreement, Spansion shareholders will receive 2.457 Cypress shares for each Spansion share they own. The shareholders of each company will own approximately 50 percent of the post-merger company. The company will have an eight-person board of directors consisting of four Cypress directors, including T.J. Rodgers and Eric Benhamou, and four Spansion directors, including John Kispert and Ray Bingham, the Spansion chairman, who will serve as the non-executive chairman of the combined company, which will be headquartered in San Jose, California and called Cypress Semiconductor Corporation.

The merger is expected to achieve more than $135 million in cost synergies on an annualized basis within three years and to be accretive to non-GAAP earnings within the first full year after the transaction closes. The combined company will continue to pay $0.11per share in quarterly dividends to shareholders.

“Bringing together these high-performing organizations creates operating efficiencies and economies of scale, and will deliver maximum value for our shareholders, new opportunities for employees and an improved experience for our customers,” said John Kispert, CEO of Spansion. “With unparalleled expertise, global reach in markets like Japan and market-leading products for automotive, IoT, industrial and communications markets, the new company is well positioned to deliver best-of-breed solutions and execute on our long-term vision of adding value through embedded system-on-chip solutions.”

The closing of the transaction is subject to customary conditions, including approval by Cypress and Spansion stockholders and review by regulators in the U.S., Germany and China. The transaction has been unanimously approved by the boards of directors of both companies. Cypress and Spansion expect the deal to close in the first half of 2015.

Jefferies LLC and Morgan Stanley & Co. LLC served as financial advisors and Fenwick & West and Latham & Watkins acted as legal counsel to Spansion. Qatalyst Partners acted as financial advisor and Wilson Sonsini Goodrich & Rosati acted as legal counsel to Cypress.

Soitec and CEA-Leti, along with the Fraunhofer Institute for Solar Energy Systems ISE, announced a new world record for the direct conversion of sunlight into electricity has been established. The record multi-junction solar cell converts 46 % of the solar light into electrical energy. Multi-junction cells are used in concentrator photovoltaic (CPV) systems to produce low-cost electricity in photovoltaic power plants, in regions with a large amount of direct solar radiation. The achievement of a new world record one year after the one previously announced in September 2013 by these French and German partners shows the strong competitiveness of the European photovoltaic research and industry.

Multi-junction solar cells are based on a selection of III-V compound semiconductor materials. The world record cell is a four-junction cell, and each of its sub-cells converts precisely one quarter of the incoming photons in the wavelength range between 300 and 1750 nm into electricity. When applied in concentrator PV, a very small cell is used with a Fresnel lens, which concentrates the sunlight onto the cell. The new record 46.0% efficiency was measured at a concentration of 508 suns and has been confirmed by the Japanese AIST (National Institute of Advanced Industrial Science and Technology), one of the leading centers for independent verification of solar cell performance results under standard-testing conditions.

A special challenge that had to be met by this cell is the exact distribution of the photons among the four sub-cells. This has been achieved by precise tuning of the composition and thicknesses of each layer inside the cell structure. “This is a major milestone for our French-German collaboration. We are extremely pleased to hear that our result of 46% efficiency has now been independently confirmed by AIST in Japan”, explains Dr. Frank Dimroth, project manager for the cell development at the German Fraunhofer Institute for Solar Energy Systems ISE. “CPV is the most efficient solar technology today and suitable for all countries with high direct normal irradiance.”

Jocelyne Wasselin, Vice President Solar Cell Product Development for Soitec, a company headquartered in France and a world leader in high performance semiconductor materials, said: “We are very proud of this new world record. It confirms we made the right technology choice when we decided to develop this four-junction solar cell, and clearly indicates that we can demonstrate a 50% efficiency in the near future”.

She added: “To produce this new generation of solar cells, we have already installed a line in France. It uses our bonding and layer-transfer technologies and already employs more than 25 engineers and technicians. I have no doubt that this successful cooperation with our French and German partners will drive further increase of CPV technology efficiency and competitiveness.”

New record solar cell on a 100 mm wafer yielding approximately 500 concentrator solar cell devices. ©Fraunhofer ISE/Photo Alexander Wekkeli

New record solar cell on a 100 mm wafer yielding approximately 500 concentrator solar cell devices. ©Fraunhofer ISE/Photo Alexander Wekkeli